Lines Matching refs:priv
465 static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8192eu_identify_chip() argument
467 struct device *dev = &priv->udev->dev; in rtl8192eu_identify_chip()
471 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_identify_chip()
472 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192eu_identify_chip()
479 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); in rtl8192eu_identify_chip()
482 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
483 priv->tx_paths = 1; in rtl8192eu_identify_chip()
484 priv->rtl_chip = RTL8191E; in rtl8192eu_identify_chip()
486 strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
487 priv->tx_paths = 2; in rtl8192eu_identify_chip()
488 priv->rtl_chip = RTL8192E; in rtl8192eu_identify_chip()
490 priv->rf_paths = 2; in rtl8192eu_identify_chip()
491 priv->rx_paths = 2; in rtl8192eu_identify_chip()
492 priv->has_wifi = 1; in rtl8192eu_identify_chip()
495 rtl8xxxu_identify_vendor_2bits(priv, vendor); in rtl8192eu_identify_chip()
497 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192eu_identify_chip()
498 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
500 rtl8xxxu_config_endpoints_sie(priv); in rtl8192eu_identify_chip()
505 if (!priv->ep_tx_count) in rtl8192eu_identify_chip()
506 ret = rtl8xxxu_config_endpoints_no_sie(priv); in rtl8192eu_identify_chip()
513 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8192e_set_tx_power() argument
522 cck = priv->cck_tx_power_index_A[group]; in rtl8192e_set_tx_power()
524 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
527 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
529 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
532 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
534 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
535 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; in rtl8192e_set_tx_power()
538 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8192e_set_tx_power()
539 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8192e_set_tx_power()
541 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
543 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
545 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
548 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
549 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
550 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
551 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
553 if (priv->tx_paths > 1) { in rtl8192e_set_tx_power()
554 cck = priv->cck_tx_power_index_B[group]; in rtl8192e_set_tx_power()
556 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
559 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
561 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
564 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
566 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
567 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8192e_set_tx_power()
571 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); in rtl8192e_set_tx_power()
572 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); in rtl8192e_set_tx_power()
574 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
576 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
578 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
581 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
582 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
583 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
584 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
588 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8192eu_parse_efuse() argument
590 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; in rtl8192eu_parse_efuse()
596 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8192eu_parse_efuse()
598 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8192eu_parse_efuse()
600 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8192eu_parse_efuse()
603 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8192eu_parse_efuse()
606 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8192eu_parse_efuse()
610 priv->ht20_tx_power_diff[0].a = in rtl8192eu_parse_efuse()
612 priv->ht20_tx_power_diff[0].b = in rtl8192eu_parse_efuse()
615 priv->ht40_tx_power_diff[0].a = 0; in rtl8192eu_parse_efuse()
616 priv->ht40_tx_power_diff[0].b = 0; in rtl8192eu_parse_efuse()
619 priv->ofdm_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
621 priv->ofdm_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
624 priv->ht20_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
626 priv->ht20_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
629 priv->ht40_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
631 priv->ht40_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
635 priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; in rtl8192eu_parse_efuse()
640 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8192eu_load_firmware() argument
647 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8192eu_load_firmware()
652 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_bb() argument
657 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
659 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
663 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
665 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
668 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
670 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
671 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); in rtl8192eu_init_phy_bb()
673 if (priv->hi_pa) in rtl8192eu_init_phy_bb()
674 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); in rtl8192eu_init_phy_bb()
676 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); in rtl8192eu_init_phy_bb()
679 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_rf() argument
683 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); in rtl8192eu_init_phy_rf()
687 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); in rtl8192eu_init_phy_rf()
693 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_a() argument
702 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
703 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180); in rtl8192eu_iqk_path_a()
705 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_iqk_path_a()
706 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8192eu_iqk_path_a()
707 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_iqk_path_a()
708 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77); in rtl8192eu_iqk_path_a()
710 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
713 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_iqk_path_a()
714 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_a()
715 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
716 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
718 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); in rtl8192eu_iqk_path_a()
719 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); in rtl8192eu_iqk_path_a()
722 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_a()
725 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_iqk_path_a()
726 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_a()
731 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_a()
732 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_iqk_path_a()
733 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_iqk_path_a()
743 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_a() argument
749 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
752 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
753 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
754 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
755 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_a()
757 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
758 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
759 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
760 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_a()
763 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_a()
764 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0); in rtl8192eu_rx_iqk_path_a()
767 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
770 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_a()
771 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
774 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
775 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
776 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
777 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
779 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f); in rtl8192eu_rx_iqk_path_a()
780 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f); in rtl8192eu_rx_iqk_path_a()
783 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_a()
786 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_rx_iqk_path_a()
787 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
792 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
793 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_rx_iqk_path_a()
794 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_rx_iqk_path_a()
802 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
803 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_a()
809 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
812 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
814 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
815 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
816 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
817 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_a()
819 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
820 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
821 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
822 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_a()
825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_a()
826 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0); in rtl8192eu_rx_iqk_path_a()
829 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
832 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
835 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
836 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
837 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
838 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
840 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); in rtl8192eu_rx_iqk_path_a()
841 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); in rtl8192eu_rx_iqk_path_a()
844 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_a()
847 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_rx_iqk_path_a()
848 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
852 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
853 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
855 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
856 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_a()
863 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", in rtl8192eu_rx_iqk_path_a()
870 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_b() argument
875 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
876 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180); in rtl8192eu_iqk_path_b()
878 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_iqk_path_b()
879 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000); in rtl8192eu_iqk_path_b()
880 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_iqk_path_b()
881 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77); in rtl8192eu_iqk_path_b()
883 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
886 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
887 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
888 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_iqk_path_b()
889 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_b()
891 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303); in rtl8192eu_iqk_path_b()
892 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); in rtl8192eu_iqk_path_b()
895 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_b()
898 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_iqk_path_b()
899 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_b()
904 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_b()
905 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_iqk_path_b()
906 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_iqk_path_b()
913 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", in rtl8192eu_iqk_path_b()
919 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_b() argument
925 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
928 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
929 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
930 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
931 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_b()
933 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
934 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
935 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
936 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_b()
939 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_b()
940 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0); in rtl8192eu_rx_iqk_path_b()
943 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
946 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_b()
947 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
950 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
951 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
952 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
953 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
955 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f); in rtl8192eu_rx_iqk_path_b()
956 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f); in rtl8192eu_rx_iqk_path_b()
959 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_b()
962 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
963 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
968 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
969 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_rx_iqk_path_b()
970 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_rx_iqk_path_b()
981 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
982 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_b()
988 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
991 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
993 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
994 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
995 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
996 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_b()
998 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
999 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1000 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1001 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_b()
1004 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980); in rtl8192eu_rx_iqk_path_b()
1005 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0); in rtl8192eu_rx_iqk_path_b()
1008 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
1011 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
1014 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1015 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1016 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1017 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
1019 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); in rtl8192eu_rx_iqk_path_b()
1020 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); in rtl8192eu_rx_iqk_path_b()
1023 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_b()
1026 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
1027 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
1031 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
1032 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1033 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1035 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1036 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180); in rtl8192eu_rx_iqk_path_b()
1043 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", in rtl8192eu_rx_iqk_path_b()
1050 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8192eu_phy_iqcalibrate() argument
1053 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iqcalibrate()
1077 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1078 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1087 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1089 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1090 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1091 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1094 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8192eu_phy_iqcalibrate()
1097 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1099 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8192eu_phy_iqcalibrate()
1101 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8192eu_phy_iqcalibrate()
1103 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8192eu_phy_iqcalibrate()
1104 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8192eu_phy_iqcalibrate()
1105 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); in rtl8192eu_phy_iqcalibrate()
1107 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8192eu_phy_iqcalibrate()
1109 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8192eu_phy_iqcalibrate()
1111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1113 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1114 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1116 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1118 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1119 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1120 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1123 path_a_ok = rtl8192eu_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1125 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1128 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1140 path_a_ok = rtl8192eu_rx_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1142 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1145 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1156 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1158 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1159 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8192eu_phy_iqcalibrate()
1160 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1163 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8192eu_phy_iqcalibrate()
1165 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1166 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1167 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1170 path_b_ok = rtl8192eu_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1172 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_phy_iqcalibrate()
1174 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_phy_iqcalibrate()
1184 path_b_ok = rtl8192eu_rx_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1186 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1189 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1201 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1205 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1209 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1212 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1213 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1216 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1218 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1219 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
1221 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1222 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1224 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1226 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1231 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1232 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1236 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8192eu_phy_iq_calibrate() argument
1238 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iq_calibrate()
1253 rtl8192eu_phy_iqcalibrate(priv, result, i); in rtl8192eu_phy_iq_calibrate()
1256 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1265 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1272 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1292 priv->rege94 = reg_e94; in rtl8192eu_phy_iq_calibrate()
1294 priv->rege9c = reg_e9c; in rtl8192eu_phy_iq_calibrate()
1298 priv->regeb4 = reg_eb4; in rtl8192eu_phy_iq_calibrate()
1300 priv->regebc = reg_ebc; in rtl8192eu_phy_iq_calibrate()
1311 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8192eu_phy_iq_calibrate()
1312 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8192eu_phy_iq_calibrate()
1316 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8192eu_phy_iq_calibrate()
1319 if (priv->rf_paths > 1) in rtl8192eu_phy_iq_calibrate()
1320 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8192eu_phy_iq_calibrate()
1323 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8192eu_phy_iq_calibrate()
1324 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iq_calibrate()
1330 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) in rtl8192e_crystal_afe_adjust() argument
1338 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1340 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1342 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1344 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1350 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1352 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1357 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1359 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1362 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) in rtl8192e_disabled_to_emu() argument
1367 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_disabled_to_emu()
1369 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_disabled_to_emu()
1372 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8192e_emu_to_active() argument
1379 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1381 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1384 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1386 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1389 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1391 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1395 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1410 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); in rtl8192e_emu_to_active()
1412 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); in rtl8192e_emu_to_active()
1415 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1417 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1420 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1437 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_lps() argument
1439 struct device *dev = &priv->udev->dev; in rtl8192eu_active_to_lps()
1445 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8192eu_active_to_lps()
1453 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192eu_active_to_lps()
1467 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1469 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1474 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1476 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1479 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1482 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1484 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1486 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1488 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); in rtl8192eu_active_to_lps()
1490 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); in rtl8192eu_active_to_lps()
1496 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_emu() argument
1502 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); in rtl8192eu_active_to_emu()
1504 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_active_to_emu()
1507 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); in rtl8192eu_active_to_emu()
1509 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); in rtl8192eu_active_to_emu()
1512 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1514 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_active_to_emu()
1517 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1524 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8192eu_active_to_emu()
1534 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) in rtl8192eu_emu_to_disabled() argument
1539 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_emu_to_disabled()
1542 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_emu_to_disabled()
1547 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) in rtl8192eu_power_on() argument
1553 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_power_on()
1555 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); in rtl8192eu_power_on()
1560 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); in rtl8192eu_power_on()
1563 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); in rtl8192eu_power_on()
1564 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); in rtl8192eu_power_on()
1570 rtl8192e_crystal_afe_adjust(priv); in rtl8192eu_power_on()
1571 rtl8192e_disabled_to_emu(priv); in rtl8192eu_power_on()
1573 ret = rtl8192e_emu_to_active(priv); in rtl8192eu_power_on()
1577 rtl8xxxu_write16(priv, REG_CR, 0x0000); in rtl8192eu_power_on()
1583 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_power_on()
1589 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_power_on()
1595 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) in rtl8192eu_power_off() argument
1600 rtl8xxxu_flush_fifo(priv); in rtl8192eu_power_off()
1602 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8192eu_power_off()
1604 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8192eu_power_off()
1607 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); in rtl8192eu_power_off()
1609 rtl8192eu_active_to_lps(priv); in rtl8192eu_power_off()
1612 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8192eu_power_off()
1613 rtl8xxxu_firmware_self_reset(priv); in rtl8192eu_power_off()
1616 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_power_off()
1618 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_power_off()
1621 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8192eu_power_off()
1623 rtl8xxxu_reset_8051(priv); in rtl8192eu_power_off()
1625 rtl8192eu_active_to_emu(priv); in rtl8192eu_power_off()
1626 rtl8192eu_emu_to_disabled(priv); in rtl8192eu_power_off()
1629 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) in rtl8192e_enable_rf() argument
1634 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8192e_enable_rf()
1636 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8192e_enable_rf()
1638 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8192e_enable_rf()
1640 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8192e_enable_rf()
1645 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8192e_enable_rf()
1647 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8192e_enable_rf()
1649 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1651 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192e_enable_rf()
1653 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
1655 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8192e_enable_rf()
1657 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192e_enable_rf()
1660 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8192e_enable_rf()
1665 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8192e_enable_rf()
1667 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8192e_enable_rf()
1672 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8192e_enable_rf()
1675 static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats) in rtl8192e_cck_rssi() argument
1688 if (priv->cck_agc_report_type == 0) in rtl8192e_cck_rssi()
1701 struct rtl8xxxu_priv *priv = container_of(led_cdev, in rtl8192eu_led_brightness_set() local
1704 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1); in rtl8192eu_led_brightness_set()
1716 rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg); in rtl8192eu_led_brightness_set()