Lines Matching refs:val32
360 u32 val32, ofdm, mcs; in rtl8188f_set_tx_power() local
368 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8188f_set_tx_power()
369 val32 &= 0xffff00ff; in rtl8188f_set_tx_power()
370 val32 |= (cck << 8); in rtl8188f_set_tx_power()
371 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8188f_set_tx_power()
373 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8188f_set_tx_power()
374 val32 &= 0xff; in rtl8188f_set_tx_power()
375 val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); in rtl8188f_set_tx_power()
376 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8188f_set_tx_power()
430 u32 val32, initial_gain, reg948; in rtl8188f_spur_calibration() local
432 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); in rtl8188f_spur_calibration()
433 val32 |= GENMASK(28, 24); in rtl8188f_spur_calibration()
434 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
437 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_D_SYNC_PATH); in rtl8188f_spur_calibration()
438 val32 |= BIT(9); in rtl8188f_spur_calibration()
439 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
447 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8188f_spur_calibration()
448 val32 &= GENMASK(5, 3); in rtl8188f_spur_calibration()
449 hw_ctrl_s1 = val32 == BIT(3); in rtl8188f_spur_calibration()
458 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
459 val32 &= ~FPGA_RF_MODE_CCK; in rtl8188f_spur_calibration()
460 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
462 val32 = initial_gain & ~OFDM0_X_AGC_CORE1_IGI_MASK; in rtl8188f_spur_calibration()
463 val32 |= 0x30; in rtl8188f_spur_calibration()
464 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188f_spur_calibration()
486 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188f_spur_calibration()
487 val32 |= FPGA_RF_MODE_CCK; in rtl8188f_spur_calibration()
488 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188f_spur_calibration()
499 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); in rtl8188f_spur_calibration()
500 val32 |= BIT(28); in rtl8188f_spur_calibration()
501 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); in rtl8188f_spur_calibration()
509 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING); in rtl8188f_spur_calibration()
510 val32 &= ~BIT(28); in rtl8188f_spur_calibration()
511 rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32); in rtl8188f_spur_calibration()
517 u32 val32; in rtl8188fu_config_channel() local
524 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); in rtl8188fu_config_channel()
525 val32 &= ~MODE_AG_CHANNEL_MASK; in rtl8188fu_config_channel()
526 val32 |= channel; in rtl8188fu_config_channel()
527 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8188fu_config_channel()
533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
534 val32 &= ~FPGA_RF_MODE; in rtl8188fu_config_channel()
535 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; in rtl8188fu_config_channel()
536 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
538 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); in rtl8188fu_config_channel()
539 val32 &= ~FPGA_RF_MODE; in rtl8188fu_config_channel()
540 val32 |= hw->conf.chandef.width == NL80211_CHAN_WIDTH_40; in rtl8188fu_config_channel()
541 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188fu_config_channel()
544 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
545 val32 |= GENMASK(10, 8); in rtl8188fu_config_channel()
546 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
549 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); in rtl8188fu_config_channel()
550 val32 |= BIT(14) | BIT(12); in rtl8188fu_config_channel()
551 val32 &= ~BIT(13); in rtl8188fu_config_channel()
552 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188fu_config_channel()
555 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8188fu_config_channel()
556 val32 &= ~GENMASK(31, 30); in rtl8188fu_config_channel()
557 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8188fu_config_channel()
560 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); in rtl8188fu_config_channel()
561 val32 &= ~BIT(29); in rtl8188fu_config_channel()
562 val32 |= BIT(28); in rtl8188fu_config_channel()
563 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); in rtl8188fu_config_channel()
566 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE); in rtl8188fu_config_channel()
567 val32 &= ~BIT(29); in rtl8188fu_config_channel()
568 val32 |= BIT(28); in rtl8188fu_config_channel()
569 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32); in rtl8188fu_config_channel()
571 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); in rtl8188fu_config_channel()
572 val32 &= ~BIT(19); in rtl8188fu_config_channel()
573 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); in rtl8188fu_config_channel()
575 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR); in rtl8188fu_config_channel()
576 val32 &= ~GENMASK(23, 20); in rtl8188fu_config_channel()
577 val32 |= BIT(21); in rtl8188fu_config_channel()
580 val32 |= BIT(20); in rtl8188fu_config_channel()
582 val32 |= BIT(22); in rtl8188fu_config_channel()
583 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32); in rtl8188fu_config_channel()
596 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); in rtl8188fu_config_channel()
597 val32 &= ~CCK0_SIDEBAND; in rtl8188fu_config_channel()
599 val32 |= CCK0_SIDEBAND; in rtl8188fu_config_channel()
600 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8188fu_config_channel()
602 val32 = rtl8xxxu_read32(priv, REG_DATA_SUBCHANNEL); in rtl8188fu_config_channel()
603 val32 &= ~GENMASK(3, 0); in rtl8188fu_config_channel()
608 val32 |= subchannel; in rtl8188fu_config_channel()
609 rtl8xxxu_write32(priv, REG_DATA_SUBCHANNEL, val32); in rtl8188fu_config_channel()
611 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); in rtl8188fu_config_channel()
612 val32 &= ~RSR_RSC_BANDWIDTH_40M; in rtl8188fu_config_channel()
613 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); in rtl8188fu_config_channel()
617 val32 = channel; in rtl8188fu_config_channel()
620 val32 |= MODE_AG_BW_20MHZ_8723B; in rtl8188fu_config_channel()
622 val32 |= MODE_AG_BW_40MHZ_8723B; in rtl8188fu_config_channel()
623 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); in rtl8188fu_config_channel()
628 val32 = 0x00065; in rtl8188fu_config_channel()
630 val32 = 0x00025; in rtl8188fu_config_channel()
631 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RXG_MIX_SWBW, val32); in rtl8188fu_config_channel()
635 val32 = 0x0; in rtl8188fu_config_channel()
637 val32 = 0x01000; in rtl8188fu_config_channel()
638 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RX_BB2, val32); in rtl8188fu_config_channel()
648 u32 agg_rx, val32; in rtl8188fu_init_aggregation() local
651 val32 = rtl8xxxu_read32(priv, REG_DWBCN0_CTRL_8188F); in rtl8188fu_init_aggregation()
652 val32 &= ~(0xf << 4); in rtl8188fu_init_aggregation()
653 val32 |= usb_tx_agg_desc_num << 4; in rtl8188fu_init_aggregation()
654 rtl8xxxu_write32(priv, REG_DWBCN0_CTRL_8188F, val32); in rtl8188fu_init_aggregation()
675 u32 val32; in rtl8188fu_init_statistics() local
684 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_init_statistics()
685 val32 |= 0xff; in rtl8188fu_init_statistics()
686 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_init_statistics()
689 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8188fu_init_statistics()
690 val32 &= ~(BIT(8) | BIT(9) | BIT(10)); in rtl8188fu_init_statistics()
691 val32 |= BIT(8); in rtl8188fu_init_statistics()
692 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8188fu_init_statistics()
695 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8188fu_init_statistics()
696 val32 |= BIT(7); in rtl8188fu_init_statistics()
697 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8188fu_init_statistics()
792 u32 val32; in rtl8188f_phy_lc_calibrate() local
801 val32 = lstf & ~OFDM_LSTF_MASK; in rtl8188f_phy_lc_calibrate()
802 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8188f_phy_lc_calibrate()
835 u32 reg_eac, reg_e94, reg_e9c, val32; in rtl8188fu_iqk_path_a() local
841 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
842 val32 &= 0x000000ff; in rtl8188fu_iqk_path_a()
843 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
848 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_iqk_path_a()
849 val32 |= 0x80000; in rtl8188fu_iqk_path_a()
850 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_iqk_path_a()
860 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
861 val32 &= 0x000000ff; in rtl8188fu_iqk_path_a()
862 val32 |= 0x80800000; in rtl8188fu_iqk_path_a()
863 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
884 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
885 val32 &= 0x000000ff; in rtl8188fu_iqk_path_a()
886 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
908 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; in rtl8188fu_rx_iqk_path_a() local
914 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
915 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
916 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
921 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_rx_iqk_path_a()
922 val32 |= 0x80000; in rtl8188fu_rx_iqk_path_a()
923 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_rx_iqk_path_a()
935 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
936 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
937 val32 |= 0x80800000; in rtl8188fu_rx_iqk_path_a()
938 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
965 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
966 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
967 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
983 val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | in rtl8188fu_rx_iqk_path_a()
985 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8188fu_rx_iqk_path_a()
990 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
991 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
992 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
994 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8188fu_rx_iqk_path_a()
995 val32 |= 0x80000; in rtl8188fu_rx_iqk_path_a()
996 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8188fu_rx_iqk_path_a()
1010 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1011 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
1012 val32 |= 0x80800000; in rtl8188fu_rx_iqk_path_a()
1013 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1039 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
1040 val32 &= 0x000000ff; in rtl8188fu_rx_iqk_path_a()
1041 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
1065 u32 i, val32, rx_initial_gain, lok_result; in rtl8188fu_phy_iqcalibrate() local
1109 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); in rtl8188fu_phy_iqcalibrate()
1110 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI); in rtl8188fu_phy_iqcalibrate()
1123 val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL); in rtl8188fu_phy_iqcalibrate()
1124 val32 |= 0x00ff0000; in rtl8188fu_phy_iqcalibrate()
1125 rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32); in rtl8188fu_phy_iqcalibrate()
1128 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1129 val32 &= 0xff; in rtl8188fu_phy_iqcalibrate()
1130 val32 |= 0x80800000; in rtl8188fu_phy_iqcalibrate()
1131 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1138 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1139 val32 &= 0xff; in rtl8188fu_phy_iqcalibrate()
1140 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1142 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1144 result[t][0] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1146 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1148 result[t][1] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1156 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1158 result[t][2] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1160 val32 = rtl8xxxu_read32(priv, in rtl8188fu_phy_iqcalibrate()
1162 result[t][3] = (val32 >> 16) & 0x3ff; in rtl8188fu_phy_iqcalibrate()
1171 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_phy_iqcalibrate()
1172 val32 &= 0xff; in rtl8188fu_phy_iqcalibrate()
1173 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_phy_iqcalibrate()
1183 val32 = 0x01000000; in rtl8188fu_phy_iqcalibrate()
1184 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); in rtl8188fu_phy_iqcalibrate()
1185 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); in rtl8188fu_phy_iqcalibrate()
1204 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1205 val32 &= 0xffffff00; in rtl8188fu_phy_iqcalibrate()
1206 val32 |= 0x50; in rtl8188fu_phy_iqcalibrate()
1207 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1208 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8188fu_phy_iqcalibrate()
1209 val32 &= 0xffffff00; in rtl8188fu_phy_iqcalibrate()
1210 val32 |= rx_initial_gain & 0xff; in rtl8188fu_phy_iqcalibrate()
1211 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32); in rtl8188fu_phy_iqcalibrate()
1336 u32 val32; in rtl8188f_emu_to_active() local
1346 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188f_emu_to_active()
1347 if (val32 & BIT(17)) in rtl8188f_emu_to_active()
1374 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188f_emu_to_active()
1375 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { in rtl8188f_emu_to_active()
1396 u32 val32; in rtl8188fu_active_to_emu() local
1416 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8188fu_active_to_emu()
1417 if ((val32 & APS_FSMCO_MAC_OFF) == 0) { in rtl8188fu_active_to_emu()
1456 u32 val32; in rtl8188fu_active_to_lps() local
1474 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8188fu_active_to_lps()
1475 if (!val32) { in rtl8188fu_active_to_lps()
1584 u32 val32; in rtl8188f_enable_rf() local
1605 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55); in rtl8188f_enable_rf()
1606 val32 &= ~0xfc000; in rtl8188f_enable_rf()
1607 val32 |= val8 << 14; in rtl8188f_enable_rf()
1608 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, val32); in rtl8188f_enable_rf()
1613 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_enable_rf()
1614 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); in rtl8188f_enable_rf()
1615 val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A; in rtl8188f_enable_rf()
1616 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_enable_rf()
1623 u32 val32; in rtl8188f_disable_rf() local
1625 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); in rtl8188f_disable_rf()
1626 val32 &= ~OFDM_RF_PATH_TX_MASK; in rtl8188f_disable_rf()
1627 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); in rtl8188f_disable_rf()
1636 u32 val32; in rtl8188f_usb_quirks() local
1642 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); in rtl8188f_usb_quirks()
1643 val32 |= TXDMA_OFFSET_DROP_DATA_EN; in rtl8188f_usb_quirks()
1644 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); in rtl8188f_usb_quirks()
1653 u32 val32; in rtl8188f_set_crystal_cap() local
1658 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); in rtl8188f_set_crystal_cap()
1664 FIELD_GET(XTAL1, val32), in rtl8188f_set_crystal_cap()
1665 FIELD_GET(XTAL0, val32), in rtl8188f_set_crystal_cap()
1668 val32 &= ~(XTAL1 | XTAL0); in rtl8188f_set_crystal_cap()
1669 val32 |= FIELD_PREP(XTAL1, crystal_cap) | in rtl8188f_set_crystal_cap()
1671 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); in rtl8188f_set_crystal_cap()