Lines Matching full:reg
57 u32 reg; in rt61pci_bbp_write() local
65 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
66 reg = 0; in rt61pci_bbp_write()
67 rt2x00_set_field32(®, PHY_CSR3_VALUE, value); in rt61pci_bbp_write()
68 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_write()
69 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_write()
70 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0); in rt61pci_bbp_write()
72 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
81 u32 reg; in rt61pci_bbp_read() local
91 * doesn't become available in time, reg will be 0xffffffff in rt61pci_bbp_read()
94 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
95 reg = 0; in rt61pci_bbp_read()
96 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word); in rt61pci_bbp_read()
97 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1); in rt61pci_bbp_read()
98 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1); in rt61pci_bbp_read()
100 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
102 WAIT_FOR_BBP(rt2x00dev, ®); in rt61pci_bbp_read()
105 value = rt2x00_get_field32(reg, PHY_CSR3_VALUE); in rt61pci_bbp_read()
115 u32 reg; in rt61pci_rf_write() local
123 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt61pci_rf_write()
124 reg = 0; in rt61pci_rf_write()
125 rt2x00_set_field32(®, PHY_CSR4_VALUE, value); in rt61pci_rf_write()
126 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21); in rt61pci_rf_write()
127 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0); in rt61pci_rf_write()
128 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1); in rt61pci_rf_write()
130 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
141 u32 reg; in rt61pci_mcu_request() local
149 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt61pci_mcu_request()
150 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt61pci_mcu_request()
151 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt61pci_mcu_request()
152 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt61pci_mcu_request()
153 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt61pci_mcu_request()
154 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
156 reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR); in rt61pci_mcu_request()
157 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt61pci_mcu_request()
158 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1); in rt61pci_mcu_request()
159 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
169 u32 reg; in rt61pci_eepromregister_read() local
171 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); in rt61pci_eepromregister_read()
173 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); in rt61pci_eepromregister_read()
174 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); in rt61pci_eepromregister_read()
176 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK); in rt61pci_eepromregister_read()
178 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT); in rt61pci_eepromregister_read()
184 u32 reg = 0; in rt61pci_eepromregister_write() local
186 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); in rt61pci_eepromregister_write()
187 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); in rt61pci_eepromregister_write()
188 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, in rt61pci_eepromregister_write()
190 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT, in rt61pci_eepromregister_write()
193 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
233 u32 reg; in rt61pci_rfkill_poll() local
235 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_rfkill_poll()
236 return rt2x00_get_field32(reg, MAC_CSR13_VAL5); in rt61pci_rfkill_poll()
284 u32 reg; in rt61pci_blink_set() local
286 reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); in rt61pci_blink_set()
287 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on); in rt61pci_blink_set()
288 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off); in rt61pci_blink_set()
289 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
328 u32 reg; in rt61pci_config_pairwise_key() local
340 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); in rt61pci_config_pairwise_key()
341 if (reg && reg == ~0) { in rt61pci_config_pairwise_key()
343 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); in rt61pci_config_pairwise_key()
344 if (reg && reg == ~0) in rt61pci_config_pairwise_key()
348 key->hw_key_idx += reg ? ffz(reg) : 0; in rt61pci_config_pairwise_key()
364 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); in rt61pci_config_pairwise_key()
365 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
368 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); in rt61pci_config_pairwise_key()
369 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
377 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4); in rt61pci_config_pairwise_key()
378 reg |= (1 << crypto->bssidx); in rt61pci_config_pairwise_key()
379 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
402 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); in rt61pci_config_pairwise_key()
404 reg |= mask; in rt61pci_config_pairwise_key()
406 reg &= ~mask; in rt61pci_config_pairwise_key()
407 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
411 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); in rt61pci_config_pairwise_key()
413 reg |= mask; in rt61pci_config_pairwise_key()
415 reg &= ~mask; in rt61pci_config_pairwise_key()
416 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
425 u32 reg; in rt61pci_config_filter() local
433 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_config_filter()
434 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC, in rt61pci_config_filter()
436 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL, in rt61pci_config_filter()
438 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL, in rt61pci_config_filter()
440 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME, in rt61pci_config_filter()
442 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS, in rt61pci_config_filter()
445 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1); in rt61pci_config_filter()
446 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST, in rt61pci_config_filter()
448 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0); in rt61pci_config_filter()
449 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, in rt61pci_config_filter()
451 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
459 u32 reg; in rt61pci_config_intf() local
465 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_config_intf()
466 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); in rt61pci_config_intf()
467 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
471 reg = le32_to_cpu(conf->mac[1]); in rt61pci_config_intf()
472 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff); in rt61pci_config_intf()
473 conf->mac[1] = cpu_to_le32(reg); in rt61pci_config_intf()
480 reg = le32_to_cpu(conf->bssid[1]); in rt61pci_config_intf()
481 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3); in rt61pci_config_intf()
482 conf->bssid[1] = cpu_to_le32(reg); in rt61pci_config_intf()
494 u32 reg; in rt61pci_config_erp() local
496 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_config_erp()
497 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, 0x32); in rt61pci_config_erp()
498 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER); in rt61pci_config_erp()
499 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
502 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); in rt61pci_config_erp()
503 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1); in rt61pci_config_erp()
504 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, in rt61pci_config_erp()
506 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
514 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_config_erp()
515 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, in rt61pci_config_erp()
517 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
521 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); in rt61pci_config_erp()
522 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); in rt61pci_config_erp()
523 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
525 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8); in rt61pci_config_erp()
526 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); in rt61pci_config_erp()
527 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3); in rt61pci_config_erp()
528 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); in rt61pci_config_erp()
529 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
620 u32 reg; in rt61pci_config_antenna_2529_rx() local
622 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_config_antenna_2529_rx()
624 rt2x00_set_field32(®, MAC_CSR13_DIR4, 0); in rt61pci_config_antenna_2529_rx()
625 rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); in rt61pci_config_antenna_2529_rx()
627 rt2x00_set_field32(®, MAC_CSR13_DIR3, 0); in rt61pci_config_antenna_2529_rx()
628 rt2x00_set_field32(®, MAC_CSR13_VAL3, !p2); in rt61pci_config_antenna_2529_rx()
630 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
709 u32 reg; in rt61pci_config_ant() local
729 reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0); in rt61pci_config_ant()
731 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, in rt61pci_config_ant()
733 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, in rt61pci_config_ant()
736 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
834 u32 reg; in rt61pci_config_retry_limit() local
836 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); in rt61pci_config_retry_limit()
837 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_DOWN, 1); in rt61pci_config_retry_limit()
838 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_RATE_STEP, 0); in rt61pci_config_retry_limit()
839 rt2x00_set_field32(®, TXRX_CSR4_OFDM_TX_FALLBACK_CCK, 0); in rt61pci_config_retry_limit()
840 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, in rt61pci_config_retry_limit()
842 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, in rt61pci_config_retry_limit()
844 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
853 u32 reg; in rt61pci_config_ps() local
856 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); in rt61pci_config_ps()
857 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, in rt61pci_config_ps()
859 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, in rt61pci_config_ps()
861 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 5); in rt61pci_config_ps()
864 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
865 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
867 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 1); in rt61pci_config_ps()
868 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
877 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); in rt61pci_config_ps()
878 rt2x00_set_field32(®, MAC_CSR11_DELAY_AFTER_TBCN, 0); in rt61pci_config_ps()
879 rt2x00_set_field32(®, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); in rt61pci_config_ps()
880 rt2x00_set_field32(®, MAC_CSR11_AUTOWAKE, 0); in rt61pci_config_ps()
881 rt2x00_set_field32(®, MAC_CSR11_WAKEUP_LATENCY, 0); in rt61pci_config_ps()
882 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
918 u32 reg; in rt61pci_link_stats() local
923 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); in rt61pci_link_stats()
924 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); in rt61pci_link_stats()
929 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); in rt61pci_link_stats()
930 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); in rt61pci_link_stats()
1044 u32 reg; in rt61pci_start_queue() local
1048 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_start_queue()
1049 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_start_queue()
1050 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1053 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_start_queue()
1054 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1); in rt61pci_start_queue()
1055 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1); in rt61pci_start_queue()
1056 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_start_queue()
1057 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1067 u32 reg; in rt61pci_kick_queue() local
1071 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1072 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1); in rt61pci_kick_queue()
1073 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1076 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1077 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1); in rt61pci_kick_queue()
1078 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1081 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1082 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1); in rt61pci_kick_queue()
1083 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1086 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1087 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1); in rt61pci_kick_queue()
1088 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1098 u32 reg; in rt61pci_stop_queue() local
1102 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1103 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1); in rt61pci_stop_queue()
1104 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1107 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1108 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1); in rt61pci_stop_queue()
1109 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1112 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1113 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1); in rt61pci_stop_queue()
1114 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1117 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1118 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1); in rt61pci_stop_queue()
1119 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1122 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_stop_queue()
1123 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 1); in rt61pci_stop_queue()
1124 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1127 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_stop_queue()
1128 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_stop_queue()
1129 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_stop_queue()
1130 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_stop_queue()
1131 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1203 u32 reg; in rt61pci_load_firmware() local
1209 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); in rt61pci_load_firmware()
1210 if (reg) in rt61pci_load_firmware()
1215 if (!reg) { in rt61pci_load_firmware()
1223 reg = 0; in rt61pci_load_firmware()
1224 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1225 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1233 reg = 0; in rt61pci_load_firmware()
1234 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1); in rt61pci_load_firmware()
1235 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1); in rt61pci_load_firmware()
1236 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1241 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0); in rt61pci_load_firmware()
1242 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1244 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0); in rt61pci_load_firmware()
1245 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1248 reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR); in rt61pci_load_firmware()
1249 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY)) in rt61pci_load_firmware()
1267 reg = 0; in rt61pci_load_firmware()
1268 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_load_firmware()
1269 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_load_firmware()
1270 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1272 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_load_firmware()
1273 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_load_firmware()
1274 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_load_firmware()
1275 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1277 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_load_firmware()
1278 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_load_firmware()
1279 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1330 u32 reg; in rt61pci_init_queues() local
1335 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0); in rt61pci_init_queues()
1336 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE, in rt61pci_init_queues()
1338 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE, in rt61pci_init_queues()
1340 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE, in rt61pci_init_queues()
1342 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE, in rt61pci_init_queues()
1344 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1346 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1); in rt61pci_init_queues()
1347 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE, in rt61pci_init_queues()
1349 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1352 reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR); in rt61pci_init_queues()
1353 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1355 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1358 reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR); in rt61pci_init_queues()
1359 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1361 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1364 reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR); in rt61pci_init_queues()
1365 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1367 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1370 reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR); in rt61pci_init_queues()
1371 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1373 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1375 reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR); in rt61pci_init_queues()
1376 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1377 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE, in rt61pci_init_queues()
1379 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4); in rt61pci_init_queues()
1380 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1383 reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR); in rt61pci_init_queues()
1384 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER, in rt61pci_init_queues()
1386 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1388 reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR); in rt61pci_init_queues()
1389 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2); in rt61pci_init_queues()
1390 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2); in rt61pci_init_queues()
1391 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2); in rt61pci_init_queues()
1392 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2); in rt61pci_init_queues()
1393 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1395 reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR); in rt61pci_init_queues()
1396 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1); in rt61pci_init_queues()
1397 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1); in rt61pci_init_queues()
1398 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1); in rt61pci_init_queues()
1399 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1); in rt61pci_init_queues()
1400 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1402 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); in rt61pci_init_queues()
1403 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1); in rt61pci_init_queues()
1404 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1411 u32 reg; in rt61pci_init_registers() local
1413 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_init_registers()
1414 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1); in rt61pci_init_registers()
1415 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0); in rt61pci_init_registers()
1416 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0); in rt61pci_init_registers()
1417 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1419 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1); in rt61pci_init_registers()
1420 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */ in rt61pci_init_registers()
1421 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1422 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */ in rt61pci_init_registers()
1423 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1424 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */ in rt61pci_init_registers()
1425 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1426 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */ in rt61pci_init_registers()
1427 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1428 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1433 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2); in rt61pci_init_registers()
1434 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13); in rt61pci_init_registers()
1435 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1436 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12); in rt61pci_init_registers()
1437 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1438 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11); in rt61pci_init_registers()
1439 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1440 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10); in rt61pci_init_registers()
1441 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1); in rt61pci_init_registers()
1442 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1447 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3); in rt61pci_init_registers()
1448 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7); in rt61pci_init_registers()
1449 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1); in rt61pci_init_registers()
1450 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6); in rt61pci_init_registers()
1451 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1); in rt61pci_init_registers()
1452 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5); in rt61pci_init_registers()
1453 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1); in rt61pci_init_registers()
1454 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1456 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7); in rt61pci_init_registers()
1457 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59); in rt61pci_init_registers()
1458 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53); in rt61pci_init_registers()
1459 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49); in rt61pci_init_registers()
1460 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46); in rt61pci_init_registers()
1461 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1463 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8); in rt61pci_init_registers()
1464 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44); in rt61pci_init_registers()
1465 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42); in rt61pci_init_registers()
1466 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42); in rt61pci_init_registers()
1467 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42); in rt61pci_init_registers()
1468 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1470 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_init_registers()
1471 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, 0); in rt61pci_init_registers()
1472 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0); in rt61pci_init_registers()
1473 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0); in rt61pci_init_registers()
1474 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0); in rt61pci_init_registers()
1475 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_init_registers()
1476 rt2x00_set_field32(®, TXRX_CSR9_TIMESTAMP_COMPENSATE, 0); in rt61pci_init_registers()
1477 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1483 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); in rt61pci_init_registers()
1484 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0); in rt61pci_init_registers()
1485 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1529 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); in rt61pci_init_registers()
1530 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); in rt61pci_init_registers()
1531 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2); in rt61pci_init_registers()
1536 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1537 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1); in rt61pci_init_registers()
1538 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1); in rt61pci_init_registers()
1539 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1541 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1542 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0); in rt61pci_init_registers()
1543 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0); in rt61pci_init_registers()
1544 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1546 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1547 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1); in rt61pci_init_registers()
1548 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1624 u32 reg; in rt61pci_toggle_irq() local
1632 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); in rt61pci_toggle_irq()
1633 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1635 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); in rt61pci_toggle_irq()
1636 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1645 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_toggle_irq()
1646 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask); in rt61pci_toggle_irq()
1647 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask); in rt61pci_toggle_irq()
1648 rt2x00_set_field32(®, INT_MASK_CSR_BEACON_DONE, mask); in rt61pci_toggle_irq()
1649 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask); in rt61pci_toggle_irq()
1650 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff); in rt61pci_toggle_irq()
1651 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1653 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_toggle_irq()
1654 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask); in rt61pci_toggle_irq()
1655 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask); in rt61pci_toggle_irq()
1656 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask); in rt61pci_toggle_irq()
1657 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask); in rt61pci_toggle_irq()
1658 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask); in rt61pci_toggle_irq()
1659 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask); in rt61pci_toggle_irq()
1660 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask); in rt61pci_toggle_irq()
1661 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask); in rt61pci_toggle_irq()
1662 rt2x00_set_field32(®, MCU_INT_MASK_CSR_TWAKEUP, mask); in rt61pci_toggle_irq()
1663 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1680 u32 reg; in rt61pci_enable_radio() local
1693 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); in rt61pci_enable_radio()
1694 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1); in rt61pci_enable_radio()
1695 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1710 u32 reg, reg2; in rt61pci_set_state() local
1716 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); in rt61pci_set_state()
1717 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep); in rt61pci_set_state()
1718 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep); in rt61pci_set_state()
1719 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1731 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1879 u32 orig_reg, reg; in rt61pci_write_beacon() local
1885 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_write_beacon()
1886 orig_reg = reg; in rt61pci_write_beacon()
1887 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_write_beacon()
1888 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1927 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1); in rt61pci_write_beacon()
1928 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1940 u32 orig_reg, reg; in rt61pci_clear_beacon() local
1947 reg = orig_reg; in rt61pci_clear_beacon()
1948 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0); in rt61pci_clear_beacon()
1949 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
2067 u32 reg; in rt61pci_txdone() local
2082 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4); in rt61pci_txdone()
2083 if (!rt2x00_get_field32(reg, STA_CSR4_VALID)) in rt61pci_txdone()
2090 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE); in rt61pci_txdone()
2099 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE); in rt61pci_txdone()
2127 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) { in rt61pci_txdone()
2137 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); in rt61pci_txdone()
2160 u32 reg; in rt61pci_enable_interrupt() local
2168 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_enable_interrupt()
2169 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_interrupt()
2170 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2178 u32 reg; in rt61pci_enable_mcu_interrupt() local
2186 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_enable_mcu_interrupt()
2187 rt2x00_set_field32(®, irq_field, 0); in rt61pci_enable_mcu_interrupt()
2188 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2236 u32 reg, mask; in rt61pci_interrupt() local
2245 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); in rt61pci_interrupt()
2246 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2248 if (!reg && !reg_mcu) in rt61pci_interrupt()
2257 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE)) in rt61pci_interrupt()
2260 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE)) in rt61pci_interrupt()
2263 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_BEACON_DONE)) in rt61pci_interrupt()
2274 mask = reg; in rt61pci_interrupt()
2283 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_interrupt()
2284 reg |= mask; in rt61pci_interrupt()
2285 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2287 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_interrupt()
2288 reg |= mask_mcu; in rt61pci_interrupt()
2289 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2302 u32 reg; in rt61pci_validate_eeprom() local
2307 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); in rt61pci_validate_eeprom()
2312 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ? in rt61pci_validate_eeprom()
2409 u32 reg; in rt61pci_init_eeprom() local
2422 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); in rt61pci_init_eeprom()
2423 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), in rt61pci_init_eeprom()
2424 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION)); in rt61pci_init_eeprom()
2742 u32 reg; in rt61pci_probe_hw() local
2764 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_probe_hw()
2765 rt2x00_set_field32(®, MAC_CSR13_DIR5, 1); in rt61pci_probe_hw()
2766 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2810 u32 reg; in rt61pci_conf_tx() local
2837 reg = rt2x00mmio_register_read(rt2x00dev, offset); in rt61pci_conf_tx()
2838 rt2x00_set_field32(®, field, queue->txop); in rt61pci_conf_tx()
2839 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2845 reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR); in rt61pci_conf_tx()
2846 rt2x00_set_field32(®, field, queue->aifs); in rt61pci_conf_tx()
2847 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2849 reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR); in rt61pci_conf_tx()
2850 rt2x00_set_field32(®, field, queue->cw_min); in rt61pci_conf_tx()
2851 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2853 reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR); in rt61pci_conf_tx()
2854 rt2x00_set_field32(®, field, queue->cw_max); in rt61pci_conf_tx()
2855 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()
2864 u32 reg; in rt61pci_get_tsf() local
2866 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13); in rt61pci_get_tsf()
2867 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32; in rt61pci_get_tsf()
2868 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12); in rt61pci_get_tsf()
2869 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER); in rt61pci_get_tsf()