Lines Matching +full:p1 +full:- +full:retry +full:- +full:params
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
14 #include <linux/crc-itu-t.h>
59 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
75 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
84 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
107 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
117 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
134 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
143 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
162 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
168 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_read()
173 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN); in rt61pci_eepromregister_read()
174 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT); in rt61pci_eepromregister_read()
175 eeprom->reg_data_clock = in rt61pci_eepromregister_read()
177 eeprom->reg_chip_select = in rt61pci_eepromregister_read()
183 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_write()
186 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in); in rt61pci_eepromregister_write()
187 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out); in rt61pci_eepromregister_write()
189 !!eeprom->reg_data_clock); in rt61pci_eepromregister_write()
191 !!eeprom->reg_chip_select); in rt61pci_eepromregister_write()
247 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ); in rt61pci_brightness_set()
249 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); in rt61pci_brightness_set()
251 if (led->type == LED_TYPE_RADIO) { in rt61pci_brightness_set()
252 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
255 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
256 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
257 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
258 } else if (led->type == LED_TYPE_ASSOC) { in rt61pci_brightness_set()
259 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
261 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
264 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
265 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
266 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
267 } else if (led->type == LED_TYPE_QUALITY) { in rt61pci_brightness_set()
269 * The brightness is divided into 6 levels (0 - 5), in rt61pci_brightness_set()
273 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, in rt61pci_brightness_set()
286 reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); in rt61pci_blink_set()
289 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
298 led->rt2x00dev = rt2x00dev; in rt61pci_init_led()
299 led->type = type; in rt61pci_init_led()
300 led->led_dev.brightness_set = rt61pci_brightness_set; in rt61pci_init_led()
301 led->led_dev.blink_set = rt61pci_blink_set; in rt61pci_init_led()
302 led->flags = LED_INITIALIZED; in rt61pci_init_led()
318 return -EOPNOTSUPP; in rt61pci_config_shared_key()
330 if (crypto->cmd == SET_KEY) { in rt61pci_config_pairwise_key()
342 key->hw_key_idx = 32; in rt61pci_config_pairwise_key()
345 return -ENOSPC; in rt61pci_config_pairwise_key()
348 key->hw_key_idx += reg ? ffz(reg) : 0; in rt61pci_config_pairwise_key()
353 memcpy(key_entry.key, crypto->key, in rt61pci_config_pairwise_key()
355 memcpy(key_entry.tx_mic, crypto->tx_mic, in rt61pci_config_pairwise_key()
357 memcpy(key_entry.rx_mic, crypto->rx_mic, in rt61pci_config_pairwise_key()
361 memcpy(&addr_entry, crypto->address, ETH_ALEN); in rt61pci_config_pairwise_key()
362 addr_entry.cipher = crypto->cipher; in rt61pci_config_pairwise_key()
364 reg = PAIRWISE_KEY_ENTRY(key->hw_key_idx); in rt61pci_config_pairwise_key()
368 reg = PAIRWISE_TA_ENTRY(key->hw_key_idx); in rt61pci_config_pairwise_key()
378 reg |= (1 << crypto->bssidx); in rt61pci_config_pairwise_key()
390 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; in rt61pci_config_pairwise_key()
394 * SEC_CSR2 and SEC_CSR3 contain only single-bit fields to indicate in rt61pci_config_pairwise_key()
399 if (key->hw_key_idx < 32) { in rt61pci_config_pairwise_key()
400 mask = 1 << key->hw_key_idx; in rt61pci_config_pairwise_key()
403 if (crypto->cmd == SET_KEY) in rt61pci_config_pairwise_key()
405 else if (crypto->cmd == DISABLE_KEY) in rt61pci_config_pairwise_key()
409 mask = 1 << (key->hw_key_idx - 32); in rt61pci_config_pairwise_key()
412 if (crypto->cmd == SET_KEY) in rt61pci_config_pairwise_key()
414 else if (crypto->cmd == DISABLE_KEY) in rt61pci_config_pairwise_key()
441 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); in rt61pci_config_filter()
443 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && in rt61pci_config_filter()
444 !rt2x00dev->intf_ap_count); in rt61pci_config_filter()
466 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync); in rt61pci_config_intf()
471 reg = le32_to_cpu(conf->mac[1]); in rt61pci_config_intf()
473 conf->mac[1] = cpu_to_le32(reg); in rt61pci_config_intf()
476 conf->mac, sizeof(conf->mac)); in rt61pci_config_intf()
480 reg = le32_to_cpu(conf->bssid[1]); in rt61pci_config_intf()
482 conf->bssid[1] = cpu_to_le32(reg); in rt61pci_config_intf()
485 conf->bssid, in rt61pci_config_intf()
486 sizeof(conf->bssid)); in rt61pci_config_intf()
505 !!erp->short_preamble); in rt61pci_config_erp()
511 erp->basic_rates); in rt61pci_config_erp()
516 erp->beacon_int * 16); in rt61pci_config_erp()
522 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, erp->slot_time); in rt61pci_config_erp()
526 rt2x00_set_field32(®, MAC_CSR8_SIFS, erp->sifs); in rt61pci_config_erp()
528 rt2x00_set_field32(®, MAC_CSR8_EIFS, erp->eifs); in rt61pci_config_erp()
549 switch (ant->rx) { in rt61pci_config_antenna_5x()
553 (rt2x00dev->curr_band != NL80211_BAND_5GHZ)); in rt61pci_config_antenna_5x()
558 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
567 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
597 switch (ant->rx) { in rt61pci_config_antenna_2x()
618 const int p1, const int p2) in rt61pci_config_antenna_2529_rx() argument
625 rt2x00_set_field32(®, MAC_CSR13_VAL4, p1); in rt61pci_config_antenna_2529_rx()
647 switch (ant->rx) { in rt61pci_config_antenna_2529()
675 * value[0] -> non-LNA
676 * value[1] -> LNA
715 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY || in rt61pci_config_ant()
716 ant->tx == ANTENNA_SW_DIVERSITY); in rt61pci_config_ant()
718 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_config_ant()
732 rt2x00dev->curr_band == NL80211_BAND_2GHZ); in rt61pci_config_ant()
734 rt2x00dev->curr_band == NL80211_BAND_5GHZ); in rt61pci_config_ant()
756 if (libconf->conf->chandef.chan->band == NL80211_BAND_2GHZ) { in rt61pci_config_lna_gain()
761 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1); in rt61pci_config_lna_gain()
767 lna_gain -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1); in rt61pci_config_lna_gain()
770 rt2x00dev->lna_gain = lna_gain; in rt61pci_config_lna_gain()
780 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower)); in rt61pci_config_channel()
781 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt61pci_config_channel()
791 r94 += txpower - MAX_TXPOWER; in rt61pci_config_channel()
792 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94)) in rt61pci_config_channel()
796 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
797 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
798 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
799 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
803 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
804 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
805 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); in rt61pci_config_channel()
806 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
810 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
811 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
812 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
813 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
841 libconf->conf->long_frame_max_tx_count); in rt61pci_config_retry_limit()
843 libconf->conf->short_frame_max_tx_count); in rt61pci_config_retry_limit()
851 (libconf->conf->flags & IEEE80211_CONF_PS) ? in rt61pci_config_ps()
858 rt2x00dev->beacon_int - 10); in rt61pci_config_ps()
860 libconf->conf->listen_interval - 1); in rt61pci_config_ps()
901 rt61pci_config_channel(rt2x00dev, &libconf->rf, in rt61pci_config()
902 libconf->conf->power_level); in rt61pci_config()
905 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); in rt61pci_config()
924 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR); in rt61pci_link_stats()
930 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR); in rt61pci_link_stats()
936 if (qual->vgc_level != vgc_level) { in rt61pci_set_vgc()
938 qual->vgc_level = vgc_level; in rt61pci_set_vgc()
939 qual->vgc_level_reg = vgc_level; in rt61pci_set_vgc()
958 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_link_tuner()
978 if (!rt2x00dev->intf_associated) in rt61pci_link_tuner()
982 * Special big-R17 for very short distance in rt61pci_link_tuner()
984 if (qual->rssi >= -35) { in rt61pci_link_tuner()
990 * Special big-R17 for short distance in rt61pci_link_tuner()
992 if (qual->rssi >= -58) { in rt61pci_link_tuner()
998 * Special big-R17 for middle-short distance in rt61pci_link_tuner()
1000 if (qual->rssi >= -66) { in rt61pci_link_tuner()
1006 * Special mid-R17 for middle distance in rt61pci_link_tuner()
1008 if (qual->rssi >= -74) { in rt61pci_link_tuner()
1015 * Lower up_bound when rssi is weaker then -74 dBm. in rt61pci_link_tuner()
1017 up_bound -= 2 * (-74 - qual->rssi); in rt61pci_link_tuner()
1021 if (qual->vgc_level > up_bound) { in rt61pci_link_tuner()
1032 if ((qual->false_cca > 512) && (qual->vgc_level < up_bound)) in rt61pci_link_tuner()
1033 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt61pci_link_tuner()
1034 else if ((qual->false_cca < 100) && (qual->vgc_level > low_bound)) in rt61pci_link_tuner()
1035 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt61pci_link_tuner()
1043 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_start_queue()
1046 switch (queue->qid) { in rt61pci_start_queue()
1066 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_kick_queue()
1069 switch (queue->qid) { in rt61pci_kick_queue()
1097 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_stop_queue()
1100 switch (queue->qid) { in rt61pci_stop_queue()
1136 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_stop_queue()
1151 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); in rt61pci_get_firmware_name()
1187 fw_crc = (data[len - 2] << 8 | data[len - 1]); in rt61pci_check_firmware()
1190 * Use the crc itu-t algorithm. in rt61pci_check_firmware()
1192 crc = crc_itu_t(0, data, len - 2); in rt61pci_check_firmware()
1217 return -EBUSY; in rt61pci_load_firmware()
1256 return -EBUSY; in rt61pci_load_firmware()
1289 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; in rt61pci_get_entry_state()
1292 if (entry->queue->qid == QID_RX) { in rt61pci_get_entry_state()
1293 word = rt2x00_desc_read(entry_priv->desc, 0); in rt61pci_get_entry_state()
1297 word = rt2x00_desc_read(entry_priv->desc, 0); in rt61pci_get_entry_state()
1306 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; in rt61pci_clear_entry()
1307 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); in rt61pci_clear_entry()
1310 if (entry->queue->qid == QID_RX) { in rt61pci_clear_entry()
1311 word = rt2x00_desc_read(entry_priv->desc, 5); in rt61pci_clear_entry()
1313 skbdesc->skb_dma); in rt61pci_clear_entry()
1314 rt2x00_desc_write(entry_priv->desc, 5, word); in rt61pci_clear_entry()
1316 word = rt2x00_desc_read(entry_priv->desc, 0); in rt61pci_clear_entry()
1318 rt2x00_desc_write(entry_priv->desc, 0, word); in rt61pci_clear_entry()
1320 word = rt2x00_desc_read(entry_priv->desc, 0); in rt61pci_clear_entry()
1323 rt2x00_desc_write(entry_priv->desc, 0, word); in rt61pci_clear_entry()
1337 rt2x00dev->tx[0].limit); in rt61pci_init_queues()
1339 rt2x00dev->tx[1].limit); in rt61pci_init_queues()
1341 rt2x00dev->tx[2].limit); in rt61pci_init_queues()
1343 rt2x00dev->tx[3].limit); in rt61pci_init_queues()
1348 rt2x00dev->tx[0].desc_size / 4); in rt61pci_init_queues()
1351 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt61pci_init_queues()
1354 entry_priv->desc_dma); in rt61pci_init_queues()
1357 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt61pci_init_queues()
1360 entry_priv->desc_dma); in rt61pci_init_queues()
1363 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; in rt61pci_init_queues()
1366 entry_priv->desc_dma); in rt61pci_init_queues()
1369 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; in rt61pci_init_queues()
1372 entry_priv->desc_dma); in rt61pci_init_queues()
1376 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1378 rt2x00dev->rx->desc_size / 4); in rt61pci_init_queues()
1382 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt61pci_init_queues()
1385 entry_priv->desc_dma); in rt61pci_init_queues()
1489 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt61pci_init_registers()
1490 return -EBUSY; in rt61pci_init_registers()
1566 return -EACCES; in rt61pci_wait_bbp_ready()
1577 return -EACCES; in rt61pci_init_bbp()
1641 * Non-checked interrupt bits are disabled by default. in rt61pci_toggle_irq()
1643 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1665 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1671 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt61pci_toggle_irq()
1672 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt61pci_toggle_irq()
1673 tasklet_kill(&rt2x00dev->autowake_tasklet); in rt61pci_toggle_irq()
1674 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_toggle_irq()
1688 return -EIO; in rt61pci_enable_radio()
1735 return -EBUSY; in rt61pci_set_state()
1761 retval = -ENOTSUPP; in rt61pci_set_device_state()
1778 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); in rt61pci_write_tx_desc()
1779 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; in rt61pci_write_tx_desc()
1780 __le32 *txd = entry_priv->desc; in rt61pci_write_tx_desc()
1787 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, entry->queue->qid); in rt61pci_write_tx_desc()
1788 rt2x00_set_field32(&word, TXD_W1_AIFSN, entry->queue->aifs); in rt61pci_write_tx_desc()
1789 rt2x00_set_field32(&word, TXD_W1_CWMIN, entry->queue->cw_min); in rt61pci_write_tx_desc()
1790 rt2x00_set_field32(&word, TXD_W1_CWMAX, entry->queue->cw_max); in rt61pci_write_tx_desc()
1791 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); in rt61pci_write_tx_desc()
1793 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags)); in rt61pci_write_tx_desc()
1798 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->u.plcp.signal); in rt61pci_write_tx_desc()
1799 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->u.plcp.service); in rt61pci_write_tx_desc()
1801 txdesc->u.plcp.length_low); in rt61pci_write_tx_desc()
1803 txdesc->u.plcp.length_high); in rt61pci_write_tx_desc()
1806 if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) { in rt61pci_write_tx_desc()
1807 _rt2x00_desc_write(txd, 3, skbdesc->iv[0]); in rt61pci_write_tx_desc()
1808 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); in rt61pci_write_tx_desc()
1812 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid); in rt61pci_write_tx_desc()
1813 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx); in rt61pci_write_tx_desc()
1815 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); in rt61pci_write_tx_desc()
1819 if (entry->queue->qid != QID_BEACON) { in rt61pci_write_tx_desc()
1822 skbdesc->skb_dma); in rt61pci_write_tx_desc()
1827 txdesc->length); in rt61pci_write_tx_desc()
1840 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); in rt61pci_write_tx_desc()
1842 test_bit(ENTRY_TXD_ACK, &txdesc->flags)); in rt61pci_write_tx_desc()
1844 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags)); in rt61pci_write_tx_desc()
1846 (txdesc->rate_mode == RATE_MODE_OFDM)); in rt61pci_write_tx_desc()
1847 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs); in rt61pci_write_tx_desc()
1849 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); in rt61pci_write_tx_desc()
1851 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags)); in rt61pci_write_tx_desc()
1853 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); in rt61pci_write_tx_desc()
1854 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); in rt61pci_write_tx_desc()
1855 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length); in rt61pci_write_tx_desc()
1857 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); in rt61pci_write_tx_desc()
1858 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); in rt61pci_write_tx_desc()
1864 skbdesc->desc = txd; in rt61pci_write_tx_desc()
1865 skbdesc->desc_len = (entry->queue->qid == QID_BEACON) ? TXINFO_SIZE : in rt61pci_write_tx_desc()
1875 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_write_beacon()
1876 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; in rt61pci_write_beacon()
1903 padding_len = roundup(entry->skb->len, 4) - entry->skb->len; in rt61pci_write_beacon()
1904 if (padding_len && skb_pad(entry->skb, padding_len)) { in rt61pci_write_beacon()
1907 entry->skb = NULL; in rt61pci_write_beacon()
1912 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); in rt61pci_write_beacon()
1914 entry_priv->desc, TXINFO_SIZE); in rt61pci_write_beacon()
1916 entry->skb->data, in rt61pci_write_beacon()
1917 entry->skb->len + padding_len); in rt61pci_write_beacon()
1922 * For Wi-Fi faily generated beacons between participating in rt61pci_write_beacon()
1933 dev_kfree_skb_any(entry->skb); in rt61pci_write_beacon()
1934 entry->skb = NULL; in rt61pci_write_beacon()
1939 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_clear_beacon()
1955 HW_BEACON_OFFSET(entry->entry_idx), 0); in rt61pci_clear_beacon()
1968 u8 offset = rt2x00dev->lna_gain; in rt61pci_agc_to_rssi()
1986 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_agc_to_rssi()
1991 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset; in rt61pci_agc_to_rssi()
1997 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_fill_rxdone()
1998 struct queue_entry_priv_mmio *entry_priv = entry->priv_data; in rt61pci_fill_rxdone()
2002 word0 = rt2x00_desc_read(entry_priv->desc, 0); in rt61pci_fill_rxdone()
2003 word1 = rt2x00_desc_read(entry_priv->desc, 1); in rt61pci_fill_rxdone()
2006 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; in rt61pci_fill_rxdone()
2008 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG); in rt61pci_fill_rxdone()
2009 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR); in rt61pci_fill_rxdone()
2011 if (rxdesc->cipher != CIPHER_NONE) { in rt61pci_fill_rxdone()
2012 rxdesc->iv[0] = _rt2x00_desc_read(entry_priv->desc, 2); in rt61pci_fill_rxdone()
2013 rxdesc->iv[1] = _rt2x00_desc_read(entry_priv->desc, 3); in rt61pci_fill_rxdone()
2014 rxdesc->dev_flags |= RXDONE_CRYPTO_IV; in rt61pci_fill_rxdone()
2016 rxdesc->icv = _rt2x00_desc_read(entry_priv->desc, 4); in rt61pci_fill_rxdone()
2017 rxdesc->dev_flags |= RXDONE_CRYPTO_ICV; in rt61pci_fill_rxdone()
2024 rxdesc->flags |= RX_FLAG_IV_STRIPPED; in rt61pci_fill_rxdone()
2030 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED; in rt61pci_fill_rxdone()
2032 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS) in rt61pci_fill_rxdone()
2033 rxdesc->flags |= RX_FLAG_DECRYPTED; in rt61pci_fill_rxdone()
2034 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC) in rt61pci_fill_rxdone()
2035 rxdesc->flags |= RX_FLAG_MMIC_ERROR; in rt61pci_fill_rxdone()
2044 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL); in rt61pci_fill_rxdone()
2045 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); in rt61pci_fill_rxdone()
2046 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT); in rt61pci_fill_rxdone()
2049 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP; in rt61pci_fill_rxdone()
2051 rxdesc->dev_flags |= RXDONE_SIGNAL_BITRATE; in rt61pci_fill_rxdone()
2053 rxdesc->dev_flags |= RXDONE_MY_BSS; in rt61pci_fill_rxdone()
2081 for (i = 0; i < rt2x00dev->tx->limit; i++) { in rt61pci_txdone()
2100 if (unlikely(index >= queue->limit)) in rt61pci_txdone()
2103 entry = &queue->entries[index]; in rt61pci_txdone()
2104 entry_priv = entry->priv_data; in rt61pci_txdone()
2105 word = rt2x00_desc_read(entry_priv->desc, 0); in rt61pci_txdone()
2117 entry_done->entry_idx); in rt61pci_txdone()
2128 case 0: /* Success, maybe with retry */ in rt61pci_txdone()
2137 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT); in rt61pci_txdone()
2141 * -> hw used fallback rates in rt61pci_txdone()
2143 if (txdesc.retry) in rt61pci_txdone()
2152 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf }; in rt61pci_wakeup()
2166 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2172 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2184 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2190 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2199 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_txstatus_tasklet()
2207 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_tbtt_tasklet()
2216 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_rxdone_tasklet()
2217 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_rxdone_tasklet()
2228 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_autowake_tasklet()
2251 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_interrupt()
2258 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_interrupt()
2261 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt61pci_interrupt()
2264 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt61pci_interrupt()
2267 tasklet_schedule(&rt2x00dev->autowake_tasklet); in rt61pci_interrupt()
2281 spin_lock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2291 spin_unlock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2319 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt61pci_validate_eeprom()
2380 if (value < -10 || value > 10) in rt61pci_validate_eeprom()
2383 if (value < -10 || value > 10) in rt61pci_validate_eeprom()
2396 if (value < -10 || value > 10) in rt61pci_validate_eeprom()
2399 if (value < -10 || value > 10) in rt61pci_validate_eeprom()
2431 return -ENODEV; in rt61pci_init_eeprom()
2438 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2443 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2445 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2452 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2458 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2465 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2467 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); in rt61pci_init_eeprom()
2475 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2477 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2486 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2488 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2489 ANTENNA_B - rt2x00_get_field16(eeprom, EEPROM_NIC_TX_FIXED); in rt61pci_init_eeprom()
2492 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2494 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2506 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt61pci_init_eeprom()
2507 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); in rt61pci_init_eeprom()
2509 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt61pci_init_eeprom()
2512 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); in rt61pci_init_eeprom()
2513 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, in rt61pci_init_eeprom()
2516 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, in rt61pci_init_eeprom()
2519 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, in rt61pci_init_eeprom()
2522 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, in rt61pci_init_eeprom()
2525 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, in rt61pci_init_eeprom()
2528 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, in rt61pci_init_eeprom()
2530 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, in rt61pci_init_eeprom()
2533 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, in rt61pci_init_eeprom()
2657 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt61pci_probe_hw_mode()
2665 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; in rt61pci_probe_hw_mode()
2670 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt61pci_probe_hw_mode()
2671 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt61pci_probe_hw_mode()
2672 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt61pci_probe_hw_mode()
2673 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt61pci_probe_hw_mode()
2675 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt61pci_probe_hw_mode()
2676 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt61pci_probe_hw_mode()
2689 rt2x00dev->hw->max_rates = 1; in rt61pci_probe_hw_mode()
2690 rt2x00dev->hw->max_report_rates = 7; in rt61pci_probe_hw_mode()
2691 rt2x00dev->hw->max_rate_tries = 1; in rt61pci_probe_hw_mode()
2696 spec->supported_bands = SUPPORT_BAND_2GHZ; in rt61pci_probe_hw_mode()
2697 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; in rt61pci_probe_hw_mode()
2700 spec->num_channels = 14; in rt61pci_probe_hw_mode()
2701 spec->channels = rf_vals_noseq; in rt61pci_probe_hw_mode()
2703 spec->num_channels = 14; in rt61pci_probe_hw_mode()
2704 spec->channels = rf_vals_seq; in rt61pci_probe_hw_mode()
2708 spec->supported_bands |= SUPPORT_BAND_5GHZ; in rt61pci_probe_hw_mode()
2709 spec->num_channels = ARRAY_SIZE(rf_vals_seq); in rt61pci_probe_hw_mode()
2715 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL); in rt61pci_probe_hw_mode()
2717 return -ENOMEM; in rt61pci_probe_hw_mode()
2719 spec->channels_info = info; in rt61pci_probe_hw_mode()
2727 if (spec->num_channels > 14) { in rt61pci_probe_hw_mode()
2729 for (i = 14; i < spec->num_channels; i++) { in rt61pci_probe_hw_mode()
2732 TXPOWER_FROM_DEV(tx_power[i - 14]); in rt61pci_probe_hw_mode()
2779 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2784 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2785 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2787 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2788 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2793 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt61pci_probe_hw()
2804 const struct ieee80211_tx_queue_params *params) in rt61pci_conf_tx() argument
2806 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_conf_tx()
2819 retval = rt2x00mac_conf_tx(hw, vif, link_id, queue_idx, params); in rt61pci_conf_tx()
2838 rt2x00_set_field32(®, field, queue->txop); in rt61pci_conf_tx()
2846 rt2x00_set_field32(®, field, queue->aifs); in rt61pci_conf_tx()
2850 rt2x00_set_field32(®, field, queue->cw_min); in rt61pci_conf_tx()
2854 rt2x00_set_field32(®, field, queue->cw_max); in rt61pci_conf_tx()
2862 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_get_tsf()
2940 switch (queue->qid) { in rt61pci_queue_init()
2942 queue->limit = 32; in rt61pci_queue_init()
2943 queue->data_size = DATA_FRAME_SIZE; in rt61pci_queue_init()
2944 queue->desc_size = RXD_DESC_SIZE; in rt61pci_queue_init()
2945 queue->priv_size = sizeof(struct queue_entry_priv_mmio); in rt61pci_queue_init()
2952 queue->limit = 32; in rt61pci_queue_init()
2953 queue->data_size = DATA_FRAME_SIZE; in rt61pci_queue_init()
2954 queue->desc_size = TXD_DESC_SIZE; in rt61pci_queue_init()
2955 queue->priv_size = sizeof(struct queue_entry_priv_mmio); in rt61pci_queue_init()
2959 queue->limit = 4; in rt61pci_queue_init()
2960 queue->data_size = 0; /* No DMA required for beacons */ in rt61pci_queue_init()
2961 queue->desc_size = TXINFO_SIZE; in rt61pci_queue_init()
2962 queue->priv_size = sizeof(struct queue_entry_priv_mmio); in rt61pci_queue_init()