Lines Matching refs:rt2x00_set_field32

88 	rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
92 	rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
93 	rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
95 	rt2x00_set_field32(&word, TXD_W1_BURST,
97 	rt2x00_set_field32(&word, TXD_W1_SD_LEN0, txwi_size);
98 	rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
99 	rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
103 	rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
108 	rt2x00_set_field32(&word, TXD_W3_WIV,
110 	rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
208 	rt2x00_set_field32(&reg, irq_field, 1);
240 			rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
245 			rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
349 		rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
399 		rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
400 		rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
401 		rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
402 		rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
403 		rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
432 		rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
437 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
438 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
439 		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
443 		rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
535 		rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
540 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
541 		rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
542 		rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
546 		rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
636 		rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
640 		rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
651 		rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
735 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
736 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
737 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
738 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
739 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
740 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
741 	rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
756 		rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
757 		rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
767 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
768 	rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);