Lines Matching +full:ieee80211 +full:- +full:freq +full:- +full:limit
1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include <linux/crc-ccitt.h>
27 #include <linux/nvmem-consumer.h>
88 mutex_lock(&rt2x00dev->csr_mutex);
105 mutex_unlock(&rt2x00dev->csr_mutex);
113 mutex_lock(&rt2x00dev->csr_mutex);
137 mutex_unlock(&rt2x00dev->csr_mutex);
147 mutex_lock(&rt2x00dev->csr_mutex);
153 switch (rt2x00dev->chip.rt) {
180 mutex_unlock(&rt2x00dev->csr_mutex);
229 mutex_lock(&rt2x00dev->csr_mutex);
239 switch (rt2x00dev->chip.rt) {
272 mutex_unlock(&rt2x00dev->csr_mutex);
288 mutex_lock(&rt2x00dev->csr_mutex);
305 mutex_unlock(&rt2x00dev->csr_mutex);
396 wiphy_name(rt2x00dev->hw->wiphy), word))
415 wiphy_name(rt2x00dev->hw->wiphy), word);
487 return -EIO;
527 mutex_lock(&rt2x00dev->csr_mutex);
545 mutex_unlock(&rt2x00dev->csr_mutex);
562 return -EBUSY;
585 return -EACCES;
607 switch (rt2x00dev->chip.rt) {
638 fw_crc = (data[len - 2] << 8 | data[len - 1]);
647 crc = crc_ccitt(~0, data, len - 2);
650 * There is a small difference between the crc-itu-t + bitrev and
651 * the crc-ccitt crc calculation. In the latter method the 2 bytes
724 return -EBUSY;
737 return -EBUSY;
771 return -EBUSY;
807 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
809 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
812 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
814 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
816 txdesc->u.ht.mpdu_density);
817 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
818 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
820 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
822 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
823 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
824 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
829 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
831 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
832 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
834 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
835 txdesc->key_idx : txdesc->u.ht.wcid);
837 txdesc->length);
838 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
839 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
851 for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
861 s8 base_val = rt2x00_rt(rt2x00dev, RT6352) ? -2 : -12;
867 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
886 rssi0 = (rssi0) ? (base_val - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
887 rssi1 = (rssi1) ? (base_val - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
888 rssi2 = (rssi2) ? (base_val - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
892 * average doesn't deliver a fair answer either since -60:-60 would
893 * be considered equally good as -50:-70 while the second is the one
903 __le32 *rxwi = (__le32 *) entry->skb->data;
908 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
909 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
914 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
917 rxdesc->bw = RATE_INFO_BW_40;
922 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
923 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
924 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
929 if (rxdesc->rate_mode == RATE_MODE_CCK)
930 rxdesc->signal &= ~0x8;
937 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
941 skb_pull(entry->skb, entry->queue->winfo_size);
964 idx -= 8;
974 skbdesc->tx_rate_idx = idx;
975 skbdesc->tx_rate_flags = flags;
990 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags))
1010 rt2x00_dbg(entry->queue->rt2x00dev,
1012 entry->queue->qid, entry->entry_idx);
1022 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1023 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1024 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1045 * If a frame was meant to be sent as a single non-aggregated MPDU
1065 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1085 * mcs - real_mcs
1088 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1096 txdesc.retry = rt2x00dev->long_retry;
1101 * -> hw used fallback rates
1107 /* RCU assures non-null sta will not be freed by mac80211. */
1110 skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1112 skbdesc->sta = NULL;
1129 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) {
1131 * TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus qid is
1145 if (unlikely(test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1146 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))) {
1148 entry->entry_idx, qid);
1164 if (!test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1167 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1172 ret = time_after(jiffies, entry->last_action + tout);
1174 rt2x00_dbg(entry->queue->rt2x00dev,
1176 entry->entry_idx, entry->queue->qid);
1219 * we loop until we find the first non-IO error entry. This
1228 if (test_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags) ||
1229 !test_bit(ENTRY_DATA_STATUS_PENDING, &entry->flags))
1232 if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags) ||
1246 if (queue->wd_idx != cur_idx) {
1247 queue->wd_idx = cur_idx;
1248 queue->wd_count = 0;
1250 queue->wd_count++;
1252 return queue->wd_count > 16;
1257 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
1259 &rt2x00dev->chan_survey[chan->hw_value];
1261 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
1262 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
1263 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
1275 switch (queue->qid) {
1290 if (rt2x00dev->intf_sta_count == 0)
1309 queue->wd_count = 0;
1322 rt2x00dev->rxdma_busy++;
1324 rt2x00dev->rxdma_busy = 0;
1328 rt2x00dev->txdma_busy++;
1330 rt2x00dev->txdma_busy = 0;
1332 busy_rx = rt2x00dev->rxdma_busy > 30;
1333 busy_tx = rt2x00dev->txdma_busy > 30;
1344 rt2x00dev->rxdma_busy = 0;
1345 rt2x00dev->txdma_busy = 0;
1354 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1357 if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_DMA_BUSY)
1360 if (rt2x00dev->link.watchdog & RT2800_WATCHDOG_HANG)
1364 ieee80211_restart_hw(rt2x00dev->hw);
1382 struct data_queue *queue = rt2x00dev->bcn;
1391 for (i = 0; i < queue->limit; i++) {
1392 entry = &queue->entries[i];
1393 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1395 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1408 bcn_num > 0 ? bcn_num - 1 : 0);
1414 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1415 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1419 const int txwi_desc_size = entry->queue->winfo_size;
1433 memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1438 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1439 skbdesc->desc = entry->skb->data;
1440 skbdesc->desc_len = txwi_desc_size;
1455 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1456 if (padding_len && skb_pad(entry->skb, padding_len)) {
1459 entry->skb = NULL;
1464 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1466 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1467 entry->skb->len + padding_len);
1468 __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1483 dev_kfree_skb_any(entry->skb);
1484 entry->skb = NULL;
1492 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1508 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1523 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1524 __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1605 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1607 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1610 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1615 if (rt2x00_is_soc(led->rt2x00dev)) {
1616 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1622 if (led->type == LED_TYPE_RADIO) {
1625 } else if (led->type == LED_TYPE_ASSOC) {
1628 } else if (led->type == LED_TYPE_QUALITY) {
1633 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1636 if (led->type == LED_TYPE_RADIO) {
1637 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1639 } else if (led->type == LED_TYPE_ASSOC) {
1640 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1642 } else if (led->type == LED_TYPE_QUALITY) {
1644 * The brightness is divided into 6 levels (0 - 5),
1649 * (1 << level) - 1
1651 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1652 (1 << brightness / (LED_FULL / 6)) - 1,
1661 led->rt2x00dev = rt2x00dev;
1662 led->type = type;
1663 led->led_dev.brightness_set = rt2800_brightness_set;
1664 led->flags = LED_INITIALIZED;
1720 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1722 if (crypto->cmd == SET_KEY) {
1725 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1732 (crypto->cipher & 0x7));
1734 (crypto->cipher & 0x8) >> 3);
1735 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1747 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1750 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1753 if ((crypto->cipher == CIPHER_TKIP) ||
1754 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1755 (crypto->cipher == CIPHER_AES))
1757 iveiv_entry.iv[3] |= key->keyidx << 6;
1771 if (crypto->cmd == SET_KEY) {
1772 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1774 memcpy(key_entry.key, crypto->key,
1776 memcpy(key_entry.tx_mic, crypto->tx_mic,
1778 memcpy(key_entry.rx_mic, crypto->rx_mic,
1781 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1793 field.bit_offset = 4 * (key->hw_key_idx % 8);
1796 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1800 (crypto->cmd == SET_KEY) * crypto->cipher);
1806 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1807 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1808 crypto->bssidx);
1822 if (crypto->cmd == SET_KEY) {
1827 if (crypto->wcid > WCID_END)
1828 return -ENOSPC;
1829 key->hw_key_idx = crypto->wcid;
1831 memcpy(key_entry.key, crypto->key,
1833 memcpy(key_entry.tx_mic, crypto->tx_mic,
1835 memcpy(key_entry.rx_mic, crypto->rx_mic,
1838 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1856 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1859 if (drv_data->ampdu_factor_cnt[i] > 0)
1862 max_psdu = min(drv_data->max_psdu, i);
1872 struct rt2x00_dev *rt2x00dev = hw->priv;
1873 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1878 * Limit global maximum TX AMPDU length to smallest value of all
1883 if (sta->deflink.ht_cap.ht_supported) {
1884 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]++;
1892 wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1898 sta_priv->wcid = wcid;
1902 * with the STA -> No error.
1907 __set_bit(wcid - WCID_START, drv_data->sta_ids);
1908 drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1914 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1924 struct rt2x00_dev *rt2x00dev = hw->priv;
1925 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1927 int wcid = sta_priv->wcid;
1929 if (sta->deflink.ht_cap.ht_supported) {
1930 drv_data->ampdu_factor_cnt[sta->deflink.ht_cap.ampdu_factor & 3]--;
1941 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1942 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1950 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1951 struct data_queue *queue = rt2x00dev->bcn;
1956 drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1957 __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1960 for (i = 0; i < queue->limit; i++) {
1961 entry = &queue->entries[i];
1962 clear_bit(ENTRY_BCN_ASSIGNED, &entry->flags);
1984 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
2023 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
2026 if (conf->sync == TSF_SYNC_AP_NONE) {
2048 conf->sync == TSF_SYNC_AP_NONE) {
2053 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
2057 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
2058 reg = le32_to_cpu(conf->mac[1]);
2060 conf->mac[1] = cpu_to_le32(reg);
2064 conf->mac, sizeof(conf->mac));
2068 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
2069 reg = le32_to_cpu(conf->bssid[1]);
2072 conf->bssid[1] = cpu_to_le32(reg);
2076 conf->bssid, sizeof(conf->bssid));
2084 bool any_sta_nongf = !!(erp->ht_opmode &
2086 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
2130 * -> fall through to mixed mode.
2143 if (erp->cts_protection) {
2185 !!erp->short_preamble);
2192 erp->cts_protection ? 2 : 0);
2198 0xff0 | erp->basic_rates);
2205 erp->slot_time);
2209 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
2216 erp->beacon_int * 16);
2240 return -EACCES;
2264 return -EACCES;
2274 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2338 switch (ant->tx_chain_num) {
2357 switch (ant->rx_chain_num) {
2368 rt2x00dev->default_ant.rx);
2377 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2393 if (ant->rx_chain_num == 1)
2407 if (libconf->rf.channel <= 14) {
2410 } else if (libconf->rf.channel <= 64) {
2413 } else if (libconf->rf.channel <= 128) {
2437 rt2x00dev->lna_gain = lna_gain;
2442 return clk_get_rate(rt2x00dev->clk) == 20000000;
2452 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2473 prev_freq_offset--;
2487 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2489 if (rt2x00dev->default_ant.tx_chain_num == 1)
2490 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2492 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2493 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2494 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2495 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2496 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2498 if (rf->channel > 14) {
2501 * make it a positive value (Minimum value is -7).
2505 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2506 (info->default_power1 >= 0));
2508 if (info->default_power1 < 0)
2509 info->default_power1 += 7;
2511 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2513 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2514 (info->default_power2 >= 0));
2516 if (info->default_power2 < 0)
2517 info->default_power2 += 7;
2519 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2521 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2522 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2525 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2527 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2528 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2529 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2530 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2534 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2535 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2536 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2537 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2541 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2542 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2543 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2544 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2552 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2555 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2558 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2562 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2566 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2570 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2576 rt2x00dev->default_ant.rx_chain_num <= 1);
2578 rt2x00dev->default_ant.rx_chain_num <= 2);
2581 rt2x00dev->default_ant.tx_chain_num <= 1);
2583 rt2x00dev->default_ant.tx_chain_num <= 2);
2587 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2595 calib_tx = drv_data->calibration_bw40;
2596 calib_rx = drv_data->calibration_bw40;
2598 calib_tx = drv_data->calibration_bw20;
2599 calib_rx = drv_data->calibration_bw20;
2630 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2634 if (rf->channel <= 14) {
2635 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2636 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2642 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2643 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2646 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2647 if (rf->channel <= 14)
2654 if (rf->channel <= 14)
2661 if (rf->channel <= 14) {
2664 info->default_power1);
2668 (info->default_power1 & 0x3) |
2669 ((info->default_power1 & 0xC) << 1));
2674 if (rf->channel <= 14) {
2677 info->default_power2);
2681 (info->default_power2 & 0x3) |
2682 ((info->default_power2 & 0xC) << 1));
2694 if (rf->channel <= 14) {
2701 switch (rt2x00dev->default_ant.tx_chain_num) {
2710 switch (rt2x00dev->default_ant.rx_chain_num) {
2722 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2726 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2727 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2729 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2730 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2733 if (rf->channel <= 14) {
2741 drv_data->txmixer_gain_24g);
2763 drv_data->txmixer_gain_5g);
2766 if (rf->channel <= 64) {
2770 } else if (rf->channel <= 128) {
2786 if (rf->channel <= 14)
2802 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2819 if (rf->channel <= 14) {
2821 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2822 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2832 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2833 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2836 rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2841 if (rf->channel <= 14)
2848 if (rf->channel <= 14) {
2851 info->default_power1 & 0x1f);
2857 ((info->default_power1 & 0x18) << 1) |
2858 (info->default_power1 & 7));
2863 if (rf->channel <= 14) {
2866 info->default_power2 & 0x1f);
2872 ((info->default_power2 & 0x18) << 1) |
2873 (info->default_power2 & 7));
2878 if (rf->channel <= 14) {
2881 info->default_power3 & 0x1f);
2887 ((info->default_power3 & 0x18) << 1) |
2888 (info->default_power3 & 7));
2902 switch (rt2x00dev->default_ant.tx_chain_num) {
2914 switch (rt2x00dev->default_ant.rx_chain_num) {
2930 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2932 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2935 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2937 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2947 if (rf->channel <= 14)
2960 if (rf->channel <= 14)
2967 if (rf->channel <= 14)
2974 if (rf->channel <= 14)
2981 if (rf->channel >= 1 && rf->channel <= 14)
2983 else if (rf->channel >= 36 && rf->channel <= 64)
2985 else if (rf->channel >= 100 && rf->channel <= 128)
2997 if (rf->channel <= 14) {
3010 if (rf->channel <= 14) {
3020 if (rf->channel <= 14)
3035 if (rf->channel <= 14)
3041 if (rf->channel <= 14) {
3051 if (rf->channel <= 14) {
3063 if (rf->channel >= 1 && rf->channel <= 14) {
3070 } else if (rf->channel >= 36 && rf->channel <= 64) {
3077 } else if (rf->channel >= 100 && rf->channel <= 128) {
3107 if (rf->channel <= 14)
3109 else if (rf->channel < 132)
3114 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3115 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3117 if (rf->channel <= 14)
3122 if (rf->channel <= 14)
3139 switch (rt2x00dev->default_ant.tx_chain_num) {
3151 switch (rt2x00dev->default_ant.rx_chain_num) {
3173 if (rf->channel <= 14)
3183 if (rf->channel <= 14)
3190 if (rf->channel <= 14)
3196 if (rf->channel <= 14)
3198 else if (rf->channel < 100)
3200 else if (rf->channel < 132)
3210 if (rf->channel <= 14)
3215 if (rf->channel <= 14)
3217 else if (rf->channel < 100)
3219 else if (rf->channel < 132)
3225 if (rf->channel <= 14)
3238 if (rf->channel <= 14)
3244 if (rf->channel <= 14)
3249 if (rf->channel <= 14) {
3250 pwr1 = info->default_power1 & 0x1f;
3251 pwr2 = info->default_power2 & 0x1f;
3252 pwr3 = info->default_power3 & 0x1f;
3254 pwr1 = 0x48 | ((info->default_power1 & 0x18) << 1) |
3255 (info->default_power1 & 0x7);
3256 pwr2 = 0x48 | ((info->default_power2 & 0x18) << 1) |
3257 (info->default_power2 & 0x7);
3258 pwr3 = 0x48 | ((info->default_power3 & 0x18) << 1) |
3259 (info->default_power3 & 0x7);
3267 rf->channel, pwr1, pwr2, pwr3);
3269 bbp = (info->default_power1 >> 5) |
3270 ((info->default_power2 & 0xe0) >> 1);
3275 bbp |= (info->default_power3 & 0xe0) >> 1;
3279 if (rf->channel <= 14)
3309 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3310 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3312 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3316 if (info->default_power1 > POWER_BOUND)
3319 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3324 if (rf->channel <= 14) {
3325 if (rf->channel == 6)
3330 if (rf->channel >= 1 && rf->channel <= 6)
3332 else if (rf->channel >= 7 && rf->channel <= 11)
3334 else if (rf->channel >= 12 && rf->channel <= 14)
3346 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3347 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3353 if (info->default_power1 > POWER_BOUND)
3356 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3358 if (info->default_power2 > POWER_BOUND)
3361 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3369 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3374 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3393 int idx = rf->channel-1;
3395 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3396 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3398 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
3402 if (info->default_power1 > POWER_BOUND)
3405 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3410 if (info->default_power2 > POWER_BOUND)
3414 info->default_power2);
3500 (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
3504 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3507 rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
3508 rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
3509 rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
3513 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
3514 rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
3517 if (rf->channel <= 14) {
3549 /* TODO RF27 <- tssi */
3551 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
3591 /* TODO RF27 <- tssi */
3593 if (rf->channel >= 36 && rf->channel <= 64) {
3599 if (rf->channel <= 50)
3601 else if (rf->channel >= 52)
3610 if (rf->channel <= 50) {
3613 } else if (rf->channel >= 52) {
3622 } else if (rf->channel >= 100 && rf->channel <= 165) {
3627 if (rf->channel <= 153) {
3630 } else if (rf->channel >= 155) {
3634 if (rf->channel <= 138) {
3639 } else if (rf->channel >= 140) {
3645 if (rf->channel <= 124)
3647 else if (rf->channel >= 126)
3649 if (rf->channel <= 138)
3651 else if (rf->channel >= 140)
3654 if (rf->channel <= 138)
3656 else if (rf->channel >= 140)
3658 if (rf->channel <= 128)
3660 else if (rf->channel >= 130)
3662 if (rf->channel <= 116)
3664 else if (rf->channel >= 118)
3666 if (rf->channel <= 138)
3668 else if (rf->channel >= 140)
3670 if (rf->channel <= 116)
3672 else if (rf->channel >= 118)
3681 if (info->default_power1 > power_bound)
3684 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3690 if (info->default_power2 > power_bound)
3693 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3703 rt2x00dev->default_ant.tx_chain_num >= 1);
3705 rt2x00dev->default_ant.tx_chain_num == 2);
3709 rt2x00dev->default_ant.rx_chain_num >= 1);
3711 rt2x00dev->default_ant.rx_chain_num == 2);
3736 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3737 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3738 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3740 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3741 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3742 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3743 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3747 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3749 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3751 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3753 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3755 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3757 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3765 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3779 * R20[7:0] in rf->rf1
3783 rfcsr = (rf->rf1 & 0x00ff);
3791 * R16[3:0] (RF PLL freq selection)
3805 * Ksd: R17<7:0> in rf->rf2
3806 * R18<7:0> in rf->rf3
3807 * R19<1:0> in rf->rf4
3810 rfcsr = rf->rf2;
3814 rfcsr = rf->rf3;
3818 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3832 rt2x00dev->default_ant.tx_chain_num != 1);
3837 rt2x00dev->default_ant.tx_chain_num != 1);
3839 rt2x00dev->default_ant.rx_chain_num != 1);
3844 rt2x00dev->default_ant.tx_chain_num != 1);
3872 conf_is_ht40(conf) && (rf->channel == 11));
3875 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3877 rx_agc_fc = drv_data->rx_calibration_bw40;
3878 tx_agc_fc = drv_data->tx_calibration_bw40;
3880 rx_agc_fc = drv_data->rx_calibration_bw20;
3881 tx_agc_fc = drv_data->tx_calibration_bw20;
3923 int cur_channel = rt2x00dev->rf_channel;
3935 power_level = (power_level - 3) * 2;
3946 power_level -= rate_power;
3953 chan_power = power_group[cnt][cur_channel - 1];
3987 if (chan->center_freq > 2457) {
4017 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
4136 bbp = (rf->channel > 14) ? 0x48 : 0x38;
4141 if (rf->channel <= 14) {
4150 if (rf->channel > 14) {
4170 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4171 info->default_power1);
4172 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4173 info->default_power2);
4174 if (rt2x00dev->default_ant.tx_chain_num > 2)
4175 info->default_power3 =
4176 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4177 info->default_power3);
4179 switch (rt2x00dev->chip.rt) {
4185 switch (rt2x00dev->chip.rf) {
4262 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4263 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4264 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4267 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4269 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4273 if (rf->channel > 14) {
4285 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4286 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4287 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4290 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4291 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4292 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4294 if (rt2x00dev->default_ant.rx_chain_num > 1)
4299 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4300 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4301 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4308 if (rf->channel <= 14) {
4349 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
4350 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
4363 switch (rt2x00dev->default_ant.tx_chain_num) {
4367 rf->channel > 14);
4369 rf->channel <= 14);
4374 rf->channel > 14);
4376 rf->channel <= 14);
4381 rf->channel > 14);
4386 rf->channel <= 14);
4390 switch (rt2x00dev->default_ant.rx_chain_num) {
4417 if (rf->channel <= 14)
4418 reg = 0x1c + (2 * rt2x00dev->lna_gain);
4420 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4433 if (rf->channel <= 14)
4458 if (rf->channel <= 14)
4459 reg = 0x1c + 2 * rt2x00dev->lna_gain;
4461 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4475 if (rf->channel <= 14)
4476 reg = 0x2e + rt2x00dev->lna_gain;
4478 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4489 bbp = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
4492 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4505 if (rt2x00dev->default_ant.rx_chain_num == 1) {
4520 bbp = rf->channel <= 14 ? 0x04 + 2 * rt2x00dev->lna_gain : 0;
4586 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
4589 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4674 for (i = 8; i >= 5; i--) {
4680 return (i - 4) * step;
4697 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4709 comp_value = -comp_value;
4720 comp_value = -comp_value;
4740 * Hence, we assume the regulatory limit that cfg80211 calulated for
4744 delta = power_level - max_power;
4787 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4791 (eirp_txpower - power_level) : 0;
4795 txpower = max(0, txpower + delta - reg_limit);
4827 enum nl80211_band band = chan->band;
4843 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5197 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5200 (i - TX_PWR_CFG_9_IDX - 1) : i,
5213 enum nl80211_band band = chan->band;
5223 /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
5226 * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
5228 * used a fixed offset between HT20 and HT40 rates they had to work-
5273 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5290 * registers. As recent 2T chips use 8-bit instead of 4-bit values for
5291 * power-offsets more space would be needed. Ralink decided to keep the
5333 * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
5346 enum nl80211_band band = chan->band;
5361 switch (rt2x00dev->chip.rt) {
5382 chan->max_power);
5386 * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
5389 * regulatory limit, however this could be utilized for devices with
5392 if (delta <= -12) {
5395 } else if (delta <= -6) {
5536 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5537 rt2x00dev->tx_power);
5548 * A voltage-controlled oscillator(VCO) is an electronic oscillator
5559 switch (rt2x00dev->chip.rf) {
5597 rt2x00dev->chip.rf);
5605 if (rt2x00dev->rf_channel <= 14) {
5606 switch (rt2x00dev->default_ant.tx_chain_num) {
5619 switch (rt2x00dev->default_ant.tx_chain_num) {
5643 libconf->conf->short_frame_max_tx_count);
5645 libconf->conf->long_frame_max_tx_count);
5653 (libconf->conf->flags & IEEE80211_CONF_PS) ?
5663 libconf->conf->listen_interval - 1);
5667 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5675 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5688 * To provide correct survey data for survey-based ACS algorithm
5693 rt2800_config_channel(rt2x00dev, libconf->conf,
5694 &libconf->rf, &libconf->channel);
5695 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5696 libconf->conf->power_level);
5699 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5700 libconf->conf->power_level);
5719 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5727 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5739 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5741 vgc = 0x2e + rt2x00dev->lna_gain;
5745 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5747 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5749 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5750 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5752 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5762 if (qual->vgc_level != vgc_level) {
5770 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5776 qual->vgc_level = vgc_level;
5777 qual->vgc_level_reg = vgc_level;
5802 switch (rt2x00dev->chip.rt) {
5805 if (qual->rssi > -65) {
5806 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5814 if (qual->rssi > -65)
5819 if (qual->rssi > -65)
5824 if (qual->rssi > -80)
5838 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6050 drv_data->max_psdu = 3;
6054 drv_data->max_psdu = 2;
6056 drv_data->max_psdu = 1;
6058 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
6255 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6627 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
6977 rt2x00dev->default_ant.rx_chain_num == 2);
7048 rt2x00dev->default_ant.rx_chain_num == 2);
7257 switch (rt2x00dev->chip.rt) {
7370 if ((passband - stopband) <= filter_target) {
7372 overtuned += ((passband - stopband) == filter_target);
7379 rfcsr24 -= !!overtuned;
7400 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7416 drv_data->calibration_bw20 =
7418 drv_data->calibration_bw40 =
7424 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7425 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7446 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7462 if (drv_data->txmixer_gain_24g >= min_gain) {
7464 drv_data->txmixer_gain_24g);
7517 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7526 tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
7752 &rt2x00dev->cap_flags);
7754 &rt2x00dev->cap_flags);
7964 if (rt2x00dev->default_ant.rx_chain_num == 1)
8007 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8073 drv_data->calibration_bw20 = 0x1f;
8074 drv_data->calibration_bw40 = 0x2f;
8077 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
8078 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
8554 int calcode = ((d2 - d1) * 1000) / 43;
8632 d1 = bytevalue - 256;
8642 d2 = bytevalue - 256;
8750 for (i = 15; i >= 0; i = i - 1) {
8816 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
8876 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
8960 result = (bbptemp & 0xffffff) - 0x1000000;
8976 bbpval1 = si - mi * mi;
9004 sigma_i = rt2800_do_sqrt_accumulation(100 * (si - mi * mi));
9005 sigma_q = rt2800_do_sqrt_accumulation(100 * (sq - mq * mq));
9006 r_iq = 10 * (riq - (mi * mq));
9011 (sigma_i - sigma_q) <= 112 &&
9012 (sigma_i - sigma_q) >= -112 &&
9013 mi <= 32 && mi >= -32 &&
9014 mq <= 32 && mq >= -32) {
9015 r_iq = 10 * (riq - (mi * mq));
9020 g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
9023 if (ph_rx > 20 || ph_rx < -20) {
9028 if (g_imb > 12 || g_imb < -12) {
9287 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9289 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9296 tidxi = 0x40 - tidx;
9307 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9309 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9333 fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
9335 fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
9374 for (bidx = 5; bidx >= 0; bidx--) {
9380 idx0 = idxf[iorq] - ibit;
9431 for (bidx = 5; bidx >= 1; bidx--) {
9447 idx0 = iq_err - ibit;
9501 gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
9502 perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
9504 gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
9505 gsta = gerr - 1;
9508 perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
9509 psta = perr - 1;
9695 vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
9816 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9824 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9843 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9868 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9878 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
9894 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9913 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9920 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
9925 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9929 vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
9970 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9986 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
10096 cal_val -= 128;
10104 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10181 /* I-3 */
10188 /* I-4,5,6,7,8,9 */
10273 cal_diff = cal_r32_init - cal_r32_val;
10296 drv_data->tx_calibration_bw20 = tx_agc_fc;
10298 drv_data->tx_calibration_bw40 = tx_agc_fc;
10301 drv_data->rx_calibration_bw20 = rx_agc_fc;
10303 drv_data->rx_calibration_bw40 = rx_agc_fc;
10343 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
10487 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
10747 switch (rt2x00dev->chip.rt) {
10799 return -EIO;
10805 return -EIO;
10821 return -EIO;
10931 mutex_lock(&rt2x00dev->csr_mutex);
10944 *(__le32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
10946 *(__le32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
10948 *(__le32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
10950 *(__le32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
10952 mutex_unlock(&rt2x00dev->csr_mutex);
10968 struct device_node *np = rt2x00dev->dev->of_node;
10969 unsigned int len = rt2x00dev->ops->eeprom_size;
10985 dev_err(rt2x00dev->dev, "invalid eeprom size, required: 0x%04x\n", len);
10987 return -EINVAL;
10990 memcpy(rt2x00dev->eeprom, data, len);
11028 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
11091 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
11119 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
11133 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
11232 return -ENODEV;
11240 rt2x00dev->default_ant.tx_chain_num =
11242 rt2x00dev->default_ant.rx_chain_num =
11257 rt2x00dev->default_ant.tx = ANTENNA_A;
11258 rt2x00dev->default_ant.rx = ANTENNA_A;
11261 rt2x00dev->default_ant.tx = ANTENNA_A;
11262 rt2x00dev->default_ant.rx = ANTENNA_B;
11266 rt2x00dev->default_ant.tx = ANTENNA_A;
11267 rt2x00dev->default_ant.rx = ANTENNA_A;
11273 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
11274 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
11281 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
11283 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
11289 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
11292 * Detect if this device has Bluetooth co-existence.
11296 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
11302 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
11308 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
11309 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
11310 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
11312 rt2x00dev->led_mcu_reg = eeprom;
11316 * Check if support EIRP tx power limit feature.
11322 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
11334 &rt2x00dev->cap_flags);
11338 &rt2x00dev->cap_flags);
11347 &rt2x00dev->cap_flags);
11349 &rt2x00dev->cap_flags);
11729 struct hw_mode_spec *spec = &rt2x00dev->spec;
11740 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
11746 rt2x00dev->hw->wiphy->retry_short = 2;
11747 rt2x00dev->hw->wiphy->retry_long = 2;
11752 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
11753 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
11754 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
11755 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
11756 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
11766 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
11768 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
11770 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
11771 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
11784 rt2x00dev->hw->max_rates = 1;
11785 rt2x00dev->hw->max_report_rates = 7;
11786 rt2x00dev->hw->max_rate_tries = 1;
11791 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
11793 switch (rt2x00dev->chip.rf) {
11796 spec->num_channels = 14;
11797 spec->channels = rf_vals;
11802 spec->num_channels = ARRAY_SIZE(rf_vals);
11803 spec->channels = rf_vals;
11821 spec->num_channels = 14;
11823 spec->channels = rf_vals_3x_xtal20;
11825 spec->channels = rf_vals_3x;
11829 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
11830 spec->channels = rf_vals_7620;
11835 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
11836 spec->channels = rf_vals_3x;
11840 spec->num_channels = ARRAY_SIZE(rf_vals_3853);
11841 spec->channels = rf_vals_3853;
11847 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
11848 spec->channels = rf_vals_5592_xtal40;
11850 spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
11851 spec->channels = rf_vals_5592_xtal20;
11856 if (WARN_ON_ONCE(!spec->channels))
11857 return -ENODEV;
11859 spec->supported_bands = SUPPORT_BAND_2GHZ;
11860 if (spec->num_channels > 14)
11861 spec->supported_bands |= SUPPORT_BAND_5GHZ;
11867 spec->ht.ht_supported = true;
11869 spec->ht.ht_supported = false;
11871 spec->ht.cap =
11877 tx_chains = rt2x00dev->default_ant.tx_chain_num;
11878 rx_chains = rt2x00dev->default_ant.rx_chain_num;
11881 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
11883 spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
11885 spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
11886 spec->ht.ampdu_density = 4;
11887 spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
11889 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
11890 spec->ht.mcs.tx_params |=
11891 (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
11896 spec->ht.mcs.rx_mask[2] = 0xff;
11899 spec->ht.mcs.rx_mask[1] = 0xff;
11902 spec->ht.mcs.rx_mask[0] = 0xff;
11903 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
11910 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
11912 return -ENOMEM;
11914 rt2x00dev->chan_survey =
11915 kcalloc(spec->num_channels, sizeof(struct rt2x00_chan_survey),
11917 if (!rt2x00dev->chan_survey) {
11919 return -ENOMEM;
11922 spec->channels_info = info;
11927 if (rt2x00dev->default_ant.tx_chain_num > 2)
11940 if (spec->num_channels > 14) {
11946 if (rt2x00dev->default_ant.tx_chain_num > 2)
11953 for (i = 14; i < spec->num_channels; i++) {
11954 info[i].default_power1 = default_power1[i - 14];
11955 info[i].default_power2 = default_power2[i - 14];
11957 info[i].default_power3 = default_power3[i - 14];
11961 switch (rt2x00dev->chip.rf) {
11981 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
12023 return -ENODEV;
12072 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
12073 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
12075 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
12081 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
12082 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
12083 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
12085 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
12086 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
12087 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
12089 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
12091 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
12092 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
12095 rt2x00dev->link.watchdog = modparam_watchdog;
12098 rt2x00dev->link.watchdog &= ~RT2800_WATCHDOG_DMA_BUSY;
12099 if (rt2x00dev->link.watchdog) {
12100 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
12101 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
12107 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
12114 * IEEE80211 stack callback functions.
12120 struct rt2x00_dev *rt2x00dev = hw->priv;
12124 if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
12127 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
12131 memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
12132 memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
12138 struct rt2x00_dev *rt2x00dev = hw->priv;
12179 struct rt2x00_dev *rt2x00dev = hw->priv;
12211 rt2x00_set_field32(®, field, queue->txop);
12219 rt2x00_set_field32(®, field, queue->aifs);
12223 rt2x00_set_field32(®, field, queue->cw_min);
12227 rt2x00_set_field32(®, field, queue->cw_max);
12234 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
12235 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
12236 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
12237 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
12246 struct rt2x00_dev *rt2x00dev = hw->priv;
12262 struct ieee80211_sta *sta = params->sta;
12263 enum ieee80211_ampdu_mlme_action action = params->action;
12264 u16 tid = params->tid;
12265 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
12275 if (sta_priv->wcid > WCID_END)
12276 return -ENOSPC;
12294 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
12299 rt2x00_warn((struct rt2x00_dev *)hw->priv,
12310 struct rt2x00_dev *rt2x00dev = hw->priv;
12312 &rt2x00dev->chan_survey[idx];
12315 if (idx >= rt2x00dev->bands[band].n_channels) {
12316 idx -= rt2x00dev->bands[band].n_channels;
12320 if (idx >= rt2x00dev->bands[band].n_channels)
12321 return -ENOENT;
12326 survey->channel = &rt2x00dev->bands[band].channels[idx];
12328 survey->filled = SURVEY_INFO_TIME |
12332 survey->time = div_u64(chan_survey->time_idle + chan_survey->time_busy, 1000);
12333 survey->time_busy = div_u64(chan_survey->time_busy, 1000);
12334 survey->time_ext_busy = div_u64(chan_survey->time_ext_busy, 1000);
12336 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
12337 survey->filled |= SURVEY_INFO_IN_USE;