Lines Matching +full:dw +full:- +full:high +full:- +full:reset

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
36  * Default offset is required for RSSI <-> dBm conversion.
70  * SOFT_RESET: Software reset, 1: reset, 0: normal.
71  * BBP_RESET: Hardware reset, 1: reset, 0, release.
218  * KICK_DECRYPT: Kick decryption engine, self-clear.
228  * CSR11: Back-off control register.
229  * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
230  * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
267  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
287  * CFP: ASIC is in contention-free period.
452  * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
545  * RX_TRESHOLD: Rx threshold in dw to start pci access
546  * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
547  * TX_TRESHOLD: Tx threshold in dw to start pci access
548  * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
549  * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
550  * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
647  * KICK_RX: Kick one-shot rx in one-shot rx mode.
648  * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
649  * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
665  * RALINKCSR: Ralink Rx auto-reset BBCR.
666  * AR_BBP_DATA#: Auto reset BBP register # data.
667  * AR_BBP_ID#: Auto reset BBP register # id.
730  * LINK_POLARITY: 0: active low, 1: active high.
731  * ACTIVITY_POLARITY: 0: active low, 1: active high.
818  * MACCSR2: TX_PE to RX_PE turn-around time control register
891  * KICK_ENCRYPT: Kick encryption engine, self-clear.
1072  * RSSI <-> dBm offset calibration
1136  * Word6-9: Key
1198  * Word6-9: Key