Lines Matching +full:0 +full:x000000ff
20 #define RF2420 0x0000
21 #define RF2421 0x0001
32 #define CSR_REG_BASE 0x0000
33 #define CSR_REG_SIZE 0x014c
34 #define EEPROM_BASE 0x0000
35 #define EEPROM_SIZE 0x0100
36 #define BBP_BASE 0x0000
37 #define BBP_SIZE 0x0020
38 #define RF_BASE 0x0004
39 #define RF_SIZE 0x000c
54 #define CSR0 0x0000
55 #define CSR0_REVISION FIELD32(0x0000ffff)
59 * SOFT_RESET: Software reset, 1: reset, 0: normal.
60 * BBP_RESET: Hardware reset, 1: reset, 0, release.
63 #define CSR1 0x0004
64 #define CSR1_SOFT_RESET FIELD32(0x00000001)
65 #define CSR1_BBP_RESET FIELD32(0x00000002)
66 #define CSR1_HOST_READY FIELD32(0x00000004)
71 #define CSR2 0x0008
74 * CSR3: STA MAC address register 0.
76 #define CSR3 0x000c
77 #define CSR3_BYTE0 FIELD32(0x000000ff)
78 #define CSR3_BYTE1 FIELD32(0x0000ff00)
79 #define CSR3_BYTE2 FIELD32(0x00ff0000)
80 #define CSR3_BYTE3 FIELD32(0xff000000)
85 #define CSR4 0x0010
86 #define CSR4_BYTE4 FIELD32(0x000000ff)
87 #define CSR4_BYTE5 FIELD32(0x0000ff00)
90 * CSR5: BSSID register 0.
92 #define CSR5 0x0014
93 #define CSR5_BYTE0 FIELD32(0x000000ff)
94 #define CSR5_BYTE1 FIELD32(0x0000ff00)
95 #define CSR5_BYTE2 FIELD32(0x00ff0000)
96 #define CSR5_BYTE3 FIELD32(0xff000000)
101 #define CSR6 0x0018
102 #define CSR6_BYTE4 FIELD32(0x000000ff)
103 #define CSR6_BYTE5 FIELD32(0x0000ff00)
116 #define CSR7 0x001c
117 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
118 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
119 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
120 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
121 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
122 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
123 #define CSR7_RXDONE FIELD32(0x00000040)
136 #define CSR8 0x0020
137 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
138 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
139 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
140 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
141 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
142 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
143 #define CSR8_RXDONE FIELD32(0x00000040)
149 #define CSR9 0x0024
150 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
160 #define CSR11 0x002c
161 #define CSR11_CWMIN FIELD32(0x0000000f)
162 #define CSR11_CWMAX FIELD32(0x000000f0)
163 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
164 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
165 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
168 * CSR12: Synchronization configuration register 0.
173 #define CSR12 0x0030
174 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
175 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
181 * CFP_PERIOD: Cfp period, default is 0 TU.
183 #define CSR13 0x0034
184 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
185 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
190 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
198 #define CSR14 0x0038
199 #define CSR14_TSF_COUNT FIELD32(0x00000001)
200 #define CSR14_TSF_SYNC FIELD32(0x00000006)
201 #define CSR14_TBCN FIELD32(0x00000008)
202 #define CSR14_TCFP FIELD32(0x00000010)
203 #define CSR14_TATIMW FIELD32(0x00000020)
204 #define CSR14_BEACON_GEN FIELD32(0x00000040)
205 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
206 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
214 #define CSR15 0x003c
215 #define CSR15_CFP FIELD32(0x00000001)
216 #define CSR15_ATIMW FIELD32(0x00000002)
217 #define CSR15_BEACON_SENT FIELD32(0x00000004)
220 * CSR16: TSF timer register 0.
222 #define CSR16 0x0040
223 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
228 #define CSR17 0x0044
229 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
232 * CSR18: IFS timer register 0.
236 #define CSR18 0x0048
237 #define CSR18_SIFS FIELD32(0x0000ffff)
238 #define CSR18_PIFS FIELD32(0xffff0000)
245 #define CSR19 0x004c
246 #define CSR19_DIFS FIELD32(0x0000ffff)
247 #define CSR19_EIFS FIELD32(0xffff0000)
255 #define CSR20 0x0050
256 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
257 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
258 #define CSR20_AUTOWAKE FIELD32(0x01000000)
263 * TYPE_93C46: 1: 93c46, 0:93c66.
265 #define CSR21 0x0054
266 #define CSR21_RELOAD FIELD32(0x00000001)
267 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
268 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
269 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
270 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
271 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
278 #define CSR22 0x0058
279 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
280 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
294 #define TXCSR0 0x0060
295 #define TXCSR0_KICK_TX FIELD32(0x00000001)
296 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
297 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
298 #define TXCSR0_ABORT FIELD32(0x00000008)
307 #define TXCSR1 0x0064
308 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
309 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
310 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
311 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
320 #define TXCSR2 0x0068
321 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
322 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
323 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
324 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
329 #define TXCSR3 0x006c
330 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
335 #define TXCSR4 0x0070
336 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
341 #define TXCSR5 0x0074
342 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
347 #define TXCSR6 0x0078
348 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
354 #define TXCSR7 0x007c
355 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
373 #define RXCSR0 0x0080
374 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
375 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
376 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
377 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
378 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
379 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
380 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
381 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
388 #define RXCSR1 0x0084
389 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
390 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
395 #define RXCSR2 0x0088
396 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
403 #define RXCSR3 0x0090
404 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
405 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
406 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
407 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
408 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
409 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
410 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
411 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
418 #define RXCSR4 0x0094
419 #define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
420 #define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
421 #define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
422 #define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
425 * ARCSR0: Auto Responder PLCP config register 0.
429 #define ARCSR0 0x0098
430 #define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
431 #define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
432 #define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
433 #define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
440 #define ARCSR1 0x009c
441 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
442 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
443 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
444 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
453 * BIG_ENDIAN: 1: big endian, 0: little endian.
455 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
457 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
458 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
461 #define PCICSR 0x008c
462 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
463 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
464 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
465 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
466 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
472 #define CNT0 0x00a0
473 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
483 #define TIMECSR2 0x00a8
484 #define CNT1 0x00ac
485 #define CNT2 0x00b0
486 #define TIMECSR3 0x00b4
487 #define CNT3 0x00b8
488 #define CNT4 0x00bc
489 #define CNT5 0x00c0
498 #define PWRCSR0 0x00c4
503 #define PSCSR0 0x00c8
504 #define PSCSR1 0x00cc
505 #define PSCSR2 0x00d0
506 #define PSCSR3 0x00d4
510 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
518 #define PWRCSR1 0x00d8
519 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
520 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
521 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
522 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
523 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
524 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
532 #define TIMECSR 0x00dc
533 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
534 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
535 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
538 * MACCSR0: MAC configuration register 0.
540 #define MACCSR0 0x00e0
549 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
552 #define MACCSR1 0x00e4
553 #define MACCSR1_KICK_RX FIELD32(0x00000001)
554 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
555 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
556 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
557 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
558 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
559 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
566 #define RALINKCSR 0x00e8
567 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
568 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
569 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
570 #define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
580 #define BCNCSR 0x00ec
581 #define BCNCSR_CHANGE FIELD32(0x00000001)
582 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
583 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
584 #define BCNCSR_MODE FIELD32(0x00006000)
585 #define BCNCSR_PLUS FIELD32(0x00008000)
596 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
598 #define BBPCSR 0x00f0
599 #define BBPCSR_VALUE FIELD32(0x000000ff)
600 #define BBPCSR_REGNUM FIELD32(0x00007f00)
601 #define BBPCSR_BUSY FIELD32(0x00008000)
602 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
608 * IF_SELECT: Chip to program: 0: rf, 1: if.
612 #define RFCSR 0x00f4
613 #define RFCSR_VALUE FIELD32(0x00ffffff)
614 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
615 #define RFCSR_IF_SELECT FIELD32(0x20000000)
616 #define RFCSR_PLL_LD FIELD32(0x40000000)
617 #define RFCSR_BUSY FIELD32(0x80000000)
623 * LINK: 0: linkoff, 1: linkup.
624 * ACTIVITY: 0: idle, 1: active.
626 #define LEDCSR 0x00f8
627 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
628 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
629 #define LEDCSR_LINK FIELD32(0x00010000)
630 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
639 #define RXPTR 0x0100
640 #define TXPTR 0x0104
641 #define PRIPTR 0x0108
642 #define ATIMPTR 0x010c
651 * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
653 #define GPIOCSR 0x0120
654 #define GPIOCSR_VAL0 FIELD32(0x00000001)
655 #define GPIOCSR_VAL1 FIELD32(0x00000002)
656 #define GPIOCSR_VAL2 FIELD32(0x00000004)
657 #define GPIOCSR_VAL3 FIELD32(0x00000008)
658 #define GPIOCSR_VAL4 FIELD32(0x00000010)
659 #define GPIOCSR_VAL5 FIELD32(0x00000020)
660 #define GPIOCSR_VAL6 FIELD32(0x00000040)
661 #define GPIOCSR_VAL7 FIELD32(0x00000080)
662 #define GPIOCSR_DIR0 FIELD32(0x00000100)
663 #define GPIOCSR_DIR1 FIELD32(0x00000200)
664 #define GPIOCSR_DIR2 FIELD32(0x00000400)
665 #define GPIOCSR_DIR3 FIELD32(0x00000800)
666 #define GPIOCSR_DIR4 FIELD32(0x00001000)
667 #define GPIOCSR_DIR5 FIELD32(0x00002000)
668 #define GPIOCSR_DIR6 FIELD32(0x00004000)
669 #define GPIOCSR_DIR7 FIELD32(0x00008000)
674 #define BBPPCSR 0x0124
680 #define BCNCSR1 0x0130
681 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
687 #define MACCSR2 0x0134
688 #define MACCSR2_DELAY FIELD32(0x000000ff)
693 #define ARCSR2 0x013c
694 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
695 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
696 #define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
697 #define ARCSR2_LENGTH FIELD32(0xffff0000)
702 #define ARCSR3 0x0140
703 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
704 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
705 #define ARCSR3_LENGTH FIELD32(0xffff0000)
710 #define ARCSR4 0x0144
711 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
712 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
713 #define ARCSR4_LENGTH FIELD32(0xffff0000)
718 #define ARCSR5 0x0148
719 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
720 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
721 #define ARCSR5_LENGTH FIELD32(0xffff0000)
731 #define BBP_R1_TX_ANTENNA FIELD8(0x03)
736 #define BBP_R4_RX_ANTENNA FIELD8(0x06)
745 #define RF1_TUNER FIELD32(0x00020000)
750 #define RF3_TUNER FIELD32(0x00000100)
751 #define RF3_TXPOWER FIELD32(0x00003e00)
761 #define EEPROM_MAC_ADDR_0 0x0002
762 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
763 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
764 #define EEPROM_MAC_ADDR1 0x0003
765 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
766 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
767 #define EEPROM_MAC_ADDR_2 0x0004
768 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
769 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
774 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
775 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
777 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
778 * RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
781 #define EEPROM_ANTENNA 0x0b
782 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
783 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
784 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
785 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
786 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
787 #define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
788 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
793 #define EEPROM_BBP_START 0x0c
795 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
796 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
801 #define EEPROM_TXPOWER_START 0x13
803 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
804 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
819 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
820 #define TXD_W0_VALID FIELD32(0x00000002)
821 #define TXD_W0_RESULT FIELD32(0x0000001c)
822 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
823 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
824 #define TXD_W0_ACK FIELD32(0x00000200)
825 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
826 #define TXD_W0_RTS FIELD32(0x00000800)
827 #define TXD_W0_IFS FIELD32(0x00006000)
828 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
829 #define TXD_W0_AGC FIELD32(0x00ff0000)
830 #define TXD_W0_R2 FIELD32(0xff000000)
835 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
840 #define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
841 #define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
847 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
848 #define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
849 #define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
850 #define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
851 #define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
852 #define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
854 #define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
855 #define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
856 #define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
857 #define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
858 #define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
859 #define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
864 #define TXD_W5_BBCR4 FIELD32(0x0000ffff)
865 #define TXD_W5_AGC_REG FIELD32(0x007f0000)
866 #define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
867 #define TXD_W5_XXX_REG FIELD32(0x7f000000)
868 #define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
873 #define TXD_W6_SK_BUFF FIELD32(0xffffffff)
878 #define TXD_W7_RESERVED FIELD32(0xffffffff)
887 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
888 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
889 #define RXD_W0_MULTICAST FIELD32(0x00000004)
890 #define RXD_W0_BROADCAST FIELD32(0x00000008)
891 #define RXD_W0_MY_BSS FIELD32(0x00000010)
892 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
893 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
894 #define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
899 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
904 #define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
905 #define RXD_W2_BBR0 FIELD32(0x00ff0000)
906 #define RXD_W2_SIGNAL FIELD32(0xff000000)
911 #define RXD_W3_RSSI FIELD32(0x000000ff)
912 #define RXD_W3_BBR3 FIELD32(0x0000ff00)
913 #define RXD_W3_BBR4 FIELD32(0x00ff0000)
914 #define RXD_W3_BBR5 FIELD32(0xff000000)
919 #define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
924 #define RXD_W5_RESERVED FIELD32(0xffffffff)
925 #define RXD_W6_RESERVED FIELD32(0xffffffff)
926 #define RXD_W7_RESERVED FIELD32(0xffffffff)