Lines Matching +full:0 +full:x83000000
73 #define MT_RRO_TOP_BASE 0xA000
76 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8)
77 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC)
78 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8)
80 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34)
83 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38)
84 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C)
85 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40)
88 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C)
89 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60)
93 #define MT_RRO_BA_BITMAP_BASE_EXT0 MT_RRO_TOP(0x70)
94 #define MT_RRO_BA_BITMAP_BASE_EXT1 MT_RRO_TOP(0x74)
95 #define MT_RRO_HOST_INT_ENA MT_RRO_TOP(0x204)
96 #define MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA BIT(0)
98 #define MT_RRO_ADDR_ELEM_SEG_ADDR0 MT_RRO_TOP(0x400)
100 #define MT_RRO_ACK_SN_CTRL MT_RRO_TOP(0x50)
102 #define MT_RRO_ACK_SN_CTRL_SESSION_MASK GENMASK(11, 0)
104 #define MT_RRO_DBG_RD_CTRL MT_RRO_TOP(0xe0)
105 #define MT_RRO_DBG_RD_ADDR GENMASK(15, 0)
108 #define MT_RRO_DBG_RDAT_DW(_n) MT_RRO_TOP(0xf0 + (_n) * 0x4)
110 #define MT_MCU_INT_EVENT 0x2108
111 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
116 #define MT_PLE_BASE 0x820c0000
119 #define MT_FL_Q_EMPTY MT_PLE(0x360)
120 #define MT_FL_Q0_CTRL MT_PLE(0x3e0)
121 #define MT_FL_Q2_CTRL MT_PLE(0x3e8)
122 #define MT_FL_Q3_CTRL MT_PLE(0x3ec)
124 #define MT_PLE_FREEPG_CNT MT_PLE(0x380)
125 #define MT_PLE_FREEPG_HEAD_TAIL MT_PLE(0x384)
126 #define MT_PLE_PG_HIF_GROUP MT_PLE(0x00c)
127 #define MT_PLE_HIF_PG_INFO MT_PLE(0x388)
129 #define MT_PLE_AC_QEMPTY(ac, n) MT_PLE(0x600 + 0x80 * (ac) + ((n) << 2))
130 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
133 #define MT_MDP_BASE 0x820cc000
136 #define MT_MDP_DCR2 MT_MDP(0x8e8)
139 /* TMAC: band 0(0x820e4000), band 1(0x820f4000), band 2(0x830e4000) */
143 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
146 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x0c8)
147 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x0cc)
148 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
151 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x014)
152 #define MT_IFS_EIFS_OFDM GENMASK(8, 0)
157 #define MT_TMAC_ICR1(_band) MT_WF_TMAC(_band, 0x018)
158 #define MT_IFS_EIFS_CCK GENMASK(8, 0)
160 /* WF DMA TOP: band 0(0x820e7000), band 1(0x820f7000), band 2(0x830e7000) */
164 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
167 #define MT_DMA_TCRF1(_band) MT_WF_DMA(_band, 0x054)
170 /* WTBLOFF TOP: band 0(0x820e9000), band 1(0x820f9000), band 2(0x830e9000) */
174 #define MT_WTBLOFF_RSCR(_band) MT_WTBLOFF(_band, 0x008)
178 #define MT_WTBLOFF_ACR(_band) MT_WTBLOFF(_band, 0x010)
181 /* ETBF: band 0(0x820ea000), band 1(0x820fa000), band 2(0x830ea000) */
185 #define MT_ETBF_RX_FB_CONT(_band) MT_WF_ETBF(_band, 0x100)
188 #define MT_ETBF_RX_FB_NR GENMASK(3, 0)
190 /* LPON: band 0(0x820eb000), band 1(0x820fb000), band 2(0x830eb000) */
194 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x360)
195 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x364)
196 #define MT_LPON_FRCR(_band) MT_WF_LPON(_band, 0x37c)
198 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (((n) * 4) << 4))
199 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
200 #define MT_LPON_TCR_SW_WRITE BIT(0)
202 #define MT_LPON_TCR_SW_READ GENMASK(1, 0)
204 /* MIB: band 0(0x820ed000), band 1(0x820fd000), band 2(0x830ed000)*/
224 #define MT_MIB_TSCR5(_band) MT_WF_MIB(_band, 0x6c4)
225 #define MT_MIB_TSCR6(_band) MT_WF_MIB(_band, 0x6c8)
226 #define MT_MIB_TSCR7(_band) MT_WF_MIB(_band, 0x6d0)
233 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
234 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
242 #define MT_MIB_TSCR0(_band) MT_WF_MIB(_band, 0x6b0)
243 #define MT_MIB_TSCR2(_band) MT_WF_MIB(_band, 0x6b8)
246 #define MT_MIB_TSCR3(_band) MT_WF_MIB(_band, 0x6bc)
249 #define MT_MIB_TSCR4(_band) MT_WF_MIB(_band, 0x6c0)
264 #define MT_MIB_SDR27(_band) MT_WF_MIB(_band, 0x080)
265 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT GENMASK(15, 0)
267 #define MT_MIB_SDR28(_band) MT_WF_MIB(_band, 0x084)
268 #define MT_MIB_SDR28_TX_RWP_NEED_CNT GENMASK(15, 0)
273 #define MT_MIB_TSCR1(_band) MT_WF_MIB(_band, 0x6b4)
275 #define MT_MIB_BTSCR0(_band) MT_WF_MIB(_band, 0x5e0)
279 #define MT_MIB_BFTFCR(_band) MT_WF_MIB(_band, 0x5d0)
282 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
283 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 4)) & GENMASK(9, 0))
286 #define MT_WF_UMIB_BASE 0x820cd000
289 #define MT_UMIB_RPDCR(_band) (MT_WF_UMIB(0x594) + (_band) * 0x164)
292 #define MT_WTBLON_TOP_BASE 0x820d4000
294 #define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x370)
295 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(4, 0)
297 #define MT_WTBL_UPDATE MT_WTBLON_TOP(0x380)
298 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(11, 0)
302 #define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0)
305 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8)
306 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc)
310 #define MT_WTBL_BASE 0x820d8000
317 /* AGG: band 0(0x820e2000), band 1(0x820f2000), band 2(0x830e2000) */
321 #define MT_AGG_ACR4(_band) MT_WF_AGG(_band, 0x3c)
324 /* ARB: band 0(0x820e3000), band 1(0x820f3000), band 2(0x830e3000) */
328 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x000)
332 /* RMAC: band 0(0x820e5000), band 1(0x820f5000), band 2(0x830e5000), */
336 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
337 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
358 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
365 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
368 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)
370 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384)
373 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c)
374 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)
376 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390)
377 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)
379 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x03e0)
382 /* RATE: band 0(0x820ee000), band 1(0x820fe000), band 2(0x830ee000) */
386 #define MT_RATE_HRCR0(_band) MT_WF_RATE(_band, 0x050)
387 #define MT_RATE_HRCR0_CFEND_RATE GENMASK(14, 0)
390 #define MT_WFDMA0_BASE 0xd4000
393 #define MT_WFDMA0_RST MT_WFDMA0(0x100)
397 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
398 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
402 #define MT_WFDMA0_RX_INT_PCIE_SEL MT_WFDMA0(0x154)
406 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
408 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
409 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
416 #define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268)
417 #define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c)
418 #define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270)
419 #define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c)
421 #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
425 #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4)
429 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
430 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
431 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
432 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
435 #define MT_WFDMA1_BASE 0xd5000
438 #define MT_WFDMA_EXT_CSR_BASE 0xd7000
441 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30)
442 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
445 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
446 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
448 #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500)
449 #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0)
451 #define MT_PCIE_RECOG_ID 0xd7090
452 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
456 #define MT_WFDMA0_PCIE1_BASE 0xd8000
459 #define MT_INT_PCIE1_SOURCE_CSR_EXT MT_WFDMA0_PCIE1(0x118)
460 #define MT_INT_PCIE1_MASK_CSR MT_WFDMA0_PCIE1(0x11c)
462 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
463 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
472 #define MT_Q_BASE(q) ((dev->q_wfdma_mask >> (q)) & 0x1 ? \
479 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)
480 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)
481 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)
482 #define MT_RXQ_RRO_IND_RING_BASE MT_RRO_TOP(0x40)
484 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
485 MT_MCUQ_ID(q) * 0x4)
486 #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
487 MT_RXQ_ID(q) * 0x4)
488 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
489 MT_TXQ_ID(q) * 0x4)
491 #define MT_INT_SOURCE_CSR MT_WFDMA0(0x200)
492 #define MT_INT_MASK_CSR MT_WFDMA0(0x204)
494 #define MT_INT1_SOURCE_CSR MT_WFDMA0_PCIE1(0x200)
495 #define MT_INT1_MASK_CSR MT_WFDMA0_PCIE1(0x204)
500 #define MT_INT_RX_DONE_WM BIT(0)
567 #define MT_MCU_CMD MT_WFDMA0(0x1f0)
579 #define MT_HIF_REMAP_L1 0x155024
581 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
583 #define MT_HIF_REMAP_BASE_L1 0x130000
585 #define MT_HIF_REMAP_L2 0x1b4
586 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
587 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
589 #define MT_HIF_REMAP_BASE_L2 0x1000
591 #define MT_INFRA_BASE 0x18000000
592 #define MT_WFSYS0_PHY_START 0x18400000
593 #define MT_WFSYS1_PHY_START 0x18800000
594 #define MT_WFSYS1_PHY_END 0x18bfffff
595 #define MT_CBTOP1_PHY_START 0x70000000
596 #define MT_CBTOP1_PHY_END 0x77ffffff
597 #define MT_CBTOP2_PHY_START 0xf0000000
598 #define MT_INFRA_MCU_START 0x7c000000
599 #define MT_INFRA_MCU_END 0x7c3fffff
602 #define MT_FW_ASSERT_CNT 0x02208274
603 #define MT_FW_DUMP_STATE 0x02209e90
605 #define MT_SWDEF_BASE 0x00401400
608 #define MT_SWDEF_MODE MT_SWDEF(0x3c)
609 #define MT_SWDEF_NORMAL_MODE 0
611 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
612 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
613 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
614 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04c)
615 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
616 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)
617 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)
618 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05c)
619 #define MT_SWDEF_LAMC_WISR6_BN2_STATS MT_SWDEF(0x060)
620 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x064)
621 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x068)
622 #define MT_SWDEF_LAMC_WISR7_BN2_STATS MT_SWDEF(0x06c)
625 #define MT_LED_TOP_BASE 0x18013000
628 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))
634 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))
635 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)
638 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
641 #define MT_CONN_DBG_CTL_BASE 0x18023000
643 #define MT_CONN_DBG_CTL_OUT_SEL MT_CONN_DBG_CTL(0x604)
644 #define MT_CONN_DBG_CTL_PC_LOG_SEL MT_CONN_DBG_CTL(0x60c)
645 #define MT_CONN_DBG_CTL_PC_LOG MT_CONN_DBG_CTL(0x610)
647 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
648 #define MT_LED_GPIO_MUX3 0x7000505C /* GPIO 26 */
652 #define MT_TOP_BASE 0xe0000
655 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
656 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
660 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
661 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
663 #define MT_TOP_MISC MT_TOP(0xf0)
664 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
667 #define MT_ADIE_CHIP_ID(_idx) (0x0f00002c + ((_idx) << 28))
668 #define MT_ADIE_VERSION_MASK GENMASK(15, 0)
671 #define MT_PAD_GPIO 0x700056f0
678 #define MT_HW_REV 0x70010204
679 #define MT_HW_REV1 0x8a00
681 #define MT_WF_SUBSYS_RST 0x70028600
684 #define MT_PCIE_MAC_BASE 0x74030000
686 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
688 #define MT_PCIE1_MAC_BASE 0x74090000
691 #define MT_PCIE1_MAC_INT_ENABLE MT_PCIE1_MAC(0x188)
694 #define MT_WF_PHYRX_CSD_BASE 0x83000000
698 #define MT_WF_PHYRX_CSD_IRPI(_band, _wf) MT_WF_PHYRX_CSD(_band, _wf, 0x1000)
701 #define MT_WF_PHYRX_BAND_BASE 0x83080000
705 #define MT_WF_PHYRX_BAND_GID_TAB_VLD0(_band) MT_WF_PHYRX_BAND(_band, 0x1054)
706 #define MT_WF_PHYRX_BAND_GID_TAB_VLD1(_band) MT_WF_PHYRX_BAND(_band, 0x1058)
707 #define MT_WF_PHYRX_BAND_GID_TAB_POS0(_band) MT_WF_PHYRX_BAND(_band, 0x105c)
708 #define MT_WF_PHYRX_BAND_GID_TAB_POS1(_band) MT_WF_PHYRX_BAND(_band, 0x1060)
709 #define MT_WF_PHYRX_BAND_GID_TAB_POS2(_band) MT_WF_PHYRX_BAND(_band, 0x1064)
710 #define MT_WF_PHYRX_BAND_GID_TAB_POS3(_band) MT_WF_PHYRX_BAND(_band, 0x1068)
712 #define MT_WF_PHYRX_BAND_RX_CTRL1(_band) MT_WF_PHYRX_BAND(_band, 0x2004)
713 #define MT_WF_PHYRX_BAND_RX_CTRL1_IPI_EN GENMASK(2, 0)
717 #define MT_WF_PHYRX_CSD_BAND_RXTD12(_band) MT_WF_PHYRX_BAND(_band, 0x8230)
722 #define MT_MCU_WM_EXCP_BASE 0x89050000
724 #define MT_MCU_WM_EXCP_PC_CTRL MT_MCU_WM_EXCP(0x100)
725 #define MT_MCU_WM_EXCP_PC_LOG MT_MCU_WM_EXCP(0x104)
726 #define MT_MCU_WM_EXCP_LR_CTRL MT_MCU_WM_EXCP(0x200)
727 #define MT_MCU_WM_EXCP_LR_LOG MT_MCU_WM_EXCP(0x204)
730 #define MT_AFE_CTL_BASE 0x18043000
732 ((_band) * 0x1000) + (ofs))
733 #define MT_AFE_CTL_BAND_PLL_03(_band) MT_AFE_CTL_BAND(_band, 0x2c)