21 	[WF_AGG_BASE]		= { { 0x820e2000, 0x820f2000, 0x830e2000 } },
22 	[WF_ARB_BASE]		= { { 0x820e3000, 0x820f3000, 0x830e3000 } },
23 	[WF_TMAC_BASE]		= { { 0x820e4000, 0x820f4000, 0x830e4000 } },
24 	[WF_RMAC_BASE]		= { { 0x820e5000, 0x820f5000, 0x830e5000 } },
25 	[WF_DMA_BASE]		= { { 0x820e7000, 0x820f7000, 0x830e7000 } },
26 	[WF_WTBLOFF_BASE]	= { { 0x820e9000, 0x820f9000, 0x830e9000 } },
27 	[WF_ETBF_BASE]		= { { 0x820ea000, 0x820fa000, 0x830ea000 } },
28 	[WF_LPON_BASE]		= { { 0x820eb000, 0x820fb000, 0x830eb000 } },
29 	[WF_MIB_BASE]		= { { 0x820ed000, 0x820fd000, 0x830ed000 } },
30 	[WF_RATE_BASE]		= { { 0x820ee000, 0x820fe000, 0x830ee000 } },
34 	[MIB_RVSR0]		= 0x720,
35 	[MIB_RVSR1]		= 0x724,
36 	[MIB_BTSCR5]		= 0x788,
37 	[MIB_BTSCR6]		= 0x798,
38 	[MIB_RSCR1]		= 0x7ac,
39 	[MIB_RSCR27]		= 0x954,
40 	[MIB_RSCR28]		= 0x958,
41 	[MIB_RSCR29]		= 0x95c,
42 	[MIB_RSCR30]		= 0x960,
43 	[MIB_RSCR31]		= 0x964,
44 	[MIB_RSCR33]		= 0x96c,
45 	[MIB_RSCR35]		= 0x974,
46 	[MIB_RSCR36]		= 0x978,
47 	[MIB_BSCR0]		= 0x9cc,
48 	[MIB_BSCR1]		= 0x9d0,
49 	[MIB_BSCR2]		= 0x9d4,
50 	[MIB_BSCR3]		= 0x9d8,
51 	[MIB_BSCR4]		= 0x9dc,
52 	[MIB_BSCR5]		= 0x9e0,
53 	[MIB_BSCR6]		= 0x9e4,
54 	[MIB_BSCR7]		= 0x9e8,
55 	[MIB_BSCR17]		= 0xa10,
56 	[MIB_TRDR1]		= 0xa28,
60 	[MIB_RVSR0]		= 0x760,
61 	[MIB_RVSR1]		= 0x764,
62 	[MIB_BTSCR5]		= 0x7c8,
63 	[MIB_BTSCR6]		= 0x7d8,
64 	[MIB_RSCR1]		= 0x7f0,
65 	[MIB_RSCR27]		= 0x998,
66 	[MIB_RSCR28]		= 0x99c,
67 	[MIB_RSCR29]		= 0x9a0,
68 	[MIB_RSCR30]		= 0x9a4,
69 	[MIB_RSCR31]		= 0x9a8,
70 	[MIB_RSCR33]		= 0x9b0,
71 	[MIB_RSCR35]		= 0x9b8,
72 	[MIB_RSCR36]		= 0x9bc,
73 	[MIB_BSCR0]		= 0xac8,
74 	[MIB_BSCR1]		= 0xacc,
75 	[MIB_BSCR2]		= 0xad0,
76 	[MIB_BSCR3]		= 0xad4,
77 	[MIB_BSCR4]		= 0xad8,
78 	[MIB_BSCR5]		= 0xadc,
79 	[MIB_BSCR6]		= 0xae0,
80 	[MIB_BSCR7]		= 0xae4,
81 	[MIB_BSCR17]		= 0xb0c,
82 	[MIB_TRDR1]		= 0xb24,
86 	{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
87 	{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
88 	{ 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */
89 	{ 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */
90 	{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
91 	{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
92 	{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
93 	{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
94 	{ 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
95 	{ 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */
96 	{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
97 	{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
98 	{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
99 	{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
100 	{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
101 	{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
102 	{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
103 	{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
104 	{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
105 	{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
106 	{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
107 	{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
108 	{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
109 	{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
110 	{ 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
111 	{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
112 	{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
113 	{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
114 	{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
115 	{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
116 	{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
117 	{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
118 	{ 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
119 	{ 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
120 	{ 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
121 	{ 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
122 	{ 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
123 	{ 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
124 	{ 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
125 	{ 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
126 	{ 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
127 	{ 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
128 	{ 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */
129 	{ 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
130 	{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
131 	{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
132 	{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */
133 	{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
134 	{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
135 	{ 0x0, 0x0, 0x0 }, /* imply end of search */
170 	if (addr < 0x100000)  in __mt7996_reg_addr()
173 	for (i = 0; i < dev->reg.map_size; i++) {  in __mt7996_reg_addr()
186 	return 0;  in __mt7996_reg_addr()
308 	u32 hif1_ofs = 0;  in mt7996_mmio_wed_init()
311 		return 0;  in mt7996_mmio_wed_init()
315 	hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_mmio_wed_init()
324 				      pci_resource_start(pci_dev, 0),  in mt7996_mmio_wed_init()
325 				      pci_resource_len(pci_dev, 0));  in mt7996_mmio_wed_init()
326 	wed->wlan.phy_base = pci_resource_start(pci_dev, 0);  in mt7996_mmio_wed_init()
334 					     MT_TXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
338 						 MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
343 						 MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
353 		wed->wlan.id = 0x7991;  in mt7996_mmio_wed_init()
354 		wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1;  in mt7996_mmio_wed_init()
359 		wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
368 		wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base +  in mt7996_mmio_wed_init()
382 		wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1;  in mt7996_mmio_wed_init()
385 		wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1;  in mt7996_mmio_wed_init()
388 		wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1;  in mt7996_mmio_wed_init()
392 		wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1;  in mt7996_mmio_wed_init()
395 			wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
400 			wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) +  in mt7996_mmio_wed_init()
423 		return 0;  in mt7996_mmio_wed_init()
430 	return 0;  in mt7996_mmio_wed_init()
446 	case 0x7990:  in mt7996_mmio_init()
452 	case 0x7992:  in mt7996_mmio_init()
473 	mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff);  in mt7996_mmio_init()
477 	return 0;  in mt7996_mmio_init()
522 	u32 i, intr, mask, intr1 = 0;  in mt7996_irq_tasklet()
525 		mtk_wed_device_irq_set_mask(wed_hif2, 0);  in mt7996_irq_tasklet()
533 		mtk_wed_device_irq_set_mask(wed, 0);  in mt7996_irq_tasklet()
537 		mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7996_irq_tasklet()
539 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7996_irq_tasklet()
562 	for (i = 0; i < __MT_RXQ_MAX; i++) {  in mt7996_irq_tasklet()
583 		mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0);  in mt7996_irq_handler()
585 		mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7996_irq_handler()
589 			mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0);  in mt7996_irq_handler()
591 			mt76_wr(dev, MT_INT1_MASK_CSR, 0);  in mt7996_irq_handler()
641 	mt76_wr(dev, MT_INT_MASK_CSR, 0);  in mt7996_mmio_probe()