14 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
16 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
57 		dev->backup_l1 = 0;  in mt7925_reg_remap_restore()
62 		dev->backup_l2 = 0;  in mt7925_reg_remap_restore()
103 		{ 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */  in __mt7925_reg_addr()
104 		{ 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */  in __mt7925_reg_addr()
105 		{ 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */  in __mt7925_reg_addr()
106 		{ 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */  in __mt7925_reg_addr()
107 		{ 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */  in __mt7925_reg_addr()
108 		{ 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */  in __mt7925_reg_addr()
109 		{ 0x59000000, 0x007000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA1 */  in __mt7925_reg_addr()
110 		{ 0x820c0000, 0x008000, 0x0004000 }, /* WF_UMAC_TOP (PLE) */  in __mt7925_reg_addr()
111 		{ 0x820c8000, 0x00c000, 0x0002000 }, /* WF_UMAC_TOP (PSE) */  in __mt7925_reg_addr()
112 		{ 0x820cc000, 0x00e000, 0x0002000 }, /* WF_UMAC_TOP (PP) */  in __mt7925_reg_addr()
113 		{ 0x74030000, 0x010000, 0x0001000 }, /* PCIe MAC */  in __mt7925_reg_addr()
114 		{ 0x820e0000, 0x020000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */  in __mt7925_reg_addr()
115 		{ 0x820e1000, 0x020400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */  in __mt7925_reg_addr()
116 		{ 0x820e2000, 0x020800, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */  in __mt7925_reg_addr()
117 		{ 0x820e3000, 0x020c00, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */  in __mt7925_reg_addr()
118 		{ 0x820e4000, 0x021000, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */  in __mt7925_reg_addr()
119 		{ 0x820e5000, 0x021400, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */  in __mt7925_reg_addr()
120 		{ 0x820ce000, 0x021c00, 0x0000200 }, /* WF_LMAC_TOP (WF_SEC) */  in __mt7925_reg_addr()
121 		{ 0x820e7000, 0x021e00, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */  in __mt7925_reg_addr()
122 		{ 0x820cf000, 0x022000, 0x0001000 }, /* WF_LMAC_TOP (WF_PF) */  in __mt7925_reg_addr()
123 		{ 0x820e9000, 0x023400, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */  in __mt7925_reg_addr()
124 		{ 0x820ea000, 0x024000, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */  in __mt7925_reg_addr()
125 		{ 0x820eb000, 0x024200, 0x0000400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */  in __mt7925_reg_addr()
126 		{ 0x820ec000, 0x024600, 0x0000200 }, /* WF_LMAC_TOP BN0 (WF_INT) */  in __mt7925_reg_addr()
127 		{ 0x820ed000, 0x024800, 0x0000800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */  in __mt7925_reg_addr()
128 		{ 0x820ca000, 0x026000, 0x0002000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */  in __mt7925_reg_addr()
129 		{ 0x820d0000, 0x030000, 0x0010000 }, /* WF_LMAC_TOP (WF_WTBLON) */  in __mt7925_reg_addr()
130 		{ 0x40000000, 0x070000, 0x0010000 }, /* WF_UMAC_SYSRAM */  in __mt7925_reg_addr()
131 		{ 0x00400000, 0x080000, 0x0010000 }, /* WF_MCU_SYSRAM */  in __mt7925_reg_addr()
132 		{ 0x00410000, 0x090000, 0x0010000 }, /* WF_MCU_SYSRAM (configure register) */  in __mt7925_reg_addr()
133 		{ 0x820f0000, 0x0a0000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */  in __mt7925_reg_addr()
134 		{ 0x820f1000, 0x0a0600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */  in __mt7925_reg_addr()
135 		{ 0x820f2000, 0x0a0800, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */  in __mt7925_reg_addr()
136 		{ 0x820f3000, 0x0a0c00, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */  in __mt7925_reg_addr()
137 		{ 0x820f4000, 0x0a1000, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */  in __mt7925_reg_addr()
138 		{ 0x820f5000, 0x0a1400, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */  in __mt7925_reg_addr()
139 		{ 0x820f7000, 0x0a1e00, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */  in __mt7925_reg_addr()
140 		{ 0x820f9000, 0x0a3400, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */  in __mt7925_reg_addr()
141 		{ 0x820fa000, 0x0a4000, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */  in __mt7925_reg_addr()
142 		{ 0x820fb000, 0x0a4200, 0x0000400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */  in __mt7925_reg_addr()
143 		{ 0x820fc000, 0x0a4600, 0x0000200 }, /* WF_LMAC_TOP BN1 (WF_INT) */  in __mt7925_reg_addr()
144 		{ 0x820fd000, 0x0a4800, 0x0000800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */  in __mt7925_reg_addr()
145 		{ 0x820c4000, 0x0a8000, 0x0004000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */  in __mt7925_reg_addr()
146 		{ 0x820b0000, 0x0ae000, 0x0001000 }, /* [APB2] WFSYS_ON */  in __mt7925_reg_addr()
147 		{ 0x80020000, 0x0b0000, 0x0010000 }, /* WF_TOP_MISC_OFF */  in __mt7925_reg_addr()
148 		{ 0x81020000, 0x0c0000, 0x0010000 }, /* WF_TOP_MISC_ON */  in __mt7925_reg_addr()
149 		{ 0x7c020000, 0x0d0000, 0x0010000 }, /* CONN_INFRA, wfdma */  in __mt7925_reg_addr()
150 		{ 0x7c060000, 0x0e0000, 0x0010000 }, /* CONN_INFRA, conn_host_csr_top */  in __mt7925_reg_addr()
151 		{ 0x7c000000, 0x0f0000, 0x0010000 }, /* CONN_INFRA */  in __mt7925_reg_addr()
152 		{ 0x70020000, 0x1f0000, 0x0010000 }, /* Reserved for CBTOP, can't switch */  in __mt7925_reg_addr()
153 		{ 0x7c500000, 0x060000, 0x2000000 }, /* remap */  in __mt7925_reg_addr()
154 		{ 0x0, 0x0, 0x0 } /* End */  in __mt7925_reg_addr()
158 	if (addr < 0x200000)  in __mt7925_reg_addr()
163 	for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {  in __mt7925_reg_addr()
176 	if ((addr >= 0x18000000 && addr < 0x18c00000) ||  in __mt7925_reg_addr()
177 	    (addr >= 0x70000000 && addr < 0x78000000) ||  in __mt7925_reg_addr()
178 	    (addr >= 0x7c000000 && addr < 0x7c400000))  in __mt7925_reg_addr()
221 					 MT_TX_RING_BASE, NULL, 0);  in mt7925_dma_init()
225 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);  in mt7925_dma_init()
254 	if (ret < 0)  in mt7925_dma_init()
316 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));  in mt7925_pci_probe()
328 	if (ret < 0)  in mt7925_pci_probe()
357 	mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);  in mt7925_pci_probe()
388 		    (mt76_rr(dev, MT_HW_REV) & 0xff);  in mt7925_pci_probe()
398 	mt76_wr(dev, irq_map.host_irq_enable, 0);  in mt7925_pci_probe()
400 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);  in mt7925_pci_probe()
415 	return 0;  in mt7925_pci_probe()
455 	if (err < 0)  in mt7925_pci_suspend()
477 		  MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);  in mt7925_pci_suspend()
484 	mt76_wr(dev, dev->irq_map->host_irq_enable, 0);  in mt7925_pci_suspend()
489 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);  in mt7925_pci_suspend()
498 	return 0;  in mt7925_pci_suspend()
514 	if (err < 0)  in mt7925_pci_suspend()
529 	if (err < 0)  in mt7925_pci_resume()
535 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);  in mt7925_pci_resume()
565 	if (err < 0)  in mt7925_pci_resume()