Lines Matching +full:0 +full:x65c
129 #define MT_MCU_WFDMA0_BASE 0x2000
132 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
135 #define MT_MCU_WFDMA1_BASE 0x3000
139 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
145 #define MT_PLE_BASE 0x820c0000
148 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
153 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
154 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
164 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
166 #define MT_PSE_BASE 0x820c8000
170 #define MT_MDP_BASE 0x820cd000
173 #define MT_MDP_DCR0 MT_MDP(0x000)
177 #define MT_MDP_DCR1 MT_MDP(0x004)
180 #define MT_MDP_DCR2 MT_MDP(0x0e8)
194 #define MT_MDP_TO_HIF 0
197 /* TRB: band 0(0x820e1000), band 1(0x820f1000) */
198 #define MT_WF_TRB_BASE(_band) ((_band) ? 0x820f1000 : 0x820e1000)
201 #define MT_TRB_RXPSR0(_band) MT_WF_TRB(_band, 0x03c)
203 #define MT_TRB_RXPSR0_RX_RMAC_PTR GENMASK(9, 0)
205 /* TMAC: band 0(0x820e4000), band 1(0x820f4000) */
206 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
209 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
215 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
219 #define MT_TMAC_ATCR_TXV_TOUT GENMASK(7, 0)
222 #define MT_TMAC_TRCR0_TR2T_CHK GENMASK(8, 0)
226 #define MT_IFS_EIFS_OFDM GENMASK(8, 0)
232 #define MT_IFS_EIFS_CCK GENMASK(8, 0)
235 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
241 /* WF DMA TOP: band 0(0x820e7000),band 1(0x820f7000) */
242 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
245 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
249 /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */
250 #define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000)
253 #define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008)
257 /* ETBF: band 0(0x820ea000), band 1(0x820fa000) */
258 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000)
261 #define MT_ETBF_TX_NDP_BFRP(_band) MT_WF_ETBF(_band, 0x040)
263 #define MT_ETBF_TX_FB_TRI GENMASK(15, 0)
268 #define MT_ETBF_PAR_RPT0_FB_NR GENMASK(2, 0)
270 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x0f0)
272 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
274 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x0f8)
278 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
280 /* LPON: band 0(0x820eb000), band 1(0x820fb000) */
281 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
288 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + \
290 #define MT_LPON_TCR_MT7916(_band, n) MT_WF_LPON(_band, 0x0a8 + \
292 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
293 #define MT_LPON_TCR_SW_WRITE BIT(0)
295 #define MT_LPON_TCR_SW_READ GENMASK(1, 0)
297 /* MIB: band 0(0x820ed000), band 1(0x820fd000) */
304 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
307 #define MT_MIB_SDR0(_band) MT_WF_MIB(_band, 0x010)
308 #define MT_MIB_SDR0_BERACON_TX_CNT_MASK GENMASK(15, 0)
311 #define MT_MIB_SDR3_FCS_ERR_MASK GENMASK(15, 0)
315 #define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0)
320 #define MT_MIB_SDR6(_band) MT_WF_MIB(_band, 0x020)
321 #define MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK GENMASK(15, 0)
324 #define MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK GENMASK(15, 0)
327 #define MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK GENMASK(15, 0)
331 #define MT_MIB_SDR9_CCA_BUSY_TIME_MASK GENMASK(23, 0)
334 #define MT_MIB_SDR10_MRDY_COUNT_MASK GENMASK(25, 0)
335 #define MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916 GENMASK(31, 0)
338 #define MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK GENMASK(15, 0)
344 #define MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK GENMASK(15, 0)
348 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK GENMASK(23, 0)
349 #define MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916 GENMASK(31, 0)
353 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK GENMASK(23, 0)
354 #define MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916 GENMASK(31, 0)
358 #define MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
361 #define MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK GENMASK(23, 0)
364 #define MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK GENMASK(23, 0)
368 #define MT_MIB_SDR19_CCK_MDRDY_TIME_MASK GENMASK(23, 0)
371 #define MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK GENMASK(23, 0)
374 #define MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK GENMASK(23, 0)
384 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK GENMASK(23, 0)
385 #define MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916 GENMASK(31, 0)
392 #define MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK GENMASK(15, 0)
395 #define MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK GENMASK(15, 0)
398 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK GENMASK(7, 0)
399 #define MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916 GENMASK(15, 0)
402 #define MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK GENMASK(15, 0)
409 #define MT_MIB_SDR32_TX_PKT_EBF_CNT GENMASK(15, 0)
412 #define MT_MIB_SDR33(_band) MT_WF_MIB(_band, 0x088)
413 #define MT_MIB_SDR33_TX_PKT_IBF_CNT GENMASK(15, 0)
416 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
426 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
429 #define MT_MIB_BA_MISS_COUNT_MASK GENMASK(15, 0)
432 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x518 + (n))
433 #define MT_MIB_MB_BFTF(_band, n) MT_WF_MIB(_band, 0x510 + (n))
441 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
443 #define MT_MIB_BFCR0(_band) MT_WF_MIB(_band, 0x7b0)
444 #define MT_MIB_BFCR0_RX_FB_HT GENMASK(15, 0)
447 #define MT_MIB_BFCR1(_band) MT_WF_MIB(_band, 0x7b4)
448 #define MT_MIB_BFCR1_RX_FB_HE GENMASK(15, 0)
450 #define MT_MIB_BFCR2(_band) MT_WF_MIB(_band, 0x7b8)
451 #define MT_MIB_BFCR2_BFEE_TX_FB_TRIG GENMASK(15, 0)
453 #define MT_MIB_BFCR7(_band) MT_WF_MIB(_band, 0x7cc)
454 #define MT_MIB_BFCR7_BFEE_TX_FB_CPL GENMASK(15, 0)
457 #define MT_WTBLON_TOP_BASE 0x820d4000
460 #define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
463 #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(9, 0)
468 #define MT_WTBL_BASE 0x820d8000
475 /* AGG: band 0(0x820e2000), band 1(0x820f2000) */
476 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
483 #define MT_AGG_PCR0_MM_PROT BIT(0)
493 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
496 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
511 /* ARB: band 0(0x820e3000), band 1(0x820f3000) */
512 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
522 /* RMAC: band 0(0x820e5000), band 1(0x820f5000) */
523 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
526 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
527 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
549 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
556 #define MT_WF_RMAC_RSVD0(_band) MT_WF_RMAC(_band, 0x02e0)
559 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
561 #define MT_WF_RMAC_MIB_OBSS_BACKOFF GENMASK(15, 0)
564 #define MT_WF_RMAC_MIB_AIRTIME1(_band) MT_WF_RMAC(_band, 0x0384)
567 #define MT_WF_RMAC_MIB_AIRTIME3(_band) MT_WF_RMAC(_band, 0x038c)
568 #define MT_WF_RMAC_MIB_QOS01_BACKOFF GENMASK(31, 0)
570 #define MT_WF_RMAC_MIB_AIRTIME4(_band) MT_WF_RMAC(_band, 0x0390)
571 #define MT_WF_RMAC_MIB_QOS23_BACKOFF GENMASK(31, 0)
577 #define MT_WFDMA0_RST MT_WFDMA0(0x100)
581 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
582 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
586 #define MT_WFDMA0_MCU_HOST_INT_ENA MT_WFDMA0(0x1f4)
588 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
589 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
595 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
597 #define MT_WFDMA0_EXT0_CFG MT_WFDMA0(0x2b0)
600 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
601 #define MT_WFDMA0_PRI_DLY_INT_CFG1 MT_WFDMA0(0x2f4)
602 #define MT_WFDMA0_PRI_DLY_INT_CFG2 MT_WFDMA0(0x2f8)
603 #define MT_WPDMA_GLO_CFG MT_WFDMA0(0x208)
606 #define MT_WFDMA1_BASE 0xd5000
609 #define MT_WFDMA1_RST MT_WFDMA1(0x100)
613 #define MT_WFDMA1_BUSY_ENA MT_WFDMA1(0x13c)
614 #define MT_WFDMA1_BUSY_ENA_TX_FIFO0 BIT(0)
618 #define MT_WFDMA1_GLO_CFG MT_WFDMA1(0x208)
619 #define MT_WFDMA1_GLO_CFG_TX_DMA_EN BIT(0)
625 #define MT_WFDMA1_RST_DTX_PTR MT_WFDMA1(0x20c)
626 #define MT_WFDMA1_PRI_DLY_INT_CFG0 MT_WFDMA1(0x2f0)
630 #define MT_WFDMA_EXT_CSR_PHYS_BASE 0x18027000
634 #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR_PHYS(0x30)
635 #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0)
638 #define MT_WFDMA_WED_RING_CONTROL MT_WFDMA_EXT_CSR_PHYS(0x34)
639 #define MT_WFDMA_WED_RING_CONTROL_TX0 GENMASK(4, 0)
643 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR_PHYS(0x44)
644 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
646 #define MT_PCIE_RECOG_ID 0xd7090
647 #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0)
650 #define MT_INT_WED_SOURCE_CSR MT_WFDMA_EXT_CSR(0x200)
651 #define MT_INT_WED_MASK_CSR MT_WFDMA_EXT_CSR(0x204)
653 #define MT_WED_TX_RING_BASE MT_WFDMA_EXT_CSR(0x300)
654 #define MT_WED_RX_RING_BASE MT_WFDMA_EXT_CSR(0x400)
660 #define MT_WFDMA0_PCIE1_BUSY_ENA MT_WFDMA0_PCIE1(0x13c)
661 #define MT_WFDMA0_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
666 #define MT_WFDMA1_PCIE1_BASE 0xd9000
669 #define MT_WFDMA1_PCIE1_BUSY_ENA MT_WFDMA1_PCIE1(0x13c)
670 #define MT_WFDMA1_PCIE1_BUSY_ENA_TX_FIFO0 BIT(0)
679 #define MT_Q_BASE(q) ((dev->wfdma_mask >> (q)) & 0x1 ? \
686 #define MT_MCUQ_RING_BASE(q) (MT_Q_BASE(q) + 0x300)
687 #define MT_TXQ_RING_BASE(q) (MT_Q_BASE(__TXQ(q)) + 0x300)
688 #define MT_RXQ_RING_BASE(q) (MT_Q_BASE(__RXQ(q)) + 0x500)
690 #define MT_MCUQ_EXT_CTRL(q) (MT_Q_BASE(q) + 0x600 + \
691 MT_MCUQ_ID(q)* 0x4)
692 #define MT_RXQ_BAND1_CTRL(q) (MT_Q_BASE(__RXQ(q)) + 0x680 + \
693 MT_RXQ_ID(q)* 0x4)
694 #define MT_TXQ_EXT_CTRL(q) (MT_Q_BASE(__TXQ(q)) + 0x600 + \
695 MT_TXQ_ID(q)* 0x4)
709 #define MT_INT_RX_DONE_WM BIT(0)
767 #define MT_TOP_RGU_BASE 0x18000000
768 #define MT_TOP_PWR_CTRL (MT_TOP_RGU_BASE + (0x0))
769 #define MT_TOP_PWR_KEY (0x5746 << 16)
770 #define MT_TOP_PWR_SW_RST BIT(0)
775 #define MT_TOP_RGU_SYSRAM_PDN (MT_TOP_RGU_BASE + 0x050)
776 #define MT_TOP_RGU_SYSRAM_SLP (MT_TOP_RGU_BASE + 0x054)
777 #define MT_TOP_WFSYS_PWR (MT_TOP_RGU_BASE + 0x010)
782 #define MT7986_TOP_WM_RESET (MT_TOP_RGU_BASE + 0x120)
783 #define MT7986_TOP_WM_RESET_MASK BIT(0)
786 #define MT_HIF_REMAP_L1 0xf11ac
787 #define MT_HIF_REMAP_L1_MT7916 0xfe260
788 #define MT_HIF_REMAP_L1_MASK GENMASK(15, 0)
789 #define MT_HIF_REMAP_L1_OFFSET GENMASK(15, 0)
791 #define MT_HIF_REMAP_BASE_L1 0xe0000
793 #define MT_HIF_REMAP_L2 0xf11b0
794 #define MT_HIF_REMAP_L2_MASK GENMASK(19, 0)
795 #define MT_HIF_REMAP_L2_OFFSET GENMASK(11, 0)
797 #define MT_HIF_REMAP_L2_MT7916 0x1b8
799 #define MT_HIF_REMAP_L2_OFFSET_MT7916 GENMASK(15, 0)
801 #define MT_HIF_REMAP_BASE_L2_MT7916 0x40000
803 #define MT_INFRA_BASE 0x18000000
804 #define MT_WFSYS0_PHY_START 0x18400000
805 #define MT_WFSYS1_PHY_START 0x18800000
806 #define MT_WFSYS1_PHY_END 0x18bfffff
807 #define MT_CBTOP1_PHY_START 0x70000000
809 #define MT_CBTOP2_PHY_START 0xf0000000
810 #define MT_INFRA_MCU_START 0x7c000000
815 #define MT_CONN_INFRA_BASE 0x18001000
818 #define MT_CONN_INFRA_EFUSE MT_CONN_INFRA(0x020)
820 #define MT_CONN_INFRA_ADIE_RESET MT_CONN_INFRA(0x030)
821 #define MT_CONN_INFRA_ADIE1_RESET_MASK BIT(0)
824 #define MT_CONN_INFRA_OSC_RC_EN MT_CONN_INFRA(0x380)
826 #define MT_CONN_INFRA_OSC_CTRL MT_CONN_INFRA(0x300)
828 #define MT_CONN_INFRA_OSC_STB_TIME_MASK GENMASK(23, 0)
830 #define MT_CONN_INFRA_HW_CTRL MT_CONN_INFRA(0x200)
831 #define MT_CONN_INFRA_HW_CTRL_MASK BIT(0)
833 #define MT_CONN_INFRA_WF_SLP_PROT MT_CONN_INFRA(0x540)
834 #define MT_CONN_INFRA_WF_SLP_PROT_MASK BIT(0)
836 #define MT_CONN_INFRA_WF_SLP_PROT_RDY MT_CONN_INFRA(0x544)
840 #define MT_CONN_INFRA_EMI_REQ MT_CONN_INFRA(0x414)
841 #define MT_CONN_INFRA_EMI_REQ_MASK BIT(0)
845 #define MT_AFE_CTRL_BASE(_band) (0x18003000 + ((_band) << 19))
848 #define MT_AFE_DIG_EN_01(_band) MT_AFE_CTRL(_band, 0x00)
849 #define MT_AFE_DIG_EN_02(_band) MT_AFE_CTRL(_band, 0x04)
850 #define MT_AFE_DIG_EN_03(_band) MT_AFE_CTRL(_band, 0x08)
851 #define MT_AFE_DIG_TOP_01(_band) MT_AFE_CTRL(_band, 0x0c)
853 #define MT_AFE_PLL_STB_TIME(_band) MT_AFE_CTRL(_band, 0xf4)
854 #define MT_AFE_PLL_STB_TIME_MASK (GENMASK(30, 16) | GENMASK(14, 0))
855 #define MT_AFE_PLL_STB_TIME_VAL (FIELD_PREP(GENMASK(30, 16), 0x4bc) | \
856 FIELD_PREP(GENMASK(14, 0), 0x7e4))
858 #define MT_AFE_WPLL_CFG_MASK GENMASK(1, 0)
865 #define MT_AFE_PLL_CFG_VAL (FIELD_PREP(MT_AFE_BPLL_CFG_MASK, 0x1) | \
866 FIELD_PREP(MT_AFE_WPLL_CFG_MASK, 0x2) | \
867 FIELD_PREP(MT_AFE_MCU_WPLL_CFG_MASK, 0x1) | \
868 FIELD_PREP(MT_AFE_MCU_BPLL_CFG_MASK, 0x2))
871 #define MT_AFE_DIG_TOP_01_VAL FIELD_PREP(MT_AFE_DIG_TOP_01_MASK, 0x9)
873 #define MT_AFE_RG_WBG_EN_RCK_MASK BIT(0)
885 #define MT_ADIE_SLP_CTRL_BASE(_band) (0x18005000 + ((_band) << 19))
888 #define MT_ADIE_SLP_CTRL_CK0(_band) MT_ADIE_SLP_CTRL(_band, 0x120)
891 #define MT_ADIE_CHIP_ID 0x02c
892 #define MT_ADIE_VERSION_MASK GENMASK(15, 0)
894 #define MT_ADIE_IDX0 GENMASK(15, 0)
897 #define MT_ADIE_RG_TOP_THADC_BG 0x034
901 #define MT_ADIE_RG_TOP_THADC 0x038
903 #define MT_ADIE_PGA_GAIN_EFUSE_MASK GENMASK(2, 0)
907 #define MT_AFE_RG_ENCAL_WBTAC_IF_SW 0x070
908 #define MT_ADIE_EFUSE_RDATA0 0x130
910 #define MT_ADIE_EFUSE2_CTRL 0x148
913 #define MT_ADIE_EFUSE_CFG 0x144
919 #define MT_ADIE_THADC_ANALOG 0x3a6
921 #define MT_ADIE_THADC_SLOP 0x3a7
924 #define MT_ADIE_7975_XTAL_CAL 0x3a1
925 #define MT_ADIE_TRIM_MASK GENMASK(6, 0)
926 #define MT_ADIE_EFUSE_TRIM_MASK GENMASK(5, 0)
930 #define MT_ADIE_7975_XO_TRIM2 0x3a2
931 #define MT_ADIE_7975_XO_TRIM3 0x3a3
932 #define MT_ADIE_7975_XO_TRIM4 0x3a4
933 #define MT_ADIE_7975_XTAL_EN 0x3a5
935 #define MT_ADIE_XO_TRIM_FLOW 0x3ac
936 #define MT_ADIE_XTAL_AXM_80M_OSC 0x390
937 #define MT_ADIE_XTAL_AXM_40M_OSC 0x391
938 #define MT_ADIE_XTAL_TRIM1_80M_OSC 0x398
939 #define MT_ADIE_XTAL_TRIM1_40M_OSC 0x399
940 #define MT_ADIE_WRI_CK_SEL 0x4ac
941 #define MT_ADIE_RG_STRAP_PIN_IN 0x4fc
942 #define MT_ADIE_XTAL_C1 0x654
943 #define MT_ADIE_XTAL_C2 0x658
944 #define MT_ADIE_RG_XO_01 0x65c
945 #define MT_ADIE_RG_XO_03 0x664
947 #define MT_ADIE_CLK_EN 0xa00
949 #define MT_ADIE_7975_XTAL 0xa18
952 #define MT_ADIE_7975_COCLK 0xa1c
953 #define MT_ADIE_7975_XO_2 0xa84
956 #define MT_ADIE_7975_XO_CTRL2 0xa94
962 #define MT_ADIE_7975_XO_CTRL6 0xaa4
966 #define MT_TOP_SPI_ADIE_BASE(_band) (0x18004000 + ((_band) << 19))
969 #define MT_TOP_SPI_BUSY_CR(_band) MT_TOP_SPI_ADIE(_band, 0)
972 #define MT_TOP_SPI_ADDR_CR(_band) MT_TOP_SPI_ADIE(_band, 0x50)
976 #define MT_TOP_SPI_WRITE_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x54)
977 #define MT_TOP_SPI_READ_DATA_CR(_band) MT_TOP_SPI_ADIE(_band, 0x58)
980 #define MT_INFRA_CKGEN_BASE 0x18009000
983 #define MT_INFRA_CKGEN_BUS MT_INFRA_CKGEN(0xa00)
987 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_1 MT_INFRA_CKGEN(0x008)
988 #define MT_INFRA_CKGEN_BUS_WPLL_DIV_2 MT_INFRA_CKGEN(0x00c)
990 #define MT_INFRA_CKGEN_RFSPI_WPLL_DIV MT_INFRA_CKGEN(0x040)
992 #define MT_INFRA_CKGEN_DIV_EN_MASK BIT(0)
995 #define MT_INFRA_BUS_BASE 0x1800e000
998 #define MT_INFRA_BUS_OFF_TIMEOUT MT_INFRA_BUS(0x300)
1000 #define MT_INFRA_BUS_TIMEOUT_EN_MASK GENMASK(3, 0)
1002 #define MT_INFRA_BUS_ON_TIMEOUT MT_INFRA_BUS(0x31c)
1003 #define MT_INFRA_BUS_EMI_START MT_INFRA_BUS(0x360)
1004 #define MT_INFRA_BUS_EMI_END MT_INFRA_BUS(0x364)
1007 #define MT_CONNINFRA_SKU_DEC_ADDR 0x18050000
1008 #define MT_CONNINFRA_SKU_MASK GENMASK(15, 0)
1032 #define MT_SWDEF_MODE MT_SWDEF(0x3c)
1033 #define MT_SWDEF_NORMAL_MODE 0
1037 #define MT_SWDEF_SER_STATS MT_SWDEF(0x040)
1038 #define MT_SWDEF_PLE_STATS MT_SWDEF(0x044)
1039 #define MT_SWDEF_PLE1_STATS MT_SWDEF(0x048)
1040 #define MT_SWDEF_PLE_AMSDU_STATS MT_SWDEF(0x04C)
1041 #define MT_SWDEF_PSE_STATS MT_SWDEF(0x050)
1042 #define MT_SWDEF_PSE1_STATS MT_SWDEF(0x054)
1043 #define MT_SWDEF_LAMC_WISR6_BN0_STATS MT_SWDEF(0x058)
1044 #define MT_SWDEF_LAMC_WISR6_BN1_STATS MT_SWDEF(0x05C)
1045 #define MT_SWDEF_LAMC_WISR7_BN0_STATS MT_SWDEF(0x060)
1046 #define MT_SWDEF_LAMC_WISR7_BN1_STATS MT_SWDEF(0x064)
1048 #define MT_DIC_CMD_REG_BASE 0x41f000
1050 #define MT_DIC_CMD_REG_CMD MT_DIC_CMD_REG(0x10)
1052 #define MT_CPU_UTIL_BASE 0x41f030
1054 #define MT_CPU_UTIL_BUSY_PCT MT_CPU_UTIL(0x00)
1055 #define MT_CPU_UTIL_PEAK_BUSY_PCT MT_CPU_UTIL(0x04)
1056 #define MT_CPU_UTIL_IDLE_CNT MT_CPU_UTIL(0x08)
1057 #define MT_CPU_UTIL_PEAK_IDLE_CNT MT_CPU_UTIL(0x0c)
1058 #define MT_CPU_UTIL_CTRL MT_CPU_UTIL(0x1c)
1061 #define MT_LED_TOP_BASE 0x18013000
1064 #define MT_LED_CTRL(_n) MT_LED_PHYS(0x00 + ((_n) * 4))
1070 #define MT_LED_TX_BLINK(_n) MT_LED_PHYS(0x10 + ((_n) * 4))
1071 #define MT_LED_TX_BLINK_ON_MASK GENMASK(7, 0)
1074 #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x20 + ((_n) * 8))
1075 #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x24 + ((_n) * 8))
1078 #define MT_LED_STATUS_DURATION GENMASK(15, 0)
1080 #define MT_LED_EN(_n) MT_LED_PHYS(0x40 + ((_n) * 4))
1082 #define MT_LED_GPIO_MUX0 0x70005050 /* GPIO 1 and GPIO 2 */
1083 #define MT_LED_GPIO_MUX1 0x70005054 /* GPIO 14 and 15 */
1084 #define MT_LED_GPIO_MUX2 0x70005058 /* GPIO 18 */
1085 #define MT_LED_GPIO_MUX3 0x7000505c /* GPIO 26 */
1088 #define MT_TOP_BASE 0x18060000
1091 #define MT_TOP_LPCR_HOST_BAND(_band) MT_TOP(0x10 + ((_band) * 0x10))
1092 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
1096 #define MT_TOP_LPCR_HOST_BAND_IRQ_STAT(_band) MT_TOP(0x14 + ((_band) * 0x10))
1097 #define MT_TOP_LPCR_HOST_BAND_STAT BIT(0)
1099 #define MT_TOP_MISC MT_TOP(0xf0)
1100 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
1102 #define MT_TOP_WFSYS_WAKEUP MT_TOP(0x1a4)
1103 #define MT_TOP_WFSYS_WAKEUP_MASK BIT(0)
1105 #define MT_TOP_MCU_EMI_BASE MT_TOP(0x1c4)
1106 #define MT_TOP_MCU_EMI_BASE_MASK GENMASK(19, 0)
1108 #define MT_TOP_WF_AP_PERI_BASE MT_TOP(0x1c8)
1109 #define MT_TOP_WF_AP_PERI_BASE_MASK GENMASK(19, 0)
1111 #define MT_TOP_EFUSE_BASE MT_TOP(0x1cc)
1112 #define MT_TOP_EFUSE_BASE_MASK GENMASK(19, 0)
1114 #define MT_TOP_CONN_INFRA_WAKEUP MT_TOP(0x1a0)
1115 #define MT_TOP_CONN_INFRA_WAKEUP_MASK BIT(0)
1117 #define MT_TOP_WFSYS_RESET_STATUS MT_TOP(0x2cc)
1121 #define MT_SEMA_BASE 0x18070000
1124 #define MT_SEMA_RFSPI_STATUS (MT_SEMA(0x2000) + (11 * 4))
1125 #define MT_SEMA_RFSPI_RELEASE (MT_SEMA(0x2200) + (11 * 4))
1129 #define MT_MCU_BUS_BASE 0x18400000
1132 #define MT_MCU_BUS_TIMEOUT MT_MCU_BUS(0xf0440)
1133 #define MT_MCU_BUS_TIMEOUT_SET_MASK GENMASK(7, 0)
1137 #define MT_MCU_BUS_REMAP MT_MCU_BUS(0x120)
1140 #define MT_TOP_CFG_BASE 0x184b0000
1143 #define MT_TOP_CFG_IP_VERSION_ADDR MT_TOP_CFG(0x010)
1146 #define MT_TOP_CFG_ON_BASE 0x184c1000
1149 #define MT_TOP_CFG_ON_ROM_IDX MT_TOP_CFG_ON(0x604)
1152 #define MT_SLP_BASE 0x184c3000
1155 #define MT_SLP_STATUS MT_SLP(0x00c)
1157 #define MT_SLP_CTRL_EN_MASK BIT(0)
1161 #define MT_MCU_BUS_DBG_BASE 0x18500000
1164 #define MT_MCU_BUS_DBG_TIMEOUT MT_MCU_BUS_DBG(0x0)
1169 #define MT_HW_BOUND 0x70010020
1170 #define MT_HW_REV 0x70010204
1171 #define MT_WF_SUBSYS_RST 0x70002600
1174 #define MT_PCIE_MAC_BASE 0x74030000
1176 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
1178 #define MT_PCIE1_MAC_INT_ENABLE 0x74020188
1179 #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188
1181 #define MT_WM_MCU_PC 0x7c060204
1182 #define MT_WA_MCU_PC 0x7c06020c
1185 #define MT_WF_PP_TOP_BASE 0x820cc000
1188 #define MT_WF_PP_TOP_RXQ_WFDMA_CF_5 MT_WF_PP_TOP(0x0e8)
1191 #define MT_WF_IRPI_BASE 0x83000000
1194 #define MT_WF_IRPI_NSS(phy, nss) MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))
1195 #define MT_WF_IRPI_NSS_MT7916(phy, nss) MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))
1198 #define MT_WF_PHY_BASE 0x83080000
1201 #define MT_WF_PHY_RX_CTRL1(_phy) MT_WF_PHY(0x2004 + ((_phy) << 16))
1202 #define MT_WF_PHY_RX_CTRL1_MT7916(_phy) MT_WF_PHY(0x2004 + ((_phy) << 20))
1203 #define MT_WF_PHY_RX_CTRL1_IPI_EN GENMASK(2, 0)
1206 #define MT_WF_PHY_RXTD12(_phy) MT_WF_PHY(0x8230 + ((_phy) << 16))
1207 #define MT_WF_PHY_RXTD12_MT7916(_phy) MT_WF_PHY(0x8230 + ((_phy) << 20))
1211 #define MT_WF_PHY_TPC_CTRL_STAT(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 16))
1212 #define MT_WF_PHY_TPC_CTRL_STAT_MT7916(_phy) MT_WF_PHY(0xe7a0 + ((_phy) << 20))
1215 #define MT_MCU_WM_CIRQ_BASE 0x89010000
1217 #define MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x80)
1218 #define MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR MT_MCU_WM_CIRQ(0xc0)
1219 #define MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR MT_MCU_WM_CIRQ(0x108)
1220 #define MT_MCU_WM_CIRQ_EINT_SOFT_ADDR MT_MCU_WM_CIRQ(0x118)