Lines Matching +full:8 +full:dev
24 struct mt7915_dev *dev = data;
29 dev->ibf = !!val;
31 return mt7915_mcu_set_txbf(dev, MT_BF_TYPE_UPDATE);
37 struct mt7915_dev *dev = data;
39 *val = dev->ibf;
53 struct mt7915_dev *dev = phy->dev;
83 * 8: trigger firmware crash.
86 ret = mt7915_mcu_set_ser(dev, 0, 0, band);
94 ret = mt7915_mcu_set_ser(dev, SER_ENABLE, BIT(val), band);
98 ret = mt7915_mcu_set_ser(dev, SER_RECOVER, val, band);
103 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK);
104 ret = mt7915_mcu_set_ser(dev, 1, 3, band);
108 dev->recovery.state |= MT_MCU_CMD_WDT_MASK;
109 mt7915_reset(dev);
114 mt76_wr(dev, MT_MCU_WM_CIRQ_EINT_MASK_CLR_ADDR, BIT(18));
115 mt76_wr(dev, MT_MCU_WM_CIRQ_EINT_SOFT_ADDR, BIT(18));
129 struct mt7915_dev *dev = phy->dev;
159 "8: trigger firmware crash\n");
166 mt76_rr(dev, MT_SWDEF_SER_STATS));
169 mt76_rr(dev, MT_SWDEF_PLE_STATS));
172 mt76_rr(dev, MT_SWDEF_PLE1_STATS));
175 mt76_rr(dev, MT_SWDEF_PLE_AMSDU_STATS));
178 mt76_rr(dev, MT_SWDEF_PSE_STATS));
181 mt76_rr(dev, MT_SWDEF_PSE1_STATS));
184 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN0_STATS));
187 mt76_rr(dev, MT_SWDEF_LAMC_WISR6_BN1_STATS));
190 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN0_STATS));
193 mt76_rr(dev, MT_SWDEF_LAMC_WISR7_BN1_STATS));
196 dev->recovery.wm_reset_count,
197 dev->recovery.wa_reset_count);
217 struct mt7915_dev *dev = phy->dev;
223 if (val == RADAR_BACKGROUND && !dev->rdd2_phy) {
224 dev_err(dev->mt76.dev, "Background radar is not enabled\n");
230 dev_err(dev->mt76.dev, "No RDD found\n");
234 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_RADAR_EMULATE,
244 struct mt7915_dev *dev = data;
246 dev->muru_debug = val;
247 mt7915_mcu_muru_debug_set(dev, dev->muru_debug);
255 struct mt7915_dev *dev = data;
257 *val = dev->muru_debug;
268 struct mt7915_dev *dev = phy->dev;
275 "HE 2RU", "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU",
280 "HE 3RU", "HE 4RU", "HE 5-8RU", "HE 9-16RU", "HE >16RU"
285 if (!dev->muru_debug) {
290 mutex_lock(&dev->mt76.mutex);
300 seq_printf(file, "%8s | ", dl_non_he_type[i]);
303 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | ",
312 for (i = 5; i < 8; i++)
313 seq_printf(file, "%8s | ", dl_non_he_type[i]);
316 seq_printf(file, "%8u | %8u | %8u | ",
341 seq_printf(file, "%8s | ", dl_he_type[i]);
344 seq_printf(file, "%8u | %8u | ",
350 seq_printf(file, "%8s | ", dl_he_type[i]);
353 seq_printf(file, "%8u | %8u | %8u | ",
360 seq_printf(file, "%8s | ", dl_he_type[i]);
363 seq_printf(file, "%8u | %8u | %8u | %8u | %9u | %8u | ",
400 seq_printf(file, "%8s | ", ul_he_type[i]);
403 seq_printf(file, "%8u | %8u | %8u | ",
411 seq_printf(file, "%8s | ", ul_he_type[i]);
414 seq_printf(file, "%8u | %8u | %8u | %8u | %8u | %9u | %7u | ",
447 mutex_unlock(&dev->mt76.mutex);
456 struct mt7915_dev *dev = dev_get_drvdata(s->private);
457 struct cfg80211_chan_def *chandef = &dev->rdd2_chandef;
461 mutex_lock(&dev->mt76.mutex);
463 if (!mt7915_eeprom_has_background_radar(dev)) {
473 if (!dev->rdd2_phy) {
500 mutex_unlock(&dev->mt76.mutex);
508 struct mt7915_dev *dev = data;
519 dev->fw.debug_wm = val ? MCU_FW_LOG_TO_HOST : 0;
521 if (dev->fw.debug_bin)
524 val = dev->fw.debug_wm;
526 tx = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(1));
527 rx = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(2));
528 en = dev->fw.debug_wm || (dev->fw.debug_bin & BIT(0));
530 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, val);
540 ret = mt7915_mcu_fw_dbg_ctrl(dev, debug, val);
546 mt76_clear(dev, MT_CPU_UTIL_CTRL, BIT(0));
547 mt76_wr(dev, MT_DIC_CMD_REG_CMD, BIT(2) | BIT(13) |
548 (dev->fw.debug_wm ? 0 : BIT(0)));
549 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_MASK_CLR_ADDR, BIT(5));
550 mt76_wr(dev, MT_MCU_WM_CIRQ_IRQ_SOFT_ADDR, BIT(5));
554 dev->fw.debug_wm = 0;
562 struct mt7915_dev *dev = data;
564 *val = dev->fw.debug_wm;
575 struct mt7915_dev *dev = data;
578 dev->fw.debug_wa = val ? MCU_FW_LOG_TO_HOST : 0;
580 ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, dev->fw.debug_wa);
584 ret = mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET),
585 MCU_WA_PARAM_PDMA_RX, !!dev->fw.debug_wa, 0);
588 dev->fw.debug_wa = 0;
596 struct mt7915_dev *dev = data;
598 *val = dev->fw.debug_wa;
637 struct mt7915_dev *dev = data;
639 if (!dev->relay_fwlog)
640 dev->relay_fwlog = relay_open("fwlog_data", dev->debugfs_dir,
642 if (!dev->relay_fwlog)
645 dev->fw.debug_bin = val;
647 relay_reset(dev->relay_fwlog);
649 return mt7915_fw_debug_wm_set(dev, dev->fw.debug_wm);
655 struct mt7915_dev *dev = data;
657 *val = dev->fw.debug_bin;
668 struct mt7915_dev *dev = file->private;
670 seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WM_MCU_PC));
672 if (dev->fw.debug_wm) {
674 mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT),
675 mt76_rr(dev, MT_CPU_UTIL_PEAK_BUSY_PCT));
677 mt76_rr(dev, MT_CPU_UTIL_IDLE_CNT),
678 mt76_rr(dev, MT_CPU_UTIL_PEAK_IDLE_CNT));
689 struct mt7915_dev *dev = file->private;
691 seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WA_MCU_PC));
693 if (dev->fw.debug_wa)
694 return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
706 struct mt7915_dev *dev = phy->dev;
707 bool ext_phy = phy != &dev->phy;
713 range[i] = mt76_rr(dev, MT_MIB_ARNG(band, i));
720 seq_printf(file, "Length: %8d | ", bound[0]);
727 seq_printf(file, "%8d | ", phy->mt76->aggr_stats[i]);
784 struct mt7915_dev *dev = phy->dev;
788 mutex_lock(&dev->mt76.mutex);
797 seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %8d ",
806 mutex_unlock(&dev->mt76.mutex);
818 struct mt7915_dev *dev = phy->dev;
821 val = mt76_rr(dev, MT_FL_Q_EMPTY);
829 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl);
831 head = mt76_get_field(dev, MT_FL_Q2_CTRL,
833 tail = mt76_get_field(dev, MT_FL_Q2_CTRL,
835 queued = mt76_get_field(dev, MT_FL_Q3_CTRL,
848 struct mt7915_dev *dev = msta->vif->phy->dev;
858 val = mt76_rr(dev, MT_PLE_AC_QEMPTY(ac, idx));
863 mt76_wr(dev, MT_FL_Q0_CTRL, ctrl | msta->wcid.idx);
864 qlen = mt76_get_field(dev, MT_FL_Q3_CTRL,
876 struct mt7915_dev *dev = phy->dev;
882 { "ALTX_Q0", 8, 2, MT_LMAC_ALTX0 },
896 { "HIF_Q0", 8, 0, MT_HIF0 },
911 val = mt76_rr(dev, MT_PLE_FREEPG_CNT);
912 head = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(11, 0));
913 tail = mt76_get_field(dev, MT_PLE_FREEPG_HEAD_TAIL, GENMASK(27, 16));
919 val = mt76_rr(dev, MT_PLE_PG_HIF_GROUP);
920 head = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(11, 0));
921 tail = mt76_get_field(dev, MT_PLE_HIF_PG_INFO, GENMASK(27, 16));
946 struct mt7915_dev *dev = phy->dev;
952 { dev->mt76.q_mcu[MT_MCUQ_WM], " MCUWM" },
953 { dev->mt76.q_mcu[MT_MCUQ_WA], " MCUWA" },
954 { dev->mt76.q_mcu[MT_MCUQ_FWDL], "MCUFWDL" },
998 struct mt7915_dev *dev = phy->dev;
1018 phy != &dev->phy, phy->mt76->chandef.chan->hw_value);
1057 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_TPC_CTRL_STAT(band) :
1061 mt76_get_field(dev, reg, MT_WF_PHY_TPC_POWER));
1076 struct mt7915_dev *dev = phy->dev;
1099 dev_warn(dev->mt76.dev,
1119 mutex_lock(&dev->mt76.mutex);
1150 ret = mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(TX_POWER_FEATURE_CTRL),
1158 mutex_unlock(&dev->mt76.mutex);
1174 struct mt7915_dev *dev = dev_get_drvdata(s->private);
1181 list_for_each_entry_rcu(iter, &dev->twt_list, list)
1183 "%9d | %8d | %5c%c%c%c | %8d | %8d | %8d | %14lld |\n",
1203 struct mt7915_dev *dev = data;
1207 ret = mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, ®val, false);
1219 struct mt7915_dev *dev = data;
1222 return mt7915_mcu_rf_regval(dev, dev->mt76.debugfs_reg, &val32, true);
1230 struct mt7915_dev *dev = phy->dev;
1231 bool ext_phy = phy != &dev->phy;
1237 debugfs_create_file("muru_debug", 0600, dir, dev, &fops_muru_debug);
1247 debugfs_create_file("fw_debug_wm", 0600, dir, dev, &fops_fw_debug_wm);
1248 debugfs_create_file("fw_debug_wa", 0600, dir, dev, &fops_fw_debug_wa);
1249 debugfs_create_file("fw_debug_bin", 0600, dir, dev, &fops_fw_debug_bin);
1250 debugfs_create_file("fw_util_wm", 0400, dir, dev,
1252 debugfs_create_file("fw_util_wa", 0400, dir, dev,
1254 debugfs_create_file("implicit_txbf", 0600, dir, dev,
1258 debugfs_create_devm_seqfile(dev->mt76.dev, "twt_stats", dir,
1260 debugfs_create_file("rf_regval", 0600, dir, dev, &fops_rf_regval);
1262 if (!dev->dbdc_support || phy->mt76->band_idx) {
1264 &dev->hw_pattern);
1267 debugfs_create_devm_seqfile(dev->mt76.dev, "rdd_monitor", dir,
1272 dev->debugfs_dir = dir;
1278 mt7915_debugfs_write_fwlog(struct mt7915_dev *dev, const void *hdr, int hdrlen,
1286 dest = relay_reserve(dev->relay_fwlog, hdrlen + len + 4);
1297 relay_flush(dev->relay_fwlog);
1302 void mt7915_debugfs_rx_fw_monitor(struct mt7915_dev *dev, const void *data, int len)
1314 if (!dev->relay_fwlog)
1317 hdr.timestamp = cpu_to_le32(mt76_rr(dev, MT_LPON_FRCR(0)));
1319 mt7915_debugfs_write_fwlog(dev, &hdr, sizeof(hdr), data, len);
1322 bool mt7915_debugfs_rx_log(struct mt7915_dev *dev, const void *data, int len)
1327 if (dev->relay_fwlog)
1328 mt7915_debugfs_write_fwlog(dev, NULL, 0, data, len);
1342 struct mt7915_dev *dev = msta->vif->phy->dev;
1361 /* mode - cck: 0, ofdm: 1, ht: 2, gf: 3, vht: 4, he_su: 8, he_er: 9
1372 &phy.ldpc, &phy.stbc, &he_ltf) != 8) {
1373 dev_warn(dev->mt76.dev,
1388 ret = mt7915_mcu_set_fixed_rate_ctrl(dev, vif, sta, &phy, field);