Lines Matching refs:GENMASK
24 #define MT_RXD0_LENGTH GENMASK(15, 0)
25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
32 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
37 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(11, 0)
43 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
48 #define MT_RXD1_NORMAL_BAND_IDX GENMASK(28, 27)
54 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
55 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
57 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 13)
58 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(20, 16)
72 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
73 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
74 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
86 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
87 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
94 #define MT_RXD8_FRAME_CONTROL GENMASK(15, 0)
96 #define MT_RXD10_SEQ_CTRL GENMASK(15, 0)
97 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
99 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
102 #define MT_PRXV_TX_RATE GENMASK(6, 0)
105 #define MT_PRXV_NSTS GENMASK(10, 7)
108 #define MT_PRXV_HE_RU_ALLOC GENMASK(30, 22)
109 #define MT_PRXV_RCPI3 GENMASK(31, 24)
110 #define MT_PRXV_RCPI2 GENMASK(23, 16)
111 #define MT_PRXV_RCPI1 GENMASK(15, 8)
112 #define MT_PRXV_RCPI0 GENMASK(7, 0)
113 #define MT_PRXV_HT_SHORT_GI GENMASK(4, 3)
114 #define MT_PRXV_HT_STBC GENMASK(10, 9)
115 #define MT_PRXV_TX_MODE GENMASK(14, 11)
116 #define MT_PRXV_FRAME_MODE GENMASK(2, 0)
120 #define MT_CRXV_HE_NUM_USER GENMASK(26, 20)
121 #define MT_CRXV_HE_LTF_SIZE GENMASK(28, 27)
127 #define MT_CRXV_HE_MU_AID GENMASK(27, 17)
131 #define MT_CRXV_HE_BSS_COLOR GENMASK(15, 10)
132 #define MT_CRXV_HE_TXOP_DUR GENMASK(19, 17)
134 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
135 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
136 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
137 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
139 #define MT_CRXV_HE_RU0 GENMASK(8, 0)
140 #define MT_CRXV_HE_RU1 GENMASK(17, 9)
141 #define MT_CRXV_HE_RU2 GENMASK(26, 18)
142 #define MT_CRXV_HE_RU3_L GENMASK(31, 27)
143 #define MT_CRXV_HE_RU3_H GENMASK(3, 0)
145 #define MT_CRXV_EHT_NUM_USER GENMASK(26, 20)
146 #define MT_CRXV_EHT_LTF_SIZE GENMASK(28, 27)
150 #define MT_CRXV_EHT_MU_AID GENMASK(27, 17)
153 #define MT_CRXV_EHT_BSS_COLOR GENMASK(15, 10)
154 #define MT_CRXV_EHT_TXOP_DUR GENMASK(23, 17)
155 #define MT_CRXV_EHT_SR_MASK GENMASK(11, 8)
156 #define MT_CRXV_EHT_SR1_MASK GENMASK(15, 12)
157 #define MT_CRXV_EHT_SR2_MASK GENMASK(19, 16)
158 #define MT_CRXV_EHT_SR3_MASK GENMASK(23, 20)
159 #define MT_CRXV_EHT_RU0 GENMASK(8, 0)
160 #define MT_CRXV_EHT_RU1 GENMASK(17, 9)
161 #define MT_CRXV_EHT_RU2 GENMASK(26, 18)
162 #define MT_CRXV_EHT_RU3_L GENMASK(31, 27)
163 #define MT_CRXV_EHT_RU3_H GENMASK(3, 0)
164 #define MT_CRXV_EHT_SIG_MCS GENMASK(19, 18)
165 #define MT_CRXV_EHT_LTF_SYM GENMASK(22, 20)
216 #define MT_TXD0_Q_IDX GENMASK(31, 25)
217 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
218 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
219 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
222 #define MT_TXD1_OWN_MAC GENMASK(30, 25)
223 #define MT_TXD1_TID GENMASK(24, 21)
226 #define MT_TXD1_HDR_INFO GENMASK(20, 16)
227 #define MT_TXD1_HDR_FORMAT GENMASK(15, 14)
228 #define MT_TXD1_TGID GENMASK(13, 12)
229 #define MT_TXD1_WLAN_IDX GENMASK(11, 0)
231 #define MT_TXD2_POWER_OFFSET GENMASK(31, 26)
232 #define MT_TXD2_MAX_TX_TIME GENMASK(25, 16)
233 #define MT_TXD2_FRAG GENMASK(15, 14)
236 #define MT_TXD2_HDR_PAD GENMASK(11, 10)
239 #define MT_TXD2_BF_TYPE GENMASK(6, 7)
240 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
241 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
247 #define MT_TXD3_SEQ GENMASK(27, 16)
248 #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
249 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
257 #define MT_TXD4_PN_LOW GENMASK(31, 0)
259 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
267 #define MT_TXD5_PID GENMASK(7, 0)
269 #define MT_TXD6_TX_SRC GENMASK(31, 30)
272 #define MT_TXD6_BW GENMASK(24, 22)
273 #define MT_TXD6_TX_RATE GENMASK(21, 16)
275 #define MT_TXD6_TIMESTAMP_OFS_IDX GENMASK(14, 10)
276 #define MT_TXD6_TID_ADDBA GENMASK(10, 8)
277 #define MT_TXD6_MSDU_CNT GENMASK(9, 4)
278 #define MT_TXD6_MSDU_CNT_V2 GENMASK(15, 10)
283 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
288 #define MT_TXD7_CTXD_CNT GENMASK(25, 22)
290 #define MT_TXD7_TX_TIME GENMASK(9, 0)
292 #define MT_TXD9_WLAN_IDX GENMASK(23, 8)
294 #define MT_TXP_BUF_LEN GENMASK(11, 0)
295 #define MT_TXP_DMA_ADDR_H GENMASK(15, 12)
298 #define MT_TX_RATE_NSS GENMASK(13, 10)
299 #define MT_TX_RATE_MODE GENMASK(9, 6)
303 #define MT_TX_RATE_IDX GENMASK(5, 0)
305 #define MT_TXFREE0_PKT_TYPE GENMASK(31, 27)
306 #define MT_TXFREE0_MSDU_CNT GENMASK(25, 16)
307 #define MT_TXFREE0_RX_BYTE GENMASK(15, 0)
309 #define MT_TXFREE1_VER GENMASK(19, 16)
313 #define MT_TXFREE_INFO_WLAN_ID GENMASK(23, 12)
314 #define MT_TXFREE_INFO_MSDU_ID GENMASK(14, 0)
315 #define MT_TXFREE_INFO_COUNT GENMASK(27, 24)
316 #define MT_TXFREE_INFO_STAT GENMASK(29, 28)
321 #define MT_TXS0_BW GENMASK(31, 29)
322 #define MT_TXS0_TID GENMASK(28, 26)
324 #define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
333 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
337 #define MT_TXS0_TX_RATE GENMASK(13, 0)
339 #define MT_TXS1_SEQNO GENMASK(31, 20)
340 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
341 #define MT_TXS1_RXV_SEQNO GENMASK(15, 8)
342 #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
344 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
345 #define MT_TXS2_BAND GENMASK(29, 28)
346 #define MT_TXS2_WCID GENMASK(27, 16)
347 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
349 #define MT_TXS3_PID GENMASK(31, 24)
352 #define MT_TXS3_SRC GENMASK(5, 4)
354 #define MT_TXS3_LAST_TX_RATE GENMASK(2, 0)
356 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
361 #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
362 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
363 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
364 #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
366 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
367 #define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)
368 #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)
369 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
370 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
371 #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
373 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
374 #define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)
375 #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)
376 #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
377 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
378 #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)
381 #define MT_TXS5_MPDU_TX_CNT GENMASK(30, 20)
383 #define MT_TXS5_MPDU_TX_BYTE GENMASK(14, 0)
385 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(30, 20)
387 #define MT_TXS6_MPDU_FAIL_BYTE GENMASK(14, 0)
389 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(30, 20)
391 #define MT_TXS7_MPDU_RETRY_BYTE GENMASK(14, 0)