Lines Matching full:31
26 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
32 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
51 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
69 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
83 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
97 #define MT_RXD10_QOS_CTL GENMASK(31, 16)
99 #define MT_RXD11_HT_CONTROL GENMASK(31, 0)
109 #define MT_PRXV_RCPI3 GENMASK(31, 24)
142 #define MT_CRXV_HE_RU3_L GENMASK(31, 27)
162 #define MT_CRXV_EHT_RU3_L GENMASK(31, 27)
216 #define MT_TXD0_Q_IDX GENMASK(31, 25)
221 #define MT_TXD1_FIXED_RATE BIT(31)
231 #define MT_TXD2_POWER_OFFSET GENMASK(31, 26)
243 #define MT_TXD3_SN_VALID BIT(31)
257 #define MT_TXD4_PN_LOW GENMASK(31, 0)
259 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
269 #define MT_TXD6_TX_SRC GENMASK(31, 30)
282 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
304 #define MT_TXFREE0_PKT_TYPE GENMASK(31, 27)
310 #define MT_TXFREE_INFO_PAIR BIT(31)
320 #define MT_TXS0_BW GENMASK(31, 29)
338 #define MT_TXS1_SEQNO GENMASK(31, 20)
343 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
348 #define MT_TXS3_PID GENMASK(31, 24)
355 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
358 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
362 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
365 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
369 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
372 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
376 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)