Lines Matching refs:GENMASK
40 #define MT_TX_FREE_MSDU_CNT GENMASK(9, 0)
41 #define MT_TX_FREE_WLAN_ID GENMASK(23, 14)
42 #define MT_TX_FREE_COUNT GENMASK(12, 0)
44 #define MT_TX_FREE_STATUS GENMASK(14, 13)
45 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
48 #define MT_TX_FREE_RATE GENMASK(13, 0)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
51 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
52 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
53 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
57 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
59 #define MT_TXD1_TID GENMASK(22, 20)
60 #define MT_TXD1_HDR_PAD GENMASK(19, 18)
61 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
62 #define MT_TXD1_HDR_INFO GENMASK(15, 11)
65 #define MT_TXD1_WLAN_IDX GENMASK(9, 0)
69 #define MT_TXD2_POWER_OFFSET GENMASK(29, 24)
70 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
71 #define MT_TXD2_FRAG GENMASK(15, 14)
80 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
81 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
87 #define MT_TXD3_SEQ GENMASK(27, 16)
88 #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
89 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
97 #define MT_TXD4_PN_LOW GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
105 #define MT_TXD5_PID GENMASK(7, 0)
109 #define MT_TXD6_TX_RATE GENMASK(29, 16)
110 #define MT_TXD6_SGI GENMASK(15, 14)
111 #define MT_TXD6_HELTF GENMASK(13, 12)
114 #define MT_TXD6_ANT_ID GENMASK(7, 4)
117 #define MT_TXD6_BW GENMASK(1, 0)
119 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
122 #define MT_TXD7_TYPE GENMASK(21, 20)
123 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
125 #define MT_TXD7_PSE_FID GENMASK(27, 16)
126 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
128 #define MT_TXD7_TX_TIME GENMASK(9, 0)
130 #define MT_TXD8_L_TYPE GENMASK(5, 4)
131 #define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)
134 #define MT_TX_RATE_NSS GENMASK(12, 10)
135 #define MT_TX_RATE_MODE GENMASK(9, 6)
139 #define MT_TX_RATE_IDX GENMASK(5, 0)
142 #define MT_TXS0_BW GENMASK(30, 29)
143 #define MT_TXS0_TID GENMASK(28, 26)
145 #define MT_TXS0_TXS_FORMAT GENMASK(24, 23)
154 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
158 #define MT_TXS0_TX_RATE GENMASK(13, 0)
160 #define MT_TXS1_SEQNO GENMASK(31, 20)
161 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
162 #define MT_TXS1_RXV_SEQNO GENMASK(15, 8)
163 #define MT_TXS1_TX_POWER_DBM GENMASK(7, 0)
165 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
166 #define MT_TXS2_LAST_TX_RATE GENMASK(29, 27)
168 #define MT_TXS2_WCID GENMASK(25, 16)
169 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
171 #define MT_TXS3_PID GENMASK(31, 24)
172 #define MT_TXS3_ANT_ID GENMASK(23, 0)
174 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
177 #define MT_TXS5_MPDU_TX_BYTE GENMASK(22, 0)
178 #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23)
180 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23)
181 #define MT_TXS7_MPDU_RETRY_BYTE GENMASK(22, 0)
182 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23)
185 #define MT_RXD0_LENGTH GENMASK(15, 0)
186 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
187 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
189 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
194 #define MT_RXD1_NORMAL_WLAN_IDX GENMASK(9, 0)
200 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
201 #define MT_RXD1_NORMAL_KEY_ID GENMASK(22, 21)
213 #define MT_RXD2_NORMAL_BSSID GENMASK(5, 0)
216 #define MT_RXD2_NORMAL_MAC_HDR_LEN GENMASK(12, 8)
218 #define MT_RXD2_NORMAL_HDR_OFFSET GENMASK(15, 14)
219 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
233 #define MT_RXD4_NORMAL_PAYLOAD_FORMAT GENMASK(1, 0)
234 #define MT_RXD4_FIRST_AMSDU_FRAME GENMASK(1, 0)
239 #define MT_RXD4_NORMAL_OFLD GENMASK(12, 11)
241 #define MT_RXD4_NORMAL_WOL GENMASK(18, 14)
242 #define MT_RXD4_NORMAL_CLS_BITMAP GENMASK(28, 19)
244 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
249 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
250 #define MT_RXD3_NORMAL_CH_FREQ GENMASK(15, 8)
251 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
269 #define MT_RXD6_FRAME_CONTROL GENMASK(15, 0)
270 #define MT_RXD6_TA_LO GENMASK(31, 16)
272 #define MT_RXD7_TA_HI GENMASK(31, 0)
274 #define MT_RXD8_SEQ_CTRL GENMASK(15, 0)
275 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
277 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
280 #define MT_PRXV_TX_RATE GENMASK(6, 0)
283 #define MT_PRXV_NSTS GENMASK(9, 7)
286 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
288 #define MT_PRXV_FRAME_MODE GENMASK(14, 12)
289 #define MT_PRXV_HT_SGI GENMASK(16, 15)
290 #define MT_PRXV_HT_STBC GENMASK(23, 22)
291 #define MT_PRXV_TX_MODE GENMASK(27, 24)
296 #define MT_PRXV_RCPI3 GENMASK(31, 24)
297 #define MT_PRXV_RCPI2 GENMASK(23, 16)
298 #define MT_PRXV_RCPI1 GENMASK(15, 8)
299 #define MT_PRXV_RCPI0 GENMASK(7, 0)
300 #define MT_PRXV_HE_RU_ALLOC_H GENMASK(3, 0)
303 #define MT_CRXV_HT_STBC GENMASK(1, 0)
304 #define MT_CRXV_TX_MODE GENMASK(7, 4)
305 #define MT_CRXV_FRAME_MODE GENMASK(10, 8)
306 #define MT_CRXV_HT_SHORT_GI GENMASK(14, 13)
307 #define MT_CRXV_HE_LTF_SIZE GENMASK(18, 17)
310 #define MT_CRXV_HE_NUM_USER GENMASK(30, 24)
313 #define MT_CRXV_HE_RU0 GENMASK(7, 0)
314 #define MT_CRXV_HE_RU1 GENMASK(15, 8)
315 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
316 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
318 #define MT_CRXV_HE_MU_AID GENMASK(30, 20)
320 #define MT_CRXV_HE_SR_MASK GENMASK(11, 8)
321 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
322 #define MT_CRXV_HE_SR2_MASK GENMASK(20, 17)
323 #define MT_CRXV_HE_SR3_MASK GENMASK(24, 21)
325 #define MT_CRXV_HE_BSS_COLOR GENMASK(5, 0)
326 #define MT_CRXV_HE_TXOP_DUR GENMASK(12, 6)
330 #define MT_CRXV_SNR GENMASK(18, 13)
331 #define MT_CRXV_FOE_LO GENMASK(31, 19)
332 #define MT_CRXV_FOE_HI GENMASK(6, 0)