Lines Matching full:31
46 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD0_Q_IDX GENMASK(31, 25)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
67 #define MT_TXD2_FIX_RATE BIT(31)
83 #define MT_TXD3_SN_VALID BIT(31)
97 #define MT_TXD4_PN_LOW GENMASK(31, 0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
107 #define MT_TXD6_TX_IBF BIT(31)
119 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
141 #define MT_TXS0_FIXED_RATE BIT(31)
160 #define MT_TXS1_SEQNO GENMASK(31, 20)
165 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
171 #define MT_TXS3_PID GENMASK(31, 24)
174 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
178 #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23)
180 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23)
182 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23)
187 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
210 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
230 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
244 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
266 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
270 #define MT_RXD6_TA_LO GENMASK(31, 16)
272 #define MT_RXD7_TA_HI GENMASK(31, 0)
275 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
277 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
286 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
296 #define MT_PRXV_RCPI3 GENMASK(31, 24)
311 #define MT_CRXV_HE_UPLINK BIT(31)
316 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
331 #define MT_CRXV_FOE_LO GENMASK(31, 19)