Lines Matching +full:0 +full:x30000
15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
25 [MT_TMAC_BASE] = 0x21000,
26 [MT_RMAC_BASE] = 0x21200,
27 [MT_DMA_BASE] = 0x21800,
28 [MT_PF_BASE] = 0x22000,
29 [MT_WTBL_BASE_ON] = 0x23000,
30 [MT_WTBL_BASE_OFF] = 0x23400,
31 [MT_LPON_BASE] = 0x24200,
32 [MT_MIB_BASE] = 0x24800,
33 [MT_WTBL_BASE_ADDR] = 0x30000,
34 [MT_PCIE_REMAP_BASE2] = 0x80000,
35 [MT_TOP_MISC_BASE] = 0xc0000,
36 [MT_EFUSE_ADDR_BASE] = 0x81070000,
40 [MT_TOP_CFG_BASE] = 0x01000,
41 [MT_HW_BASE] = 0x02000,
42 [MT_DMA_SHDL_BASE] = 0x06000,
43 [MT_PCIE_REMAP_2] = 0x0700c,
44 [MT_ARB_BASE] = 0x20c00,
45 [MT_HIF_BASE] = 0x04000,
46 [MT_CSR_BASE] = 0x07000,
47 [MT_PLE_BASE] = 0x08000,
48 [MT_PSE_BASE] = 0x0c000,
49 [MT_PP_BASE] = 0x0e000,
50 [MT_CFG_BASE] = 0x20000,
51 [MT_AGG_BASE] = 0x22000,
52 [MT_TMAC_BASE] = 0x24000,
53 [MT_RMAC_BASE] = 0x25000,
54 [MT_DMA_BASE] = 0x27000,
55 [MT_PF_BASE] = 0x28000,
56 [MT_WTBL_BASE_ON] = 0x29000,
57 [MT_WTBL_BASE_OFF] = 0x29800,
58 [MT_LPON_BASE] = 0x2b000,
59 [MT_MIB_BASE] = 0x2d000,
60 [MT_WTBL_BASE_ADDR] = 0x30000,
61 [MT_PCIE_REMAP_BASE2] = 0x90000,
62 [MT_TOP_MISC_BASE] = 0xc0000,
63 [MT_EFUSE_ADDR_BASE] = 0x78011000,
76 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7615_irq_handler()
89 u32 intr, mask = 0, tx_mcu_mask = mt7615_tx_mcu_int_mask(dev); in mt7615_irq_tasklet()
92 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7615_irq_tasklet()
103 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); in mt7615_irq_tasklet()
108 if (intr & MT_INT_RX_DONE(0)) in mt7615_irq_tasklet()
109 napi_schedule(&dev->mt76.napi[0]); in mt7615_irq_tasklet()
136 if (addr < 0x100000) in __mt7615_reg_addr()
208 (mt76_rr(dev, MT_HW_REV) & 0xff); in mt7615_mmio_probe()
224 mt76_wr(dev, MT_INT_MASK_CSR, 0); in mt7615_mmio_probe()
238 return 0; in mt7615_mmio_probe()