Lines Matching +full:max +full:- +full:adj
1 // SPDX-License-Identifier: ISC
42 memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats)); in mt7603_mac_reset_counters()
51 int offset = 3 * dev->coverage_class; in mt7603_mac_set_timing()
54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ; in mt7603_mac_set_timing()
73 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); in mt7603_mac_set_timing()
75 if (dev->slottime < 20 || is_5ghz) in mt7603_mac_set_timing()
229 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx); in mt7603_wtbl_set_smps()
231 if (sta->smps == enabled) in mt7603_wtbl_set_smps()
235 sta->smps = enabled; in mt7603_wtbl_set_smps()
241 int idx = sta->wcid.idx; in mt7603_wtbl_set_ps()
244 spin_lock_bh(&dev->ps_lock); in mt7603_wtbl_set_ps()
246 if (sta->ps == enabled) in mt7603_wtbl_set_ps()
259 mt7603_filter_tx(dev, sta->vif->idx, idx, false); in mt7603_wtbl_set_ps()
266 sta->ps = enabled; in mt7603_wtbl_set_ps()
269 spin_unlock_bh(&dev->ps_lock); in mt7603_wtbl_set_ps()
332 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; in mt7603_wtbl_update_cap()
333 int idx = msta->wcid.idx; in mt7603_wtbl_update_cap()
340 ampdu_density = sta->deflink.ht_cap.ampdu_density; in mt7603_wtbl_update_cap()
347 sta->deflink.ht_cap.ampdu_factor) | in mt7603_wtbl_update_cap()
349 sta->deflink.ht_cap.ampdu_density) | in mt7603_wtbl_update_cap()
352 if (sta->deflink.ht_cap.cap) in mt7603_wtbl_update_cap()
354 if (sta->deflink.vht_cap.cap) in mt7603_wtbl_update_cap()
363 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) in mt7603_wtbl_update_cap()
365 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) in mt7603_wtbl_update_cap()
395 for (i = 7; i > 0; i--) { in mt7603_mac_tx_ba_reset()
426 spin_lock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_sta_poll()
427 if (list_empty(&dev->mt76.sta_poll_list)) { in mt7603_mac_sta_poll()
428 spin_unlock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_sta_poll()
432 msta = list_first_entry(&dev->mt76.sta_poll_list, in mt7603_mac_sta_poll()
434 list_del_init(&msta->wcid.poll_list); in mt7603_mac_sta_poll()
435 spin_unlock_bh(&dev->mt76.sta_poll_lock); in mt7603_mac_sta_poll()
437 addr = mt7603_wtbl4_addr(msta->wcid.idx); in mt7603_mac_sta_poll()
439 u32 airtime_last = msta->tx_airtime_ac[i]; in mt7603_mac_sta_poll()
441 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8); in mt7603_mac_sta_poll()
442 airtime[i] = msta->tx_airtime_ac[i] - airtime_last; in mt7603_mac_sta_poll()
446 if (msta->tx_airtime_ac[i] & BIT(22)) in mt7603_mac_sta_poll()
451 mt7603_wtbl_update(dev, msta->wcid.idx, in mt7603_mac_sta_poll()
453 memset(msta->tx_airtime_ac, 0, in mt7603_mac_sta_poll()
454 sizeof(msta->tx_airtime_ac)); in mt7603_mac_sta_poll()
457 if (!msta->wcid.sta) in mt7603_mac_sta_poll()
462 struct mt76_queue *q = dev->mphy.q_tx[i]; in mt7603_mac_sta_poll()
463 u8 qidx = q->hw_idx; in mt7603_mac_sta_poll()
479 spin_lock_bh(&dev->mt76.cc_lock); in mt7603_mac_sta_poll()
480 dev->mphy.chan_state->cc_tx += total_airtime; in mt7603_mac_sta_poll()
481 spin_unlock_bh(&dev->mt76.cc_lock); in mt7603_mac_sta_poll()
494 if (!wcid->sta) in mt7603_rx_get_wcid()
498 if (!sta->vif) in mt7603_rx_get_wcid()
501 return &sta->vif->sta.wcid; in mt7603_rx_get_wcid()
507 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; in mt7603_mac_fill_rx()
510 __le32 *rxd = (__le32 *)skb->data; in mt7603_mac_fill_rx()
523 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband; in mt7603_mac_fill_rx()
527 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast); in mt7603_mac_fill_rx()
529 status->band = sband->band; in mt7603_mac_fill_rx()
530 if (i < sband->n_channels) in mt7603_mac_fill_rx()
531 status->freq = sband->channels[i].center_freq; in mt7603_mac_fill_rx()
534 status->flag |= RX_FLAG_FAILED_FCS_CRC; in mt7603_mac_fill_rx()
537 status->flag |= RX_FLAG_MMIC_ERROR; in mt7603_mac_fill_rx()
541 status->flag |= RX_FLAG_ONLY_MONITOR; in mt7603_mac_fill_rx()
545 status->flag |= RX_FLAG_DECRYPTED; in mt7603_mac_fill_rx()
546 status->flag |= RX_FLAG_IV_STRIPPED; in mt7603_mac_fill_rx()
547 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; in mt7603_mac_fill_rx()
553 return -EINVAL; in mt7603_mac_fill_rx()
555 if (!sband->channels) in mt7603_mac_fill_rx()
556 return -EINVAL; in mt7603_mac_fill_rx()
561 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
562 return -EINVAL; in mt7603_mac_fill_rx()
567 if (status->flag & RX_FLAG_DECRYPTED) { in mt7603_mac_fill_rx()
579 status->iv[0] = data[5]; in mt7603_mac_fill_rx()
580 status->iv[1] = data[4]; in mt7603_mac_fill_rx()
581 status->iv[2] = data[3]; in mt7603_mac_fill_rx()
582 status->iv[3] = data[2]; in mt7603_mac_fill_rx()
583 status->iv[4] = data[1]; in mt7603_mac_fill_rx()
584 status->iv[5] = data[0]; in mt7603_mac_fill_rx()
592 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
593 return -EINVAL; in mt7603_mac_fill_rx()
596 status->timestamp = le32_to_cpu(rxd[0]); in mt7603_mac_fill_rx()
597 status->flag |= RX_FLAG_MACTIME_START; in mt7603_mac_fill_rx()
601 status->flag |= RX_FLAG_AMPDU_DETAILS; in mt7603_mac_fill_rx()
603 /* all subframes of an A-MPDU have the same timestamp */ in mt7603_mac_fill_rx()
604 if (dev->rx_ampdu_ts != status->timestamp) { in mt7603_mac_fill_rx()
605 if (!++dev->ampdu_ref) in mt7603_mac_fill_rx()
606 dev->ampdu_ref++; in mt7603_mac_fill_rx()
608 dev->rx_ampdu_ts = status->timestamp; in mt7603_mac_fill_rx()
610 status->ampdu_ref = dev->ampdu_ref; in mt7603_mac_fill_rx()
614 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
615 return -EINVAL; in mt7603_mac_fill_rx()
628 i = mt76_get_rate(&dev->mt76, sband, i, cck); in mt7603_mac_fill_rx()
632 status->encoding = RX_ENC_HT; in mt7603_mac_fill_rx()
634 return -EINVAL; in mt7603_mac_fill_rx()
637 return -EINVAL; in mt7603_mac_fill_rx()
641 status->enc_flags |= RX_ENC_FLAG_SHORT_GI; in mt7603_mac_fill_rx()
643 status->enc_flags |= RX_ENC_FLAG_LDPC; in mt7603_mac_fill_rx()
645 status->enc_flags |= RX_ENC_FLAG_STBC_MASK * in mt7603_mac_fill_rx()
648 status->rate_idx = i; in mt7603_mac_fill_rx()
650 status->chains = dev->mphy.antenna_mask; in mt7603_mac_fill_rx()
651 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) + in mt7603_mac_fill_rx()
652 dev->rssi_offset[0]; in mt7603_mac_fill_rx()
653 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) + in mt7603_mac_fill_rx()
654 dev->rssi_offset[1]; in mt7603_mac_fill_rx()
657 status->bw = RATE_INFO_BW_40; in mt7603_mac_fill_rx()
660 if ((u8 *)rxd - skb->data >= skb->len) in mt7603_mac_fill_rx()
661 return -EINVAL; in mt7603_mac_fill_rx()
663 return -EINVAL; in mt7603_mac_fill_rx()
666 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad); in mt7603_mac_fill_rx()
674 hdr = (struct ieee80211_hdr *)skb->data; in mt7603_mac_fill_rx()
675 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control)) in mt7603_mac_fill_rx()
678 status->aggr = unicast && in mt7603_mac_fill_rx()
679 !ieee80211_is_qos_nullfunc(hdr->frame_control); in mt7603_mac_fill_rx()
680 status->qos_ctl = *ieee80211_get_qos_ctl(hdr); in mt7603_mac_fill_rx()
681 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); in mt7603_mac_fill_rx()
694 if (rate->flags & IEEE80211_TX_RC_MCS) { in mt7603_mac_tx_rate_val()
695 rate_idx = rate->idx; in mt7603_mac_tx_rate_val()
696 nss = 1 + (rate->idx >> 3); in mt7603_mac_tx_rate_val()
698 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) in mt7603_mac_tx_rate_val()
700 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) in mt7603_mac_tx_rate_val()
704 int band = dev->mphy.chandef.chan->band; in mt7603_mac_tx_rate_val()
708 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx]; in mt7603_mac_tx_rate_val()
709 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) in mt7603_mac_tx_rate_val()
710 val = r->hw_value_short; in mt7603_mac_tx_rate_val()
712 val = r->hw_value; in mt7603_mac_tx_rate_val()
732 int wcid = sta->wcid.idx; in mt7603_wtbl_set_rates()
735 int n_rates = sta->n_rates; in mt7603_wtbl_set_rates()
747 rates[i] = rates[n_rates - 1]; in mt7603_wtbl_set_rates()
749 rateset = !(sta->rate_set_tsf & BIT(0)); in mt7603_wtbl_set_rates()
750 memcpy(sta->rateset[rateset].rates, rates, in mt7603_wtbl_set_rates()
751 sizeof(sta->rateset[rateset].rates)); in mt7603_wtbl_set_rates()
753 sta->rateset[rateset].probe_rate = *probe_rate; in mt7603_wtbl_set_rates()
754 ref = &sta->rateset[rateset].probe_rate; in mt7603_wtbl_set_rates()
756 sta->rateset[rateset].probe_rate.idx = -1; in mt7603_wtbl_set_rates()
757 ref = &sta->rateset[rateset].rates[0]; in mt7603_wtbl_set_rates()
760 rates = sta->rateset[rateset].rates; in mt7603_wtbl_set_rates()
761 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) { in mt7603_wtbl_set_rates()
769 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI) in mt7603_wtbl_set_rates()
782 rates[i].idx--; in mt7603_wtbl_set_rates()
822 bw_idx ? bw_idx - 1 : 7); in mt7603_wtbl_set_rates()
843 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset; in mt7603_wtbl_set_rates()
850 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET)) in mt7603_wtbl_set_rates()
853 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates; in mt7603_wtbl_set_rates()
854 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET; in mt7603_wtbl_set_rates()
864 if (key->keylen > 32) in mt7603_mac_get_key_info()
867 memcpy(key_data, key->key, key->keylen); in mt7603_mac_get_key_info()
869 switch (key->cipher) { in mt7603_mac_get_key_info()
876 memcpy(key_data + 16, key->key + 24, 8); in mt7603_mac_get_key_info()
877 memcpy(key_data + 24, key->key + 16, 8); in mt7603_mac_get_key_info()
896 return -EOPNOTSUPP; in mt7603_wtbl_set_key()
899 addr += key->keyidx * 16; in mt7603_wtbl_set_key()
908 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx); in mt7603_wtbl_set_key()
921 struct ieee80211_tx_rate *rate = &info->control.rates[0]; in mt7603_mac_write_txwi()
922 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; in mt7603_mac_write_txwi()
923 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data; in mt7603_mac_write_txwi()
924 struct ieee80211_vif *vif = info->control.vif; in mt7603_mac_write_txwi()
925 struct mt76_queue *q = dev->mphy.q_tx[qid]; in mt7603_mac_write_txwi()
931 u16 fc = le16_to_cpu(hdr->frame_control); in mt7603_mac_write_txwi()
938 mvif = (struct mt7603_vif *)vif->drv_priv; in mt7603_mac_write_txwi()
939 vif_idx = mvif->idx; in mt7603_mac_write_txwi()
945 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv; in mt7603_mac_write_txwi()
947 tx_count = msta->rate_count; in mt7603_mac_write_txwi()
951 wlan_idx = wcid->idx; in mt7603_mac_write_txwi()
958 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | in mt7603_mac_write_txwi()
959 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx); in mt7603_mac_write_txwi()
965 skb->priority & IEEE80211_QOS_CTL_TID_MASK) | in mt7603_mac_write_txwi()
972 if (info->flags & IEEE80211_TX_CTL_NO_ACK) in mt7603_mac_write_txwi()
978 is_multicast_ether_addr(hdr->addr1)); in mt7603_mac_write_txwi()
981 if (!(info->flags & IEEE80211_TX_CTL_AMPDU)) in mt7603_mac_write_txwi()
992 if (rate->idx >= 0 && rate->count && in mt7603_mac_write_txwi()
993 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) { in mt7603_mac_write_txwi()
994 bool stbc = info->flags & IEEE80211_TX_CTL_STBC; in mt7603_mac_write_txwi()
1004 if (rate->flags & IEEE80211_TX_RC_SHORT_GI) in mt7603_mac_write_txwi()
1007 if (!(rate->flags & IEEE80211_TX_RC_MCS)) in mt7603_mac_write_txwi()
1010 tx_count = rate->count; in mt7603_mac_write_txwi()
1020 if (ieee80211_is_data_qos(hdr->frame_control)) in mt7603_mac_write_txwi()
1021 seqno = le16_to_cpu(hdr->seq_ctrl); in mt7603_mac_write_txwi()
1022 else if (ieee80211_is_back_req(hdr->frame_control)) in mt7603_mac_write_txwi()
1023 seqno = le16_to_cpu(bar->start_seq_num); in mt7603_mac_write_txwi()
1032 u64 pn = atomic64_inc_return(&key->tx_pn); in mt7603_mac_write_txwi()
1051 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); in mt7603_tx_prepare_skb()
1052 struct ieee80211_key_conf *key = info->control.hw_key; in mt7603_tx_prepare_skb()
1056 wcid = &dev->global_sta.wcid; in mt7603_tx_prepare_skb()
1059 msta = (struct mt7603_sta *)sta->drv_priv; in mt7603_tx_prepare_skb()
1061 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER | in mt7603_tx_prepare_skb()
1063 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) in mt7603_tx_prepare_skb()
1066 mt76_tx_check_agg_ssn(sta, tx_info->skb); in mt7603_tx_prepare_skb()
1069 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); in mt7603_tx_prepare_skb()
1071 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) { in mt7603_tx_prepare_skb()
1072 spin_lock_bh(&dev->mt76.lock); in mt7603_tx_prepare_skb()
1073 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0], in mt7603_tx_prepare_skb()
1074 msta->rates); in mt7603_tx_prepare_skb()
1075 msta->rate_probe = true; in mt7603_tx_prepare_skb()
1076 spin_unlock_bh(&dev->mt76.lock); in mt7603_tx_prepare_skb()
1079 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid, in mt7603_tx_prepare_skb()
1106 fixed_rate = info->status.rates[0].count; in mt7603_fill_txs()
1107 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); in mt7603_fill_txs()
1125 info->flags |= IEEE80211_TX_STAT_ACK; in mt7603_fill_txs()
1127 info->status.ampdu_len = 1; in mt7603_fill_txs()
1128 info->status.ampdu_ack_len = !!(info->flags & in mt7603_fill_txs()
1131 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU)) in mt7603_fill_txs()
1132 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU; in mt7603_fill_txs()
1134 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY); in mt7603_fill_txs()
1137 info->status.rates[0].count = count; in mt7603_fill_txs()
1142 rate_set_tsf = READ_ONCE(sta->rate_set_tsf); in mt7603_fill_txs()
1143 rs_idx = !((u32)(le32_get_bits(txs_data[1], MT_TXS1_F0_TIMESTAMP) - in mt7603_fill_txs()
1146 rs = &sta->rateset[rs_idx]; in mt7603_fill_txs()
1148 if (!first_idx && rs->probe_rate.idx >= 0) { in mt7603_fill_txs()
1149 info->status.rates[0] = rs->probe_rate; in mt7603_fill_txs()
1151 spin_lock_bh(&dev->mt76.lock); in mt7603_fill_txs()
1152 if (sta->rate_probe) { in mt7603_fill_txs()
1154 sta->rates); in mt7603_fill_txs()
1155 sta->rate_probe = false; in mt7603_fill_txs()
1157 spin_unlock_bh(&dev->mt76.lock); in mt7603_fill_txs()
1159 info->status.rates[0] = rs->rates[first_idx / 2]; in mt7603_fill_txs()
1161 info->status.rates[0].count = 0; in mt7603_fill_txs()
1167 cur_rate = &rs->rates[idx / 2]; in mt7603_fill_txs()
1169 count -= cur_count; in mt7603_fill_txs()
1171 if (idx && (cur_rate->idx != info->status.rates[i].idx || in mt7603_fill_txs()
1172 cur_rate->flags != info->status.rates[i].flags)) { in mt7603_fill_txs()
1174 if (i == ARRAY_SIZE(info->status.rates)) { in mt7603_fill_txs()
1175 i--; in mt7603_fill_txs()
1179 info->status.rates[i] = *cur_rate; in mt7603_fill_txs()
1180 info->status.rates[i].count = 0; in mt7603_fill_txs()
1183 info->status.rates[i].count += cur_count; in mt7603_fill_txs()
1187 final_rate_flags = info->status.rates[i].flags; in mt7603_fill_txs()
1194 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ) in mt7603_fill_txs()
1195 sband = &dev->mphy.sband_5g.sband; in mt7603_fill_txs()
1197 sband = &dev->mphy.sband_2g.sband; in mt7603_fill_txs()
1199 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate, in mt7603_fill_txs()
1214 info->status.rates[i].idx = final_rate; in mt7603_fill_txs()
1215 info->status.rates[i].flags = final_rate_flags; in mt7603_fill_txs()
1224 struct mt76_dev *mdev = &dev->mt76; in mt7603_mac_add_txs_skb()
1231 trace_mac_txdone(mdev, sta->wcid.idx, pid); in mt7603_mac_add_txs_skb()
1234 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list); in mt7603_mac_add_txs_skb()
1239 info->status.rates[0].count = 0; in mt7603_mac_add_txs_skb()
1240 info->status.rates[0].idx = -1; in mt7603_mac_add_txs_skb()
1274 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); in mt7603_mac_add_txs()
1283 spin_lock_bh(&dev->mt76.rx_lock); in mt7603_mac_add_txs()
1285 spin_unlock_bh(&dev->mt76.rx_lock); in mt7603_mac_add_txs()
1295 struct sk_buff *skb = e->skb; in mt7603_tx_complete_skb()
1297 if (!e->txwi) { in mt7603_tx_complete_skb()
1302 dev->tx_hang_check = 0; in mt7603_tx_complete_skb()
1303 mt76_tx_complete_skb(mdev, e->wcid, skb); in mt7603_tx_complete_skb()
1318 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) in mt7603_pse_reset()
1327 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++; in mt7603_pse_reset()
1330 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; in mt7603_pse_reset()
1334 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3) in mt7603_pse_reset()
1335 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0; in mt7603_pse_reset()
1414 int beacon_int = dev->mt76.beacon_int; in mt7603_mac_watchdog_reset()
1415 u32 mask = dev->mt76.mmio.irqmask; in mt7603_mac_watchdog_reset()
1418 ieee80211_stop_queues(dev->mt76.hw); in mt7603_mac_watchdog_reset()
1419 set_bit(MT76_RESET, &dev->mphy.state); in mt7603_mac_watchdog_reset()
1422 mt76_txq_schedule_all(&dev->mphy); in mt7603_mac_watchdog_reset()
1424 mt76_worker_disable(&dev->mt76.tx_worker); in mt7603_mac_watchdog_reset()
1425 tasklet_disable(&dev->mt76.pre_tbtt_tasklet); in mt7603_mac_watchdog_reset()
1426 napi_disable(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1427 napi_disable(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1428 napi_disable(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1430 mutex_lock(&dev->mt76.mutex); in mt7603_mac_watchdog_reset()
1432 mt7603_beacon_set_timer(dev, -1, 0); in mt7603_mac_watchdog_reset()
1445 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true); in mt7603_mac_watchdog_reset()
1447 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true); in mt7603_mac_watchdog_reset()
1451 mt76_tx_status_check(&dev->mt76, true); in mt7603_mac_watchdog_reset()
1453 mt76_for_each_q_rx(&dev->mt76, i) { in mt7603_mac_watchdog_reset()
1457 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] || in mt7603_mac_watchdog_reset()
1458 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY) in mt7603_mac_watchdog_reset()
1461 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { in mt7603_mac_watchdog_reset()
1466 clear_bit(MT76_RESET, &dev->mphy.state); in mt7603_mac_watchdog_reset()
1469 mutex_unlock(&dev->mt76.mutex); in mt7603_mac_watchdog_reset()
1471 mt76_worker_enable(&dev->mt76.tx_worker); in mt7603_mac_watchdog_reset()
1473 tasklet_enable(&dev->mt76.pre_tbtt_tasklet); in mt7603_mac_watchdog_reset()
1474 mt7603_beacon_set_timer(dev, -1, beacon_int); in mt7603_mac_watchdog_reset()
1476 napi_enable(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1477 napi_enable(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1478 napi_enable(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1481 napi_schedule(&dev->mt76.tx_napi); in mt7603_mac_watchdog_reset()
1482 napi_schedule(&dev->mt76.napi[0]); in mt7603_mac_watchdog_reset()
1483 napi_schedule(&dev->mt76.napi[1]); in mt7603_mac_watchdog_reset()
1486 ieee80211_wake_queues(dev->mt76.hw); in mt7603_mac_watchdog_reset()
1487 mt76_txq_schedule_all(&dev->mphy); in mt7603_mac_watchdog_reset()
1536 q = dev->mphy.q_tx[i]; in mt7603_tx_hang()
1538 if (!q->queued) in mt7603_tx_hang()
1541 prev_dma_idx = dev->tx_dma_idx[i]; in mt7603_tx_hang()
1542 dma_idx = readl(&q->regs->dma_idx); in mt7603_tx_hang()
1543 dev->tx_dma_idx[i] = dma_idx; in mt7603_tx_hang()
1546 dma_idx != readl(&q->regs->cpu_idx)) in mt7603_tx_hang()
1587 if (dev->reset_test == cause + 1) { in mt7603_watchdog_check()
1588 dev->reset_test = 0; in mt7603_watchdog_check()
1604 dev->cur_reset_cause = cause; in mt7603_watchdog_check()
1605 dev->reset_cause[cause]++; in mt7603_watchdog_check()
1611 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76); in mt7603_update_channel()
1614 state = mphy->chan_state; in mt7603_update_channel()
1615 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA); in mt7603_update_channel()
1623 if (val == dev->ed_strict_mode) in mt7603_edcca_set_strict()
1626 dev->ed_strict_mode = val; in mt7603_edcca_set_strict()
1629 if (!dev->ed_monitor) in mt7603_edcca_set_strict()
1634 if (dev->ed_monitor && !dev->ed_strict_mode) in mt7603_edcca_set_strict()
1642 dev->ed_monitor && !dev->ed_strict_mode); in mt7603_edcca_set_strict()
1654 if (!dev->ed_monitor) in mt7603_edcca_check()
1659 rssi0 -= 256; in mt7603_edcca_check()
1661 if (dev->mphy.antenna_mask & BIT(1)) { in mt7603_edcca_check()
1664 rssi1 -= 256; in mt7603_edcca_check()
1669 if (max(rssi0, rssi1) >= -40 && in mt7603_edcca_check()
1670 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1671 dev->ed_strong_signal++; in mt7603_edcca_check()
1672 else if (dev->ed_strong_signal > 0) in mt7603_edcca_check()
1673 dev->ed_strong_signal--; in mt7603_edcca_check()
1678 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time)); in mt7603_edcca_check()
1679 dev->ed_time = cur_time; in mt7603_edcca_check()
1685 if (dev->ed_trigger < 0) in mt7603_edcca_check()
1686 dev->ed_trigger = 0; in mt7603_edcca_check()
1687 dev->ed_trigger++; in mt7603_edcca_check()
1689 if (dev->ed_trigger > 0) in mt7603_edcca_check()
1690 dev->ed_trigger = 0; in mt7603_edcca_check()
1691 dev->ed_trigger--; in mt7603_edcca_check()
1694 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH || in mt7603_edcca_check()
1695 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) { in mt7603_edcca_check()
1697 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) { in mt7603_edcca_check()
1701 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1702 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH; in mt7603_edcca_check()
1703 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) in mt7603_edcca_check()
1704 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH; in mt7603_edcca_check()
1717 u32 agc0 = dev->agc0, agc3 = dev->agc3; in mt7603_adjust_sensitivity()
1718 u32 adj; in mt7603_adjust_sensitivity() local
1720 if (!dev->sensitivity || dev->sensitivity < -100) { in mt7603_adjust_sensitivity()
1721 dev->sensitivity = 0; in mt7603_adjust_sensitivity()
1722 } else if (dev->sensitivity <= -84) { in mt7603_adjust_sensitivity()
1723 adj = 7 + (dev->sensitivity + 92) / 2; in mt7603_adjust_sensitivity()
1726 agc0 |= adj << 12; in mt7603_adjust_sensitivity()
1727 agc0 |= adj << 16; in mt7603_adjust_sensitivity()
1729 } else if (dev->sensitivity <= -72) { in mt7603_adjust_sensitivity()
1730 adj = 7 + (dev->sensitivity + 80) / 2; in mt7603_adjust_sensitivity()
1733 agc0 |= adj << 8; in mt7603_adjust_sensitivity()
1734 agc0 |= adj << 12; in mt7603_adjust_sensitivity()
1735 agc0 |= adj << 16; in mt7603_adjust_sensitivity()
1739 if (dev->sensitivity > -54) in mt7603_adjust_sensitivity()
1740 dev->sensitivity = -54; in mt7603_adjust_sensitivity()
1742 adj = 7 + (dev->sensitivity + 80) / 2; in mt7603_adjust_sensitivity()
1745 agc0 |= adj << 4; in mt7603_adjust_sensitivity()
1746 agc0 |= adj << 8; in mt7603_adjust_sensitivity()
1747 agc0 |= adj << 12; in mt7603_adjust_sensitivity()
1748 agc0 |= adj << 16; in mt7603_adjust_sensitivity()
1768 if (!dev->dynamic_sensitivity) in mt7603_false_cca_check()
1779 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm; in mt7603_false_cca_check()
1780 dev->false_cca_cck = pd_cck - mdrdy_cck; in mt7603_false_cca_check()
1784 min_signal = mt76_get_min_avg_rssi(&dev->mt76, 0); in mt7603_false_cca_check()
1786 dev->sensitivity = 0; in mt7603_false_cca_check()
1787 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1791 min_signal -= 15; in mt7603_false_cca_check()
1793 false_cca = dev->false_cca_ofdm + dev->false_cca_cck; in mt7603_false_cca_check()
1795 dev->sensitivity < -100 + dev->sensitivity_limit) { in mt7603_false_cca_check()
1796 if (!dev->sensitivity) in mt7603_false_cca_check()
1797 dev->sensitivity = -92; in mt7603_false_cca_check()
1799 dev->sensitivity += 2; in mt7603_false_cca_check()
1800 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1802 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) { in mt7603_false_cca_check()
1803 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1804 if (!dev->sensitivity) in mt7603_false_cca_check()
1807 dev->sensitivity -= 2; in mt7603_false_cca_check()
1810 if (dev->sensitivity && dev->sensitivity > min_signal) { in mt7603_false_cca_check()
1811 dev->sensitivity = min_signal; in mt7603_false_cca_check()
1812 dev->last_cca_adj = jiffies; in mt7603_false_cca_check()
1826 mt76_tx_status_check(&dev->mt76, false); in mt7603_mac_work()
1828 mutex_lock(&dev->mt76.mutex); in mt7603_mac_work()
1830 dev->mphy.mac_work_count++; in mt7603_mac_work()
1831 mt76_update_survey(&dev->mphy); in mt7603_mac_work()
1837 dev->mphy.aggr_stats[idx++] += val & 0xffff; in mt7603_mac_work()
1838 dev->mphy.aggr_stats[idx++] += val >> 16; in mt7603_mac_work()
1841 if (dev->mphy.mac_work_count == 10) in mt7603_mac_work()
1844 if (mt7603_watchdog_check(dev, &dev->rx_pse_check, in mt7603_mac_work()
1847 mt7603_watchdog_check(dev, &dev->beacon_check, in mt7603_mac_work()
1850 mt7603_watchdog_check(dev, &dev->tx_hang_check, in mt7603_mac_work()
1853 mt7603_watchdog_check(dev, &dev->tx_dma_check, in mt7603_mac_work()
1856 mt7603_watchdog_check(dev, &dev->rx_dma_check, in mt7603_mac_work()
1859 mt7603_watchdog_check(dev, &dev->mcu_hang, in mt7603_mac_work()
1862 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) { in mt7603_mac_work()
1863 dev->beacon_check = 0; in mt7603_mac_work()
1864 dev->tx_dma_check = 0; in mt7603_mac_work()
1865 dev->tx_hang_check = 0; in mt7603_mac_work()
1866 dev->rx_dma_check = 0; in mt7603_mac_work()
1867 dev->rx_pse_check = 0; in mt7603_mac_work()
1868 dev->mcu_hang = 0; in mt7603_mac_work()
1869 dev->rx_dma_idx = ~0; in mt7603_mac_work()
1870 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx)); in mt7603_mac_work()
1872 dev->mphy.mac_work_count = 0; in mt7603_mac_work()
1875 if (dev->mphy.mac_work_count >= 10) in mt7603_mac_work()
1876 dev->mphy.mac_work_count = 0; in mt7603_mac_work()
1878 mutex_unlock(&dev->mt76.mutex); in mt7603_mac_work()
1883 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, in mt7603_mac_work()