Lines Matching +full:data +full:- +full:ready

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 /* SPI register offsets. 4-byte aligned. */
50 #define IF_SPI_DATA_READBASE_REG 0x1C	/* Read data base reg */
51 #define IF_SPI_DATA_WRITEBASE_REG 0x20	/* Write data base reg */
52 #define IF_SPI_DATA_RDWRPORT_REG 0x24	/* Read/Write data port reg */
87 /* Host Interrupt Control bit : WLAN ready */
137 /* Host Interrupt Status bit : Tx download ready */
139 /* Host Interrupt Status bit : Rx upload ready */
141 /* Host Interrupt Status bit : Command download ready */
145 /* Host Interrupt Status bit : Command upload ready */
151 /* Host Interrupt Status bit : Data write FIFO overflow */
153 /* Host Interrupt Status bit : Data read FIFO underflow */
161 /* Host Interrupt Status Mask bit : Tx download ready */
163 /* Host Interrupt Status Mask bit : Rx upload ready */
165 /* Host Interrupt Status Mask bit : Command download ready */
169 /* Host Interrupt Status Mask bit : Command upload ready */
175 /* Host Interrupt Status Mask bit : Data write FIFO overflow */
177 /* Host Interrupt Status Mask bit : Data write FIFO underflow */
185 /* SCK edge on which the WLAN module outputs data on MISO */
190  * register name and getting back data from the WLAN module.