Lines Matching +full:umac +full:- +full:reset

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3  * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
81  * Device reset for family 8000
82  * write to bit 24 in order to reset the CPU
112  * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
114  * 0 -- EDCA BK (background) frames, lowest priority
115  * 1 -- EDCA BE (best effort) frames, normal priority
116  * 2 -- EDCA VI (video) frames, higher priority
117  * 3 -- EDCA VO (voice) and management frames, highest priority
118  * 4 -- unused
119  * 5 -- unused
120  * 6 -- unused
121  * 7 -- Commands
123  * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
125  * channels 0-3 to support 11n aggregation via EDCA DMA channels.
129  * 1)  Scheduler-Ack, in which the scheduler automatically supports a
130  *     block-ack (BA) window of up to 64 TFDs.  In this mode, each queue
133  *     Quality-Of-Service (QOS) priority, destined for a single station.
135  *     In scheduler-ack mode, the scheduler keeps track of the Tx status of
138  *     automatically processes block-acks received from the receiving STA,
139  *     and reschedules un-acked frames to be retransmitted (successful
140  *     Tx completion may end up being out-of-order).
146  * 2)  FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
174  * can keep track of at one time when creating block-ack chains of frames.
175  * Note that "64" matches the number of ack bits in a block-ack packet.
248  * Note this address is cleared after MAC reset.
288 /* UMAC Internal Tx Fifo */
436  * type: bits 0-11
437  * reserved: bits 12-18
439  * dash: bits 20-23
440  * step: bits 24-27
441  * flavor: bits 28-31