Lines Matching +full:0 +full:x00a10000
15 #define PRPH_BASE (0x00000)
16 #define PRPH_END (0xFFFFF)
19 #define APMG_BASE (PRPH_BASE + 0x3000)
20 #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
21 #define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
22 #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
23 #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
24 #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
25 #define APMG_RFKILL_REG (APMG_BASE + 0x0014)
26 #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
27 #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
28 #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
29 #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
31 #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
32 #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
33 #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
35 #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
36 #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
37 #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
38 #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
39 #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
40 #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
41 #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
43 #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
44 #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
45 #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000)
47 #define APMG_RTC_INT_STT_RFKILL (0x10000000)
50 #define DEVICE_SYSTEM_TIME_REG 0xA0206C
53 #define DEVICE_SET_NMI_REG 0x00a01c30
56 #define UREG_NIC_SET_NMI_DRIVER 0x00a05c10
60 /* Shared registers (0x0..0x3ff, via target indirect or periphery */
61 #define SHR_BASE 0x00a10000
64 #define SHR_APMG_GP1_REG 0x01dc
66 #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
67 #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
70 #define SHR_APMG_DL_CFG_REG 0x01c4
72 #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
73 #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
74 #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
77 #define SHR_APMG_XTAL_CFG_REG 0x1c0
78 #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
84 #define RELEASE_CPU_RESET (0x300C)
91 #define SHR_MISC_WFM_DTS_EN (0x00a10024)
92 #define DTSC_CFG_MODE (0x00a10604)
93 #define DTSC_VREF_AVG (0x00a10648)
94 #define DTSC_VREF5_AVG (0x00a1064c)
95 #define DTSC_CFG_MODE_PERIODIC (0x2)
96 #define DTSC_PTAT_AVG (0x00a10650)
114 * 0 -- EDCA BK (background) frames, lowest priority
123 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
125 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
170 #define SCD_MEM_LOWER_BOUND (0x0000)
180 #define SCD_TXFIFO_POS_TID (0)
182 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
185 #define SCD_QUEUE_STTS_REG_POS_TXF (0)
189 #define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
191 #define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00)
192 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000)
195 #define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F)
196 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000)
199 #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0)
203 #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
204 #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
207 #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
208 #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
211 #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
212 #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
221 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
223 #define SCD_BASE (PRPH_BASE + 0xa02c00)
225 #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
226 #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
227 #define SCD_AIT (SCD_BASE + 0x0c)
228 #define SCD_TXFACT (SCD_BASE + 0x10)
229 #define SCD_ACTIVE (SCD_BASE + 0x14)
230 #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
231 #define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
232 #define SCD_AGGR_SEL (SCD_BASE + 0x248)
233 #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
234 #define SCD_GP_CTRL (SCD_BASE + 0x1a8)
235 #define SCD_EN_CTRL (SCD_BASE + 0x254)
240 #define OSC_CLK (0xa04068)
241 #define OSC_CLK_FORCE_CONTROL (0x8)
243 #define FH_UCODE_LOAD_STATUS (0x1AF0)
250 #define UREG_UCODE_LOAD_STATUS (0xa05c40)
251 #define UREG_CPU_INIT_RUN (0xa05c44)
253 #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
254 #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
256 #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
257 #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
259 #define LMAC2_PRPH_OFFSET (0x100000)
262 #define RXF_SIZE_ADDR (0xa00c88)
263 #define RXF_RD_D_SPACE (0xa00c40)
264 #define RXF_RD_WR_PTR (0xa00c50)
265 #define RXF_RD_RD_PTR (0xa00c54)
266 #define RXF_RD_FENCE_PTR (0xa00c4c)
267 #define RXF_SET_FENCE_MODE (0xa00c14)
268 #define RXF_LD_WR2FENCE (0xa00c1c)
269 #define RXF_FIFO_RD_FENCE_INC (0xa00c68)
271 #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
272 #define RXF_DIFF_FROM_PREV (0x200)
273 #define RXF2C_DIFF_FROM_PREV (0x4e00)
275 #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
276 #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
279 #define TXF_FIFO_ITEM_CNT (0xa00438)
280 #define TXF_WR_PTR (0xa00414)
281 #define TXF_RD_PTR (0xa00410)
282 #define TXF_FENCE_PTR (0xa00418)
283 #define TXF_LOCK_FENCE (0xa00424)
284 #define TXF_LARC_NUM (0xa0043c)
285 #define TXF_READ_MODIFY_DATA (0xa00448)
286 #define TXF_READ_MODIFY_ADDR (0xa0044c)
289 #define TXF_CPU2_FIFO_ITEM_CNT (0xA00538)
290 #define TXF_CPU2_WR_PTR (0xA00514)
291 #define TXF_CPU2_RD_PTR (0xA00510)
292 #define TXF_CPU2_FENCE_PTR (0xA00518)
293 #define TXF_CPU2_LOCK_FENCE (0xA00524)
294 #define TXF_CPU2_NUM (0xA0053C)
295 #define TXF_CPU2_READ_MODIFY_DATA (0xA00548)
296 #define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C)
299 #define RSP_RADIO_CMD (0xa02804)
300 #define RSP_RADIO_RDDAT (0xa02814)
305 #define HPM_MAC_LTR_CSR 0xa0348c
306 #define HPM_MAC_LRT_ENABLE_ALL 0xf
308 #define HPM_UMAC_LTR 0xa03480
311 #define MON_BUFF_SAMPLE_CTL (0xa03c00)
312 #define MON_BUFF_BASE_ADDR (0xa03c1c)
313 #define MON_BUFF_END_ADDR (0xa03c40)
314 #define MON_BUFF_WRPTR (0xa03c44)
315 #define MON_BUFF_CYCLE_CNT (0xa03c48)
317 #define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c)
318 #define MON_BUFF_END_ADDR_VER2 (0xa03c20)
319 #define MON_BUFF_WRPTR_VER2 (0xa03c24)
320 #define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28)
321 #define MON_BUFF_SHIFT_VER2 (0x8)
323 #define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20)
324 #define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24)
325 #define DBGC_CUR_DBGBUF_STATUS (0xd03c1c)
326 #define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c)
327 #define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff)
328 #define DBGC_CUR_DBGBUF_STATUS_IDX_MSK (0x0f000000)
330 #define MON_DMARB_RD_CTL_ADDR (0xa03c60)
331 #define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
333 #define DBGC_IN_SAMPLE (0xa03c00)
334 #define DBGC_OUT_CTRL (0xa03c0c)
337 #define LDBG_M2S_BUF_WPTR (0xa0476c)
338 #define LDBG_M2S_BUF_WRAP_CNT (0xa04774)
339 #define LDBG_M2S_BUF_WPTR_VAL_MSK (0x000fffff)
340 #define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK (0x000fffff)
343 #define WFPM_PS_CTL_CLR 0xA0300C
344 #define WFMP_MAC_ADDR_0 0xA03080
345 #define WFMP_MAC_ADDR_1 0xA03084
346 #define LMPM_PMG_EN 0xA01CEC
347 #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078
348 #define RFIC_REG_RD 0xAD0470
349 #define WFPM_CTRL_REG 0xA03030
350 #define WFPM_OTP_CFG1_ADDR 0x00a03098
355 #define WFPM_OTP_CFG1_IS_JACKET(_val) (((_val) & 0x00000020) >> WFPM_OTP_BZ_BNJ_JACKET_BIT)
356 #define WFPM_OTP_CFG1_IS_CDB(_val) (((_val) & 0x00000010) >> WFPM_OTP_BZ_BNJ_CDB_BIT)
359 #define WFPM_GP2 0xA030B4
362 #define DBGI_SRAM_TARGET_ACCESS_RDATA_LSB 0x00A2E154
363 #define DBGI_SRAM_TARGET_ACCESS_RDATA_MSB 0x00A2E158
364 #define DBGI_SRAM_FIFO_POINTERS 0x00A2E148
365 #define DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK 0x00000FFF
368 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,
371 #define CNVI_AUX_MISC_CHIP 0xA200B0
372 #define CNVI_AUX_MISC_CHIP_MAC_STEP(_val) (((_val) & 0xf000000) >> 24)
373 #define CNVI_AUX_MISC_CHIP_PROD_TYPE(_val) ((_val) & 0xfff)
374 #define CNVI_AUX_MISC_CHIP_PROD_TYPE_GL 0x910
375 #define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U 0x930
376 #define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_I 0x900
377 #define CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_W 0x901
379 #define CNVR_AUX_MISC_CHIP 0xA2B800
380 #define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890
381 #define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938
382 #define CNVI_SCU_SEQ_DATA_DW9 0xA27488
384 #define CNVI_PMU_STEP_FLOW 0xA2D588
387 #define PREG_AUX_BUS_WPROT_0 0xA04CC0
390 #define PREG_PRPH_WPROT_9000 0xA04CE0
392 #define PREG_PRPH_WPROT_22000 0xA04D00
394 #define SB_MODIFY_CFG_FLAG 0xA03088
395 #define SB_CFG_RESIDES_IN_ROM 0x80
396 #define SB_CPU_1_STATUS 0xA01E30
397 #define SB_CPU_2_STATUS 0xA01E34
398 #define UMAG_SB_CPU_1_STATUS 0xA038C0
399 #define UMAG_SB_CPU_2_STATUS 0xA038C4
400 #define UMAG_GEN_HW_STATUS 0xA038C8
401 #define UREG_UMAC_CURRENT_PC 0xa05c18
402 #define UREG_LMAC1_CURRENT_PC 0xa05c1c
403 #define UREG_LMAC2_CURRENT_PC 0xa05c20
405 #define WFPM_LMAC1_PD_NOTIFICATION 0xa0338c
406 #define WFPM_ARC1_PD_NOTIFICATION 0xa03044
407 #define HPM_SECONDARY_DEVICE_STATE 0xa03404
408 #define WFPM_MAC_OTP_CFG7_ADDR 0xa03338
409 #define WFPM_MAC_OTP_CFG7_DATA 0xa0333c
418 #define LMPM_CHICK 0xA01FF8
420 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),
424 #define LMPM_PAGE_PASS_NOTIF 0xA03824
432 * type: bits 0-11
439 #define REG_CRF_ID_TYPE(val) (((val) & 0x00000FFF) >> 0)
440 #define REG_CRF_ID_SLAVE(val) (((val) & 0x00080000) >> 19)
441 #define REG_CRF_ID_DASH(val) (((val) & 0x00F00000) >> 20)
442 #define REG_CRF_ID_STEP(val) (((val) & 0x0F000000) >> 24)
443 #define REG_CRF_ID_FLAVOR(val) (((val) & 0xF0000000) >> 28)
445 #define UREG_CHICK (0xA05C00)
449 #define SD_REG_VER 0xa29600
450 #define SD_REG_VER_GEN2 0x00a2b800
452 #define REG_CRF_ID_TYPE_JF_1 0x201
453 #define REG_CRF_ID_TYPE_JF_2 0x202
454 #define REG_CRF_ID_TYPE_HR_CDB 0x503
455 #define REG_CRF_ID_TYPE_HR_NONE_CDB 0x504
456 #define REG_CRF_ID_TYPE_HR_NONE_CDB_1X1 0x501
457 #define REG_CRF_ID_TYPE_HR_NONE_CDB_CCP 0x532
458 #define REG_CRF_ID_TYPE_GF 0x410
459 #define REG_CRF_ID_TYPE_FM 0x910
460 #define REG_CRF_ID_TYPE_WHP 0xA10
462 #define HPM_DEBUG 0xA03440
466 #define HPM_HIPM_GEN_CFG 0xA03458
467 #define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0)
471 #define UREG_DOORBELL_TO_ISR6 0xA05C04
472 #define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0)
473 #define UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE (BIT(0) | BIT(1))
485 #define CNVI_MBOX_C 0xA3400C
487 #define FSEQ_ERROR_CODE 0xA340C8
488 #define FSEQ_TOP_INIT_VERSION 0xA34038
489 #define FSEQ_CNVIO_INIT_VERSION 0xA3403C
490 #define FSEQ_OTP_VERSION 0xA340FC
491 #define FSEQ_TOP_CONTENT_VERSION 0xA340F4
492 #define FSEQ_ALIVE_TOKEN 0xA340F0
493 #define FSEQ_CNVI_ID 0xA3408C
494 #define FSEQ_CNVR_ID 0xA34090
495 #define FSEQ_PREV_CNVIO_INIT_VERSION 0xA34084
496 #define FSEQ_WIFI_FSEQ_VERSION 0xA34040
497 #define FSEQ_BT_FSEQ_VERSION 0xA34044
498 #define FSEQ_CLASS_TP_VERSION 0xA34078
500 #define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3
501 #define IWL_D3_SLEEP_STATUS_RESUME 0xD0
504 #define WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK 0xFFFFF
506 #define WMAL_MRSPF_1 0xADFC20
507 #define WMAL_INDRCT_RD_CMD1 0xADFD44
508 #define WMAL_INDRCT_CMD1 0xADFC14
513 #define WFPM_LMAC1_PS_CTL_RW 0xA03380
514 #define WFPM_LMAC2_PS_CTL_RW 0xA033C0
515 #define WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK 0x0000000F
517 #define HBUS_TIMEOUT 0xA5A5A5A1
518 #define WFPM_DPHY_OFF 0xDF10FF
520 #define REG_OTP_MINOR 0xA0333C
522 #define WFPM_LMAC2_PD_NOTIFICATION 0xA033CC
525 #define DPHYIP_INDIRECT 0xA2D800
526 #define DPHYIP_INDIRECT_RD_MSK 0xFF000000