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1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
14 * low power states due to driver-invoked device resets
15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
45 * 31-16: Reserved
46 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
47 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
48 * 1-0: "Dash" (-) value, as in A-1, etc.
57 * 11:8: Step (A - 0x0, B - 0x1, etc)
64 * EEPROM and OTP (one-time-programmable) memory reads
78 * UCODE-DRIVER GP (general purpose) mailbox registers.
122 /* Doorbell - since Bz
131 /* Analog phase-lock-loop configuration */
146 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
147 * 1-0: "Dash" (-) value, as in C-1, etc.
155 * Scratch register initial configuration - this is set on init, and read
252 * Indicates state of (platform's) hardware RF-Kill switch
253 * 26-24: POWER_SAVE_TYPE
254 * Indicates current power-saving mode:
255 * 000 -- No power saving
256 * 001 -- MAC power-down
257 * 010 -- PHY (radio) power-down
258 * 011 -- Error
260 * 9-6: SYS_CONFIG
264 * Indicates MAC is entering a power-saving sleep power-down.
265 * Not a good time to access device-internal resources.
268 * access to device-internal resources. Host must wait for
269 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
272 * Host sets this to put device into fully operational D0 power mode.
273 * Host resets this after SW_RESET to put device into low power mode.
279 * init or post-power-down restore of internal SRAM memory.
281 * SRAM is restored and uCode is in normal operation mode.
282 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
387 /* One-time-programmable memory general purpose reg */
388 #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
389 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
405 * UCODE-DRIVER GP (general purpose) mailbox register 1
416 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
418 * unassociated mode, and power down.
424 * uCode sets this when preparing a power-saving power-down.
425 * uCode resets this when power-up is complete and SRAM is sane.
429 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
497 * HBUS (Host-side Bus)
501 * may be powered-down.
518 * data registers auto-increment the address by one dword.
520 * 0-31: memory address within device
536 * 0-15: register address (offset) within device
537 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
548 * Per-Tx-queue write pointer (index, really!)
551 * 0-7: queue write index
552 * 11-8: queue selector
565 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
586 /* Those are the masks INSIDE the flags bit-field: */
654 #define CSR_ADDR_BASE(trans) ((trans)->mac_cfg->base->mac_addr_from_csr)