Lines Matching +full:sub +full:- +full:units
1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
79 * Acquire il->lock before calling this function !
83 * il4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
84 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
87 * NOTE: Acquire il->lock before calling this function !
181 * The first queue used for block-ack aggregation is #7 (4965 only).
182 * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
194 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
196 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
221 * real-time temperature indicator.
229 * NOTE: uCode provides the R4 value as a 23-bit signed value. Driver
230 * must sign-extend to 32 bits before applying formula below.
234 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
236 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
242 * temperature with factory-measured temperatures when calculating txpower
279 * sub-bands of contiguous channels. 2.4GHz has just one sub-band,
280 * but 5 GHz has several sub-bands.
282 * In addition, per-band (2.4 and 5 Ghz) saturation txpowers are provided.
310 * If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
312 * regulatory limit by 3 dB (half-power) for each transmitter, so the
317 * backoff for this bit rate*. Do not exceed (saturation - backoff[rate]);
320 * Backoff values below are in 1/2 dB units (equivalent to steps in
323 * OFDM 6 - 36 MBit: 10 steps (5 dB)
329 * Backoff values apply to saturation txpower on a per-transmitter basis;
343 * 3) Determine (EEPROM) calibration sub band for the target channel, by
344 * comparing against first and last channels in each sub band
349 * referencing the 2 factory-measured (sample) channels within the sub band.
357 * edges of the sub band. The target channel may be "outside" of the
373 * be used (although only one at a time) even for non-MIMO transmissions.
385 * factory-measured txpower. Using (interpolated) factory gain table idx
396 * factory-measured temperature for sub-band. Factory values are in
405 * 2.4 GHz all channels: 3.5 degrees per half-dB step
406 * 5 GHz channels 34-43: 4.5 degrees per half-dB step
407 * 5 GHz channels >= 44: 4.0 degrees per half-dB step
416 * (from "initialize alive") and factory-measured power supply voltage
422 * (eeprom - current) / 7
427 * 2 * (current - eeprom) / 7
440 * 8) If setting up txpowers for MIMO rates (rate idxes 8-15, 24-31),
445 * Group 0: 5 GHz channel 34-43
446 * Group 1: 5 GHz channel 44-70
447 * Group 2: 5 GHz channel 71-124
448 * Group 3: 5 GHz channel 125-200
452 * The values are signed, but are in pairs of 0 and a non-negative number,
454 * avoids any need to double-check for regulatory compliance after
523 * 1) DSP gain (or sometimes called DSP attenuation). This is a fine-grained
531 * below ("well-known" means here that both factory calibration *and* the
541 #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
652 * -9 123 0x3F (highest gain)
653 * -8 117 0x3F
654 * -7 110 0x3F
655 * -6 104 0x3F
656 * -5 98 0x3F
657 * -4 110 0x3E
658 * -3 104 0x3E
659 * -2 98 0x3E
660 * -1 110 0x3D
768 * to be operated. These limits are SKU-specific (i.e. geography-specific),
769 * and channel-specific; each channel has an individual regulatory limit
772 * Units are in half-dBm (i.e. "34" means 17 dBm).
793 * Units are in half-dBm (i.e. "38" means 19 dBm).
814 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
818 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
822 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
826 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
861 * 4965 supports up to 16 DRAM-based Tx queues, and services these queues via
875 * Each Tx queue uses a byte-count table containing 320 entries:
876 * one 16-bit entry for each of 256 TFDs, plus an additional 64 entries that
877 * duplicate the first 64 entries (to avoid wrap-around within a Tx win;
882 * count table for the chosen Tx queue. If the TFD idx is 0-63, the driver
883 * must duplicate the byte count entry in corresponding idx 256-319.
885 * padding puts each byte count table on a 1024-byte boundary;
890 u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
929 * Keep-Warm (KW) buffer base address.
932 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
934 * from going into a power-savings mode that would cause higher DRAM latency,
935 * and possible data over/under-runs, before all Tx/Rx is complete.
939 * automatically invokes keep-warm accesses when normal accesses might not
943 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
950 * 4965 has 16 base pointer registers, one for each of 16 host-DRAM-resident
953 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
954 * aligned (address bits 0-7 must be 0).
957 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
962 /* Find TFD CB base pointer for given queue (range 0-15). */
987 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
999 * 31-12: Not used by driver
1000 * 11- 0: Index of last filled Rx buffer descriptor
1009 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1039 * Physical base address of 8-byte Rx Status buffer.
1041 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1048 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1055 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1056 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1073 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1075 * 29-24: reserved
1076 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1078 * 19-18: reserved
1079 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1081 * 15-14: reserved
1082 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1083 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1085 * 3- 0: reserved
1093 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1096 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1097 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1098 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */
1142 /* TFDB Area - TFDs buffer table */
1165 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1167 * 29- 4: Reserved, set to "0"
1169 * 2- 0: Reserved, set to "0"
1220 * 31-24: 1 = Channel buffers empty (channel 7:0)
1221 * 23-16: 1 = No pending requests (channel 7:0)
1234 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1238 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1254 (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1258 * it is brought from the memory to TX-FIFO