Lines Matching +full:0 +full:x1e000000
14 u32 chipid; /* 0x0 */
20 u32 otpstatus; /* 0x10, corerev >= 10 */
26 u32 intstatus; /* 0x20 */
30 u32 chipcontrol; /* 0x28, rev >= 11 */
31 u32 chipstatus; /* 0x2c, rev >= 11 */
34 u32 jtagcmd; /* 0x30, rev >= 10 */
40 u32 flashcontrol; /* 0x40 */
46 u32 broadcastaddress; /* 0x50 */
50 u32 gpiopullup; /* 0x58, corerev >= 20 */
51 u32 gpiopulldown; /* 0x5c, corerev >= 20 */
52 u32 gpioin; /* 0x60 */
53 u32 gpioout; /* 0x64 */
54 u32 gpioouten; /* 0x68 */
55 u32 gpiocontrol; /* 0x6C */
56 u32 gpiointpolarity; /* 0x70 */
57 u32 gpiointmask; /* 0x74 */
64 u32 watchdog; /* 0x80 */
70 u32 gpiotimerval; /* 0x88 */
74 u32 clockcontrol_n; /* 0x90 */
81 u32 capabilities_ext; /* 0xac */
84 u32 pll_on_delay; /* 0xb0 */
90 u32 system_clk_ctl; /* 0xc0 */
95 u32 bp_addrlow; /* 0xd0 */
107 u32 eromptr; /* 0xfc */
110 u32 pcmcia_config; /* 0x100 */
122 u32 SECI_config; /* 0x130 SECI configuration */
126 u32 eci_output; /* 0x140 */
146 u32 sromcontrol; /* 0x190 */
152 u32 clk_ctl_st; /* 0x1e0 */
157 u8 uart0data; /* 0x300 */
167 u8 uart1data; /* 0x400 */
178 u32 sr_capability; /* 0x500 */
179 u32 sr_control0; /* 0x504 */
180 u32 sr_control1; /* 0x508 */
181 u32 gpio_control; /* 0x50C */
185 u32 pmucontrol; /* 0x600 */
199 u32 gpiosel; /* 0x638, rev >= 1 */
200 u32 gpioenable; /* 0x63c, rev >= 1 */
204 u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */
205 u32 chipcontrol_addr; /* 0x650 */
206 u32 chipcontrol_data; /* 0x654 */
211 u32 pmustrapopt; /* 0x668, corerev >= 28 */
212 u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
213 u32 retention_ctl; /* 0x670, pmurev >= 15 */
215 u32 retention_grpidx; /* 0x680 */
216 u32 retention_grpctl; /* 0x684 */
222 #define CID_ID_MASK 0x0000ffff /* Chip Id mask */
223 #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
225 #define CID_PKG_MASK 0x00f00000 /* Package Option mask */
227 #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
229 #define CID_TYPE_MASK 0xf0000000 /* Chip Type */
233 #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */
234 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
235 #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */
237 #define CC_CAP_UINTCLK 0x00000008
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
239 #define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */
240 #define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */
241 #define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */
242 #define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */
243 #define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */
244 #define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */
245 #define CC_CAP_PWR_CTL 0x00040000 /* Power control */
246 #define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
249 #define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */
250 #define CC_CAP_ROM 0x00800000 /* Internal boot rom active */
251 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
252 #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
253 #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */
255 #define CC_CAP_NFLASH 0x80000000
257 #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */
259 #define CC_CAP2_GSIO 0x00000002
262 #define CC_SR_CTL0_ENABLE_MASK BIT(0)
263 #define CC_SR_CTL0_ENABLE_SHIFT 0
265 #define CC_SR_CTL0_RSRC_TRIGGER_SHIFT 2 /* Rising edge resource trigger 0 to
281 #define PCAP_REV_MASK 0x000000ff
282 #define PCAP_RC_MASK 0x00001f00
284 #define PCAP_TC_MASK 0x0001e000
286 #define PCAP_PC_MASK 0x001e0000
288 #define PCAP_VC_MASK 0x01e00000
290 #define PCAP_CC_MASK 0x1e000000
292 #define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */
294 #define PCAP5_VC_MASK 0x07c00000
296 #define PCAP5_CC_MASK 0xf8000000