Lines Matching defs:wlc_hw
588 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
591 struct bcma_device *core = wlc_hw->d11core;
596 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
600 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
673 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
676 struct bcma_device *core = wlc_hw->d11core;
682 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
697 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
706 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
709 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
711 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
714 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
717 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
718 if (BRCMS_ISNPHY(wlc_hw->band))
719 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
721 brcms_err(wlc_hw->d11core,
723 __func__, wlc_hw->unit,
724 wlc_hw->corerev);
726 if (D11REV_IS(wlc_hw->corerev, 24)) {
727 if (BRCMS_ISLCNPHY(wlc_hw->band))
728 brcms_c_write_inits(wlc_hw,
731 brcms_err(wlc_hw->d11core,
733 __func__, wlc_hw->unit,
734 wlc_hw->corerev);
736 brcms_err(wlc_hw->d11core,
738 __func__, wlc_hw->unit, wlc_hw->corerev);
743 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
745 struct bcma_device *core = wlc_hw->d11core;
751 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
753 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
755 wlc_hw->phyclk = clk;
759 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
762 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
767 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
769 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
776 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
778 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
781 wlc_hw->band = wlc_hw->bandstate[bandunit];
787 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
790 if (wlc_hw->sbclk && !wlc_hw->noreset) {
796 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
803 struct brcms_hardware *wlc_hw = wlc->hw;
807 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
808 macctrl = bcma_read32(wlc_hw->d11core,
816 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
818 brcms_b_core_phy_clk(wlc_hw, OFF);
820 brcms_c_setxband(wlc_hw, bandunit);
1015 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1028 core = wlc_hw->d11core;
1034 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1050 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1073 struct brcms_hardware *wlc_hw = wlc->hw;
1080 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1083 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1105 struct brcms_hardware *wlc_hw = wlc->hw;
1106 uint unit = wlc_hw->unit;
1111 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1119 wlc_hw->di[0] = dma_attach(name, wlc,
1125 dma_attach_err |= (NULL == wlc_hw->di[0]);
1133 wlc_hw->di[1] = dma_attach(name, wlc,
1136 dma_attach_err |= (NULL == wlc_hw->di[1]);
1143 wlc_hw->di[2] = dma_attach(name, wlc,
1146 dma_attach_err |= (NULL == wlc_hw->di[2]);
1152 wlc_hw->di[3] = dma_attach(name, wlc,
1156 dma_attach_err |= (NULL == wlc_hw->di[3]);
1160 brcms_err(wlc_hw->d11core,
1168 if (wlc_hw->di[i])
1169 wlc_hw->txavail[i] =
1170 (uint *) dma_getvar(wlc_hw->di[i],
1175 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1180 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1185 if (wlc_hw->di[j]) {
1186 dma_detach(wlc_hw->di[j]);
1187 wlc_hw->di[j] = NULL;
1197 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1199 struct brcms_c_info *wlc = wlc_hw->wlc;
1205 wlc_hw->shortslot = false;
1207 wlc_hw->SFBL = RETRY_SHORT_FB;
1208 wlc_hw->LFBL = RETRY_LONG_FB;
1211 wlc_hw->SRL = RETRY_SHORT_DEF;
1212 wlc_hw->LRL = RETRY_LONG_DEF;
1213 wlc_hw->chanspec = ch20mhz_chspec(1);
1216 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1222 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1223 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1227 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1229 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1236 if (wlc_hw->clk) {
1238 bcma_set32(wlc_hw->d11core,
1245 ((bcma_read32(wlc_hw->d11core,
1249 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1253 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1254 (bcma_read32(wlc_hw->d11core,
1258 ((bcma_read32(wlc_hw->d11core,
1263 bcma_mask32(wlc_hw->d11core,
1268 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1275 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1278 if (wlc_hw->forcefastclk && wlc_hw->clk)
1279 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1292 if (wlc_hw->forcefastclk)
1293 mboolset(wlc_hw->wake_override,
1296 mboolclr(wlc_hw->wake_override,
1313 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1332 band = wlc_hw->band;
1335 band = wlc_hw->bandstate[BAND_5G_INDEX];
1338 band = wlc_hw->bandstate[BAND_2G_INDEX];
1351 if (wlc_hw->clk && (band->mhfs[idx] != save)
1352 && (band == wlc_hw->band))
1353 brcms_b_write_shm(wlc_hw, addr[idx],
1358 wlc_hw->bandstate[0]->mhfs[idx] =
1359 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1360 wlc_hw->bandstate[1]->mhfs[idx] =
1361 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1368 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1371 wlc_hw->maccontrol = 0;
1372 wlc_hw->suspended_fifos = 0;
1373 wlc_hw->wake_override = 0;
1374 wlc_hw->mute_override = 0;
1375 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1382 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1384 u32 maccontrol = wlc_hw->maccontrol;
1387 if (wlc_hw->wake_override)
1391 if (wlc_hw->mute_override) {
1396 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1401 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1408 maccontrol = wlc_hw->maccontrol;
1416 wlc_hw->maccontrol = new_maccontrol;
1419 brcms_c_mctrl_write(wlc_hw);
1422 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1425 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1426 mboolset(wlc_hw->wake_override, override_bit);
1430 mboolset(wlc_hw->wake_override, override_bit);
1432 brcms_c_mctrl_write(wlc_hw);
1433 brcms_b_wait_for_wake(wlc_hw);
1436 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1439 mboolclr(wlc_hw->wake_override, override_bit);
1441 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1444 brcms_c_mctrl_write(wlc_hw);
1454 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1456 wlc_hw->mute_override = 1;
1461 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1464 brcms_c_mctrl_write(wlc_hw);
1468 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1470 if (wlc_hw->mute_override == 0)
1473 wlc_hw->mute_override = 0;
1478 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1481 brcms_c_mctrl_write(wlc_hw);
1488 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1491 struct bcma_device *core = wlc_hw->d11core;
1496 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1511 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1514 struct bcma_device *core = wlc_hw->d11core;
1519 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1547 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1549 wlc_hw->band->CWmin = newmin;
1551 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1553 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1554 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1557 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1559 wlc_hw->band->CWmax = newmax;
1561 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1563 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1564 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1567 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1572 fastclk = wlc_hw->forcefastclk;
1574 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1576 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1578 brcms_b_phy_reset(wlc_hw);
1579 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1583 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1586 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1589 struct brcms_c_info *wlc = wlc_hw->wlc;
1599 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1602 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1605 u16 phytxant = wlc_hw->bmac_phytxant;
1609 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1611 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1614 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1616 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1619 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1650 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1653 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1664 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1671 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1675 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1679 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1682 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1690 struct brcms_hardware *wlc_hw = wlc->hw;
1692 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1693 wlc_hw->band->bandunit);
1695 brcms_c_ucode_bsinit(wlc_hw);
1697 wlc_phy_init(wlc_hw->band->pi, chanspec);
1699 brcms_c_ucode_txant_set(wlc_hw);
1705 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1706 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1708 brcms_b_update_slot_timing(wlc_hw,
1709 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1710 true : wlc_hw->shortslot);
1713 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1714 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1720 brcms_upd_ofdm_pctl1_table(wlc_hw);
1722 brcms_b_upd_synthpu(wlc_hw);
1726 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1728 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1731 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1734 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1737 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1748 if (!BRCMS_ISNPHY(wlc_hw->band))
1752 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1754 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1758 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1761 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1763 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1766 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1768 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1771 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1776 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1779 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1780 NREV_LE(wlc_hw->band->phyrev, 4)) {
1782 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1787 brcms_b_core_phypll_reset(wlc_hw);
1790 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1793 brcms_b_core_ioctl(wlc_hw,
1799 brcms_b_core_phy_clk(wlc_hw, ON);
1805 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1807 struct brcms_c_info *wlc = wlc_hw->wlc;
1811 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1812 bcma_core_enable(wlc_hw->d11core, 0);
1813 brcms_c_mctrl_reset(wlc_hw);
1818 if (!wlc_hw->up)
1821 brcms_b_core_phy_clk(wlc_hw, ON);
1838 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1842 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1846 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1847 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1848 wlc_hw->corerev);
1856 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1858 uint boardrev = wlc_hw->boardrev;
1867 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1884 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1886 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1894 if (wlc_hw->_nbands > 1)
1901 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1903 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1909 if (!want && wlc_hw->pllreq)
1912 wlc_hw->sbclk = want;
1913 if (!wlc_hw->sbclk) {
1914 wlc_hw->clk = false;
1915 if (wlc_hw->band && wlc_hw->band->pi)
1916 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1926 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1931 xtal = wlc_hw->sbclk;
1933 brcms_b_xtal(wlc_hw, ON);
1936 clk = wlc_hw->clk;
1943 if (D11REV_GE(wlc_hw->corerev, 18))
1953 bcma_core_enable(wlc_hw->d11core, flags);
1954 brcms_c_mctrl_reset(wlc_hw);
1957 v = ((bcma_read32(wlc_hw->d11core,
1962 bcma_core_disable(wlc_hw->d11core, 0);
1965 brcms_b_xtal(wlc_hw, OFF);
1970 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1972 struct dma_pub *di = wlc_hw->di[fifo];
1982 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1984 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1990 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1992 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
1995 fastclk = wlc_hw->forcefastclk;
1997 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2000 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2002 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2003 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2005 wlc_hw->unit, __func__, i);
2007 if ((wlc_hw->di[RX_FIFO])
2008 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2009 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2011 wlc_hw->unit, __func__, RX_FIFO);
2014 if (wlc_hw->noreset) {
2015 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2016 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2025 if (D11REV_GE(wlc_hw->corerev, 18))
2038 wlc_hw->clk = false;
2039 bcma_core_enable(wlc_hw->d11core, flags);
2040 wlc_hw->clk = true;
2041 if (wlc_hw->band && wlc_hw->band->pi)
2042 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2044 brcms_c_mctrl_reset(wlc_hw);
2046 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2047 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2049 brcms_b_phy_reset(wlc_hw);
2052 brcms_b_core_phypll_ctl(wlc_hw, true);
2055 wlc_hw->wlc->macintstatus = 0;
2059 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2065 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2067 struct bcma_device *core = wlc_hw->d11core;
2079 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2094 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2100 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2101 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2102 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2103 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2104 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2105 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2107 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2108 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2125 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2127 struct bcma_device *core = wlc_hw->d11core;
2129 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2130 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2141 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2181 struct brcms_hardware *wlc_hw = wlc->hw;
2185 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2198 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2200 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2202 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2206 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2208 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2214 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2216 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2220 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2222 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2226 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2234 if (wlc_hw->boardflags & BFL_PACTRL)
2238 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2241 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2244 struct bcma_device *core = wlc_hw->d11core;
2248 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2260 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2262 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2264 if (wlc_hw->ucode_loaded)
2267 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2268 if (BRCMS_ISNPHY(wlc_hw->band)) {
2269 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2271 wlc_hw->ucode_loaded = true;
2273 brcms_err(wlc_hw->d11core,
2275 __func__, wlc_hw->unit, wlc_hw->corerev);
2276 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2277 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2278 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2280 wlc_hw->ucode_loaded = true;
2282 brcms_err(wlc_hw->d11core,
2284 __func__, wlc_hw->unit, wlc_hw->corerev);
2289 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2292 wlc_hw->bmac_phytxant = phytxant;
2295 if (!wlc_hw->up)
2297 brcms_c_ucode_txant_set(wlc_hw);
2301 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2303 return (u16) wlc_hw->wlc->stf->txant;
2306 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2308 wlc_hw->antsel_type = antsel_type;
2311 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2314 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2319 struct bcma_device *core = wlc_hw->d11core;
2321 unit = wlc_hw->unit;
2370 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2381 struct brcms_hardware *wlc_hw = wlc->hw;
2383 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2388 struct brcms_hardware *wlc_hw = wlc->hw;
2391 if (!wlc_hw->clk)
2396 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2397 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2407 struct brcms_hardware *wlc_hw = wlc->hw;
2408 if (!wlc_hw->clk)
2412 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2416 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2424 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2428 if (wlc_hw->suspended_fifos == 0)
2429 brcms_c_ucode_wake_override_set(wlc_hw,
2432 wlc_hw->suspended_fifos |= fifo;
2434 if (wlc_hw->di[tx_fifo]) {
2440 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2441 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2443 dma_txsuspend(wlc_hw->di[tx_fifo]);
2445 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2446 brcms_c_enable_mac(wlc_hw->wlc);
2450 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2458 if (wlc_hw->di[tx_fifo])
2459 dma_txresume(wlc_hw->di[tx_fifo]);
2462 if (wlc_hw->suspended_fifos == 0)
2465 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2466 if (wlc_hw->suspended_fifos == 0)
2467 brcms_c_ucode_wake_override_clear(wlc_hw,
2473 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2476 u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2480 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2481 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2482 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2483 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2486 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2489 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2490 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2491 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2492 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2495 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2498 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2501 brcms_c_ucode_mute_override_set(wlc_hw);
2503 brcms_c_ucode_mute_override_clear(wlc_hw);
2522 struct brcms_hardware *wlc_hw = wlc->hw;
2523 struct bcma_device *core = wlc_hw->d11core;
2597 struct brcms_hardware *wlc_hw = wlc->hw;
2600 if (!wlc_hw->up || !wlc->macintmask)
2607 brcms_err(wlc_hw->d11core,
2625 struct brcms_hardware *wlc_hw = wlc->hw;
2626 struct bcma_device *core = wlc_hw->d11core;
2629 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2630 wlc_hw->band->bandunit);
2635 wlc_hw->mac_suspend_depth++;
2636 if (wlc_hw->mac_suspend_depth > 1)
2640 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2645 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2656 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2663 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2671 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2673 "psm_brc 0x%04x\n", wlc_hw->unit,
2681 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2693 struct brcms_hardware *wlc_hw = wlc->hw;
2694 struct bcma_device *core = wlc_hw->d11core;
2697 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2703 wlc_hw->mac_suspend_depth--;
2704 if (wlc_hw->mac_suspend_depth > 0)
2712 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2723 brcms_c_ucode_wake_override_clear(wlc_hw,
2727 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2729 wlc_hw->hw_stf_ss_opmode = stf_mode;
2731 if (wlc_hw->clk)
2732 brcms_upd_ofdm_pctl1_table(wlc_hw);
2735 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2737 struct bcma_device *core = wlc_hw->d11core;
2739 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2757 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2770 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2785 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2796 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2798 struct bcma_device *core = wlc_hw->d11core;
2801 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2806 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2849 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2853 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2855 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2860 if (wlc_hw->noreset)
2864 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2867 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2870 brcms_b_core_phypll_ctl(wlc_hw, false);
2872 wlc_hw->clk = false;
2873 bcma_core_disable(wlc_hw->d11core, 0);
2874 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2879 struct brcms_hardware *wlc_hw = wlc->hw;
2884 if (wlc_hw->di[i]) {
2885 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2893 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2897 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2899 struct bcma_device *core = wlc_hw->d11core;
2911 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2914 struct bcma_device *core = wlc_hw->d11core;
2929 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2931 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2938 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2940 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2950 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2962 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2973 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2984 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3000 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3003 wlc_hw->SRL = SRL;
3004 wlc_hw->LRL = LRL;
3007 if (wlc_hw->up) {
3008 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3010 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3011 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3012 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3014 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3015 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3019 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3022 if (mboolisset(wlc_hw->pllreq, req_bit))
3025 mboolset(wlc_hw->pllreq, req_bit);
3027 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3028 if (!wlc_hw->sbclk)
3029 brcms_b_xtal(wlc_hw, ON);
3032 if (!mboolisset(wlc_hw->pllreq, req_bit))
3035 mboolclr(wlc_hw->pllreq, req_bit);
3037 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3038 if (wlc_hw->sbclk)
3039 brcms_b_xtal(wlc_hw, OFF);
3044 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3046 wlc_hw->antsel_avail = antsel_avail;
3112 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3115 if (!brcms_deviceremoved(wlc_hw->wlc))
3116 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3119 brcms_c_flushqueues(wlc_hw->wlc);
3158 struct brcms_hardware *wlc_hw = wlc->hw;
3159 struct bcma_device *core = wlc_hw->d11core;
3165 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3167 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3170 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3172 brcms_ucode_download(wlc_hw);
3180 brcms_b_mctrl(wlc_hw, ~0,
3188 "suspend!\n", wlc_hw->unit);
3194 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3195 if (BRCMS_ISNPHY(wlc_hw->band))
3196 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3199 " %d\n", __func__, wlc_hw->unit,
3200 wlc_hw->corerev);
3201 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3202 if (BRCMS_ISLCNPHY(wlc_hw->band))
3203 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3206 " %d\n", __func__, wlc_hw->unit,
3207 wlc_hw->corerev);
3210 __func__, wlc_hw->unit, wlc_hw->corerev);
3215 brcms_b_corerev_fifofixup(wlc_hw);
3218 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3219 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3223 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3224 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3228 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3231 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3235 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3239 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3242 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3246 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3253 wlc_hw->xmtfifo_sz[i], i);
3261 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3262 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3268 brcms_b_mctrl(wlc_hw,
3284 brcms_b_macphyclk_set(wlc_hw, ON);
3287 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3291 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3294 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3295 (u16) (wlc_hw->machwcap & 0xffff));
3296 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3297 (u16) ((wlc_hw->
3304 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3308 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3311 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3312 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3319 if (wlc_hw->di[i])
3320 dma_txinit(wlc_hw->di[i]);
3324 dma_rxinit(wlc_hw->di[RX_FIFO]);
3325 dma_rxfill(wlc_hw->di[RX_FIFO]);
3328 static void brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec)
3332 struct brcms_c_info *wlc = wlc_hw->wlc;
3335 fastclk = wlc_hw->forcefastclk;
3337 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3343 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3344 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3347 wlc_phy_cal_init(wlc_hw->band->pi);
3361 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3367 wlc_hw->mac_suspend_depth = 1;
3371 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3782 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3784 wlc_hw->shortslot = shortslot;
3786 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3787 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3788 brcms_b_update_slot_timing(wlc_hw, shortslot);
3789 brcms_c_enable_mac(wlc_hw->wlc);
3822 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3827 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: 0x%x\n", wlc_hw->unit,
3830 wlc_hw->chanspec = chanspec;
3833 if (wlc_hw->_nbands > 1) {
3835 if (wlc_hw->band->bandunit != bandunit) {
3839 if (wlc_hw->up) {
3840 wlc_phy_chanspec_radio_set(wlc_hw->
3843 brcms_b_setband(wlc_hw, bandunit, chanspec);
3845 brcms_c_setxband(wlc_hw, bandunit);
3850 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3852 if (!wlc_hw->up) {
3853 if (wlc_hw->clk)
3854 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3856 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3858 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3859 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3862 brcms_b_mute(wlc_hw, mute_tx);
4189 struct brcms_hardware *wlc_hw = wlc->hw;
4191 if (!wlc_hw->up)
4195 wlc_hw->now++;
4198 brcms_b_fifoerrors(wlc_hw);
4203 wlc_phy_watchdog(wlc_hw->band->pi);
4377 struct brcms_hardware *wlc_hw;
4397 wlc_hw = wlc->hw;
4398 wlc_hw->wlc = wlc;
4399 wlc_hw->unit = unit;
4400 wlc_hw->band = wlc_hw->bandstate[0];
4401 wlc_hw->_piomode = piomode;
4404 brcms_b_info_init(wlc_hw);
4410 wlc_hw->sih = ai_attach(core->bus);
4411 if (wlc_hw->sih == NULL) {
4427 wlc_hw->vendorid = pcidev->vendor;
4428 wlc_hw->deviceid = pcidev->device;
4430 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4431 wlc_hw->deviceid = core->bus->boardinfo.type;
4434 wlc_hw->d11core = core;
4435 wlc_hw->corerev = core->id.rev;
4438 if (!brcms_c_isgoodchip(wlc_hw)) {
4444 ai_clkctl_init(wlc_hw->sih);
4452 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4453 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4455 if (!brcms_b_validate_chip_access(wlc_hw)) {
4467 wlc_hw->boardrev = (u16) j;
4468 if (!brcms_c_validboardtype(wlc_hw)) {
4471 unit, ai_get_boardtype(wlc_hw->sih),
4472 wlc_hw->boardrev);
4476 wlc_hw->sromrev = sprom->revision;
4477 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4478 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4480 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4481 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4484 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4485 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1 ||
4486 wlc_hw->deviceid == BCM43224_CHIP_ID)
4488 wlc_hw->_nbands = 2;
4490 wlc_hw->_nbands = 1;
4492 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4493 wlc_hw->_nbands = 1;
4498 wlc->vendorid = wlc_hw->vendorid;
4499 wlc->deviceid = wlc_hw->deviceid;
4500 wlc->pub->sih = wlc_hw->sih;
4501 wlc->pub->corerev = wlc_hw->corerev;
4502 wlc->pub->sromrev = wlc_hw->sromrev;
4503 wlc->pub->boardrev = wlc_hw->boardrev;
4504 wlc->pub->boardflags = wlc_hw->boardflags;
4505 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4506 wlc->pub->_nbands = wlc_hw->_nbands;
4508 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4510 if (wlc_hw->physhim == NULL) {
4518 sha_params.sih = wlc_hw->sih;
4519 sha_params.physhim = wlc_hw->physhim;
4521 sha_params.corerev = wlc_hw->corerev;
4522 sha_params.vid = wlc_hw->vendorid;
4523 sha_params.did = wlc_hw->deviceid;
4524 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4525 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4526 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4527 sha_params.sromrev = wlc_hw->sromrev;
4528 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4529 sha_params.boardrev = wlc_hw->boardrev;
4530 sha_params.boardflags = wlc_hw->boardflags;
4531 sha_params.boardflags2 = wlc_hw->boardflags2;
4534 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4535 if (!wlc_hw->phy_sh) {
4541 for (j = 0; j < wlc_hw->_nbands; j++) {
4547 brcms_c_setxband(wlc_hw, j);
4549 wlc_hw->band->bandunit = j;
4550 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4555 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4556 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4559 WARN_ON(wlc_hw->corerev < XMTFIFOTBL_STARTREV ||
4560 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4562 wlc_hw->xmtfifo_sz =
4563 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4564 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4567 wlc_hw->band->pi =
4568 wlc_phy_attach(wlc_hw->phy_sh, core,
4569 wlc_hw->band->bandtype,
4571 if (wlc_hw->band->pi == NULL) {
4578 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4580 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4581 &wlc_hw->band->phyrev,
4582 &wlc_hw->band->radioid,
4583 &wlc_hw->band->radiorev);
4584 wlc_hw->band->abgphy_encore =
4585 wlc_phy_get_encore(wlc_hw->band->pi);
4586 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4587 wlc_hw->band->core_flags =
4588 wlc_phy_get_coreflags(wlc_hw->band->pi);
4591 if (BRCMS_ISNPHY(wlc_hw->band)) {
4592 if (NCONF_HAS(wlc_hw->band->phyrev))
4596 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4597 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4605 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4615 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4616 * keeping wlc_hw->band->pi as well for incremental update of
4620 wlc->band->pi = wlc_hw->band->pi;
4621 wlc->band->phytype = wlc_hw->band->phytype;
4622 wlc->band->phyrev = wlc_hw->band->phyrev;
4623 wlc->band->radioid = wlc_hw->band->radioid;
4624 wlc->band->radiorev = wlc_hw->band->radiorev;
4629 wlc_hw->band->CWmin = APHY_CWMIN;
4630 wlc_hw->band->CWmax = PHY_CWMAX;
4639 brcms_c_coredisable(wlc_hw);
4642 bcma_host_pci_down(wlc_hw->d11core->bus);
4645 brcms_b_xtal(wlc_hw, OFF);
4658 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4660 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4661 is_zero_ether_addr(wlc_hw->etheraddr)) {
4668 brcms_dbg_info(wlc_hw->d11core, "deviceid 0x%x nbands %d board 0x%x\n",
4669 wlc_hw->deviceid, wlc_hw->_nbands,
4670 ai_get_boardtype(wlc_hw->sih));
4810 struct brcms_hardware *wlc_hw = wlc->hw;
4812 brcms_b_detach_dmapio(wlc_hw);
4814 band = wlc_hw->band;
4815 for (i = 0; i < wlc_hw->_nbands; i++) {
4821 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4825 kfree(wlc_hw->phy_sh);
4827 wlc_phy_shim_detach(wlc_hw->physhim);
4829 if (wlc_hw->sih) {
4830 ai_detach(wlc_hw->sih);
4831 wlc_hw->sih = NULL;
4877 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4879 if (wlc_hw->wlc->pub->hw_up)
4882 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4888 brcms_b_xtal(wlc_hw, ON);
4889 ai_clkctl_init(wlc_hw->sih);
4890 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4903 wlc_phy_por_inform(wlc_hw->band->pi);
4905 wlc_hw->ucode_loaded = false;
4906 wlc_hw->wlc->pub->hw_up = true;
4908 if ((wlc_hw->boardflags & BFL_FEM)
4909 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4911 (wlc_hw->boardrev >= 0x1250
4912 && (wlc_hw->boardflags & BFL_FEM_BT)))
4913 ai_epa_4313war(wlc_hw->sih);
4917 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
4919 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
4925 brcms_b_xtal(wlc_hw, ON);
4926 ai_clkctl_init(wlc_hw->sih);
4927 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4933 bcma_host_pci_irq_ctl(wlc_hw->d11core->bus, wlc_hw->d11core,
4941 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
4943 bcma_host_pci_down(wlc_hw->d11core->bus);
4944 brcms_b_xtal(wlc_hw, OFF);
4948 bcma_host_pci_up(wlc_hw->d11core->bus);
4951 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4956 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
4958 wlc_hw->up = true;
4959 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
4962 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
4963 brcms_intrson(wlc_hw->wlc->wl);
5079 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5084 if (!wlc_hw->up)
5087 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5091 wlc_hw->wlc->macintmask = 0;
5094 brcms_intrsoff(wlc_hw->wlc->wl);
5097 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5100 callbacks += wlc_phy_down(wlc_hw->band->pi);
5105 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5110 if (!wlc_hw->up)
5113 wlc_hw->up = false;
5114 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5116 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5119 wlc_hw->sbclk = false;
5120 wlc_hw->clk = false;
5121 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5124 brcms_c_flushqueues(wlc_hw->wlc);
5128 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5129 if (bcma_read32(wlc_hw->d11core,
5131 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5132 callbacks += brcms_reset(wlc_hw->wlc->wl);
5133 brcms_c_coredisable(wlc_hw);
5137 if (!wlc_hw->noreset) {
5138 bcma_host_pci_down(wlc_hw->d11core->bus);
5139 brcms_b_xtal(wlc_hw, OFF);
5628 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5648 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
6943 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
6946 struct bcma_device *core = wlc_hw->d11core;
7237 struct brcms_hardware *wlc_hw = wlc->hw;
7255 brcms_b_write_template_ram(wlc_hw, T_BCN0_TPL_BASE,
7259 brcms_b_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
7263 brcms_b_write_template_ram(wlc_hw, T_BCN1_TPL_BASE,
7267 brcms_b_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
7271 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7273 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, dtim_period);
7275 brcms_b_write_shm(wlc_hw, M_TIMBPOS_INBEACON,
7277 brcms_b_write_shm(wlc_hw, M_DOT11_DTIMPERIOD, 0);
7285 struct brcms_hardware *wlc_hw = wlc->hw;
7286 struct bcma_device *core = wlc_hw->d11core;
7456 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7462 *blocks = wlc_hw->xmtfifo_sz[fifo];
7645 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7663 morepending = dma_rx(wlc_hw->di[fifo], &recv_frames);
7668 dma_rxfill(wlc_hw->di[fifo]);
7692 brcms_c_recv(wlc_hw->wlc, p);
7705 struct brcms_hardware *wlc_hw = wlc->hw;
7706 struct bcma_device *core = wlc_hw->d11core;
7709 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
7720 wlc_hw->unit, macintstatus);
7750 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7755 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7759 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7762 __func__, ai_get_chip_id(wlc_hw->sih),
7763 ai_get_chiprev(wlc_hw->sih));
7764 brcms_fatal_error(wlc_hw->wlc->wl);
7773 " RF Disable Input\n", wlc_hw->unit);
7785 brcms_fatal_error(wlc_hw->wlc->wl);