Lines Matching +full:tx +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define B2055_C1_SP_RXGC1 0x07 /* SP RX GC1 Core 1 */
16 #define B2055_C1_SP_RXGC2 0x08 /* SP RX GC2 Core 1 */
17 #define B2055_C2_SP_RXGC1 0x09 /* SP RX GC1 Core 2 */
18 #define B2055_C2_SP_RXGC2 0x0A /* SP RX GC2 Core 2 */
21 #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
22 #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
23 #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
24 #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
30 #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
34 #define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
110 #define B2055_C1_RX_RFSPC1 0x66 /* Core 1 RX RF SPC1 */
111 #define B2055_C1_RX_RFR1 0x67 /* Core 1 RX RF reg 1 */
112 #define B2055_C1_RX_RFR2 0x68 /* Core 1 RX RF reg 2 */
113 #define B2055_C1_RX_RFRCAL 0x69 /* Core 1 RX RF RCAL */
114 #define B2055_C1_RX_BB_BLCMP 0x6A /* Core 1 RX Baseband BUFI LPF CMP */
115 #define B2055_C1_RX_BB_LPF 0x6B /* Core 1 RX Baseband LPF */
116 #define B2055_C1_RX_BB_MIDACHP 0x6C /* Core 1 RX Baseband MIDAC High-pass */
117 #define B2055_C1_RX_BB_VGA1IDAC 0x6D /* Core 1 RX Baseband VGA1 IDAC */
118 #define B2055_C1_RX_BB_VGA2IDAC 0x6E /* Core 1 RX Baseband VGA2 IDAC */
119 #define B2055_C1_RX_BB_VGA3IDAC 0x6F /* Core 1 RX Baseband VGA3 IDAC */
120 #define B2055_C1_RX_BB_BUFOCTL 0x70 /* Core 1 RX Baseband BUFO Control */
121 #define B2055_C1_RX_BB_RCCALCTL 0x71 /* Core 1 RX Baseband RCCAL Control */
122 #define B2055_C1_RX_BB_RSSICTL1 0x72 /* Core 1 RX Baseband RSSI Control 1 */
123 #define B2055_C1_RX_BB_RSSICTL2 0x73 /* Core 1 RX Baseband RSSI Control 2 */
124 #define B2055_C1_RX_BB_RSSICTL3 0x74 /* Core 1 RX Baseband RSSI Control 3 */
125 #define B2055_C1_RX_BB_RSSICTL4 0x75 /* Core 1 RX Baseband RSSI Control 4 */
126 #define B2055_C1_RX_BB_RSSICTL5 0x76 /* Core 1 RX Baseband RSSI Control 5 */
127 #define B2055_C1_RX_BB_REG 0x77 /* Core 1 RX Baseband Regulator */
128 #define B2055_C1_RX_BB_SPARE1 0x78 /* Core 1 RX Baseband spare 1 */
129 #define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */
130 #define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */
131 #define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */
132 #define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */
133 #define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */
134 #define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */
135 #define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */
136 #define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */
137 #define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */
138 #define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */
139 #define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */
140 #define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */
141 #define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */
142 #define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */
143 #define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */
144 #define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */
147 #define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */
148 #define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */
149 #define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */
157 #define B2055_C2_RX_RFSPC1 0x95 /* Core 2 RX RF SPC1 */
158 #define B2055_C2_RX_RFR1 0x96 /* Core 2 RX RF reg 1 */
159 #define B2055_C2_RX_RFR2 0x97 /* Core 2 RX RF reg 2 */
160 #define B2055_C2_RX_RFRCAL 0x98 /* Core 2 RX RF RCAL */
161 #define B2055_C2_RX_BB_BLCMP 0x99 /* Core 2 RX Baseband BUFI LPF CMP */
162 #define B2055_C2_RX_BB_LPF 0x9A /* Core 2 RX Baseband LPF */
163 #define B2055_C2_RX_BB_MIDACHP 0x9B /* Core 2 RX Baseband MIDAC High-pass */
164 #define B2055_C2_RX_BB_VGA1IDAC 0x9C /* Core 2 RX Baseband VGA1 IDAC */
165 #define B2055_C2_RX_BB_VGA2IDAC 0x9D /* Core 2 RX Baseband VGA2 IDAC */
166 #define B2055_C2_RX_BB_VGA3IDAC 0x9E /* Core 2 RX Baseband VGA3 IDAC */
167 #define B2055_C2_RX_BB_BUFOCTL 0x9F /* Core 2 RX Baseband BUFO Control */
168 #define B2055_C2_RX_BB_RCCALCTL 0xA0 /* Core 2 RX Baseband RCCAL Control */
169 #define B2055_C2_RX_BB_RSSICTL1 0xA1 /* Core 2 RX Baseband RSSI Control 1 */
170 #define B2055_C2_RX_BB_RSSICTL2 0xA2 /* Core 2 RX Baseband RSSI Control 2 */
171 #define B2055_C2_RX_BB_RSSICTL3 0xA3 /* Core 2 RX Baseband RSSI Control 3 */
172 #define B2055_C2_RX_BB_RSSICTL4 0xA4 /* Core 2 RX Baseband RSSI Control 4 */
173 #define B2055_C2_RX_BB_RSSICTL5 0xA5 /* Core 2 RX Baseband RSSI Control 5 */
174 #define B2055_C2_RX_BB_REG 0xA6 /* Core 2 RX Baseband Regulator */
175 #define B2055_C2_RX_BB_SPARE1 0xA7 /* Core 2 RX Baseband spare 1 */
176 #define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */
177 #define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */
178 #define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */
179 #define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */
180 #define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */
181 #define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */
182 #define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */
183 #define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */
184 #define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */
185 #define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */
186 #define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */
187 #define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */
188 #define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */
189 #define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */
190 #define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */
191 #define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */
194 #define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */
195 #define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */
196 #define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */
208 #define B2055_C1_B0NB_RSSIVCM 0xD2 /* Core 1 B0 narrow-band RSSI VCM */
211 #define B2055_C2_B0NB_RSSIVCM 0xDE /* Core 2 B0 narrow-band RSSI VCM */