Lines Matching full:tx
21 #define B2055_C1_SP_TXGC1 0x0D /* SP TX GC1 Core 1 */
22 #define B2055_C1_SP_TXGC2 0x0E /* SP TX GC2 Core 1 */
23 #define B2055_C2_SP_TXGC1 0x0F /* SP TX GC1 Core 2 */
24 #define B2055_C2_SP_TXGC2 0x10 /* SP TX GC2 Core 2 */
30 #define B2055_C1_PD_TX 0x16 /* PD Core 1 TX */
34 #define B2055_C2_PD_TX 0x1A /* PD Core 2 TX */
129 #define B2055_C1_RX_TXBBRCAL 0x79 /* Core 1 RX TX BB RCAL */
130 #define B2055_C1_TX_RF_SPGA 0x7A /* Core 1 TX RF SGM PGA */
131 #define B2055_C1_TX_RF_SPAD 0x7B /* Core 1 TX RF SGM PAD */
132 #define B2055_C1_TX_RF_CNTPGA1 0x7C /* Core 1 TX RF counter PGA 1 */
133 #define B2055_C1_TX_RF_CNTPAD1 0x7D /* Core 1 TX RF counter PAD 1 */
134 #define B2055_C1_TX_RF_PGAIDAC 0x7E /* Core 1 TX RF PGA IDAC */
135 #define B2055_C1_TX_PGAPADTN 0x7F /* Core 1 TX PGA PAD TN */
136 #define B2055_C1_TX_PADIDAC1 0x80 /* Core 1 TX PAD IDAC 1 */
137 #define B2055_C1_TX_PADIDAC2 0x81 /* Core 1 TX PAD IDAC 2 */
138 #define B2055_C1_TX_MXBGTRIM 0x82 /* Core 1 TX MX B/G TRIM */
139 #define B2055_C1_TX_RF_RCAL 0x83 /* Core 1 TX RF RCAL */
140 #define B2055_C1_TX_RF_PADTSSI1 0x84 /* Core 1 TX RF PAD TSSI1 */
141 #define B2055_C1_TX_RF_PADTSSI2 0x85 /* Core 1 TX RF PAD TSSI2 */
142 #define B2055_C1_TX_RF_SPARE 0x86 /* Core 1 TX RF spare */
143 #define B2055_C1_TX_RF_IQCAL1 0x87 /* Core 1 TX RF I/Q CAL 1 */
144 #define B2055_C1_TX_RF_IQCAL2 0x88 /* Core 1 TX RF I/Q CAL 2 */
147 #define B2055_C1_TX_VOSCNCL 0x8B /* Core 1 TX VOS CNCL */
148 #define B2055_C1_TX_LPF_MXGMIDAC 0x8C /* Core 1 TX LPF MXGM IDAC */
149 #define B2055_C1_TX_BB_MXGM 0x8D /* Core 1 TX BB MXGM */
176 #define B2055_C2_RX_TXBBRCAL 0xA8 /* Core 2 RX TX BB RCAL */
177 #define B2055_C2_TX_RF_SPGA 0xA9 /* Core 2 TX RF SGM PGA */
178 #define B2055_C2_TX_RF_SPAD 0xAA /* Core 2 TX RF SGM PAD */
179 #define B2055_C2_TX_RF_CNTPGA1 0xAB /* Core 2 TX RF counter PGA 1 */
180 #define B2055_C2_TX_RF_CNTPAD1 0xAC /* Core 2 TX RF counter PAD 1 */
181 #define B2055_C2_TX_RF_PGAIDAC 0xAD /* Core 2 TX RF PGA IDAC */
182 #define B2055_C2_TX_PGAPADTN 0xAE /* Core 2 TX PGA PAD TN */
183 #define B2055_C2_TX_PADIDAC1 0xAF /* Core 2 TX PAD IDAC 1 */
184 #define B2055_C2_TX_PADIDAC2 0xB0 /* Core 2 TX PAD IDAC 2 */
185 #define B2055_C2_TX_MXBGTRIM 0xB1 /* Core 2 TX MX B/G TRIM */
186 #define B2055_C2_TX_RF_RCAL 0xB2 /* Core 2 TX RF RCAL */
187 #define B2055_C2_TX_RF_PADTSSI1 0xB3 /* Core 2 TX RF PAD TSSI1 */
188 #define B2055_C2_TX_RF_PADTSSI2 0xB4 /* Core 2 TX RF PAD TSSI2 */
189 #define B2055_C2_TX_RF_SPARE 0xB5 /* Core 2 TX RF spare */
190 #define B2055_C2_TX_RF_IQCAL1 0xB6 /* Core 2 TX RF I/Q CAL 1 */
191 #define B2055_C2_TX_RF_IQCAL2 0xB7 /* Core 2 TX RF I/Q CAL 2 */
194 #define B2055_C2_TX_VOSCNCL 0xBA /* Core 2 TX VOS CNCL */
195 #define B2055_C2_TX_LPF_MXGMIDAC 0xBB /* Core 2 TX LPF MXGM IDAC */
196 #define B2055_C2_TX_BB_MXGM 0xBC /* Core 2 TX BB MXGM */