Lines Matching +full:0 +full:x186
64 N_RF_CTL_OVER_CMD_RXRF_PU = 0,
72 N_INTC_OVERRIDE_OFF = 0,
80 N_RSSI_W1 = 0,
90 N_RAIL_I = 0,
132 for (i = 0; i < 200; i++) { in b43_nphy_force_rf_sequence()
157 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 } in b43_nphy_rf_ctl_override_rev7()
172 for (i = 0; i < 2; i++) { in b43_nphy_rf_ctl_override_rev7()
180 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1; in b43_nphy_rf_ctl_override_rev7()
208 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
209 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
210 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
213 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
214 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
215 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
216 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
217 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
220 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
221 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
222 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); in b43_nphy_rf_ctl_override_one_to_many()
223 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); in b43_nphy_rf_ctl_override_one_to_many()
226 tmp = value & 0xFF; in b43_nphy_rf_ctl_override_one_to_many()
227 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
229 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
232 tmp = value & 0x7FFF; in b43_nphy_rf_ctl_override_one_to_many()
233 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
235 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); in b43_nphy_rf_ctl_override_one_to_many()
252 for (i = 0; i < 2; i++) { in b43_nphy_rf_ctl_override()
253 if (index == 0 || index == 16) { in b43_nphy_rf_ctl_override()
260 en_addr = B43_PHY_N((i == 0) ? in b43_nphy_rf_ctl_override()
262 val_addr = B43_PHY_N((i == 0) ? in b43_nphy_rf_ctl_override()
270 if (core == 0 || ((1 << i) & core)) { in b43_nphy_rf_ctl_override()
282 value = 0; in b43_nphy_rf_ctl_override()
287 for (i = 0; i < 2; i++) { in b43_nphy_rf_ctl_override()
300 addr = B43_PHY_N((i == 0) ? in b43_nphy_rf_ctl_override()
307 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rf_ctl_override()
311 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); in b43_nphy_rf_ctl_override()
325 for (core = 0; core < 2; core++) { in b43_nphy_rf_ctl_intc_override_rev7()
326 if ((core_sel == 1 && core != 0) || in b43_nphy_rf_ctl_intc_override_rev7()
330 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; in b43_nphy_rf_ctl_intc_override_rev7()
334 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override_rev7()
335 b43_phy_mask(dev, 0x2ff, ~0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
339 b43_phy_maskset(dev, reg, ~0xC0, value << 6); in b43_nphy_rf_ctl_intc_override_rev7()
340 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override_rev7()
342 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); in b43_nphy_rf_ctl_intc_override_rev7()
343 b43_phy_set(dev, 0x2ff, 0x2000); in b43_nphy_rf_ctl_intc_override_rev7()
344 b43_phy_set(dev, 0x2ff, 0x0001); in b43_nphy_rf_ctl_intc_override_rev7()
347 tmp = 0x0030; in b43_nphy_rf_ctl_intc_override_rev7()
353 b43_phy_set(dev, reg, 0x1000); in b43_nphy_rf_ctl_intc_override_rev7()
357 tmp = 0x0001; in b43_nphy_rf_ctl_intc_override_rev7()
358 tmp2 = 0x0004; in b43_nphy_rf_ctl_intc_override_rev7()
361 tmp = 0x0004; in b43_nphy_rf_ctl_intc_override_rev7()
362 tmp2 = 0x0001; in b43_nphy_rf_ctl_intc_override_rev7()
370 tmp = 0x0002; in b43_nphy_rf_ctl_intc_override_rev7()
371 tmp2 = 0x0008; in b43_nphy_rf_ctl_intc_override_rev7()
374 tmp = 0x0008; in b43_nphy_rf_ctl_intc_override_rev7()
375 tmp2 = 0x0002; in b43_nphy_rf_ctl_intc_override_rev7()
401 for (i = 0; i < 2; i++) { in b43_nphy_rf_ctl_intc_override()
405 reg = (i == 0) ? in b43_nphy_rf_ctl_intc_override()
407 b43_phy_set(dev, reg, 0x400); in b43_nphy_rf_ctl_intc_override()
411 b43_phy_write(dev, reg, 0); in b43_nphy_rf_ctl_intc_override()
417 0xFC3F, (value << 6)); in b43_nphy_rf_ctl_intc_override()
419 0xFFFE, 1); in b43_nphy_rf_ctl_intc_override()
422 for (j = 0; j < 100; j++) { in b43_nphy_rf_ctl_intc_override()
424 j = 0; in b43_nphy_rf_ctl_intc_override()
433 0xFFFE); in b43_nphy_rf_ctl_intc_override()
436 0xFC3F, (value << 6)); in b43_nphy_rf_ctl_intc_override()
438 0xFFFE, 1); in b43_nphy_rf_ctl_intc_override()
441 for (j = 0; j < 100; j++) { in b43_nphy_rf_ctl_intc_override()
443 j = 0; in b43_nphy_rf_ctl_intc_override()
452 0xFFFE); in b43_nphy_rf_ctl_intc_override()
457 tmp = 0x0020; in b43_nphy_rf_ctl_intc_override()
460 tmp = 0x0010; in b43_nphy_rf_ctl_intc_override()
467 tmp = 0x0001; in b43_nphy_rf_ctl_intc_override()
470 tmp = 0x0004; in b43_nphy_rf_ctl_intc_override()
477 tmp = 0x0002; in b43_nphy_rf_ctl_intc_override()
480 tmp = 0x0008; in b43_nphy_rf_ctl_intc_override()
497 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); in b43_nphy_write_clip_detection()
504 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); in b43_nphy_read_clip_detection()
521 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); in b43_nphy_classifier()
539 b43_phy_force_clock(dev, 0); in b43_nphy_reset_cca()
550 static const u16 clip[] = { 0xFFFF, 0xFFFF }; in b43_nphy_stay_in_carrier_search()
551 if (nphy->deaf_count++ == 0) { in b43_nphy_stay_in_carrier_search()
552 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); in b43_nphy_stay_in_carrier_search()
553 b43_nphy_classifier(dev, 0x7, in b43_nphy_stay_in_carrier_search()
560 if (--nphy->deaf_count == 0) { in b43_nphy_stay_in_carrier_search()
561 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); in b43_nphy_stay_in_carrier_search()
571 offset = b43_is_40mhz(dev) ? 0x159 : 0x154; in b43_nphy_read_lpf_ctl()
572 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; in b43_nphy_read_lpf_ctl()
592 gain[0] = 6; in b43_nphy_adjust_lna_gain_table()
596 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); in b43_nphy_adjust_lna_gain_table()
601 gain[0] = 0; in b43_nphy_adjust_lna_gain_table()
602 gain[1] = 0; in b43_nphy_adjust_lna_gain_table()
605 for (i = 0; i < 2; i++) { in b43_nphy_adjust_lna_gain_table()
607 data[0] = 19 + gain[i]; in b43_nphy_adjust_lna_gain_table()
612 data[0] = lna_gain[0] + gain[i]; in b43_nphy_adjust_lna_gain_table()
623 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); in b43_nphy_adjust_lna_gain_table()
628 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_adjust_lna_gain_table()
637 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; in b43_nphy_set_rf_sequence()
639 u16 offset2 = offset1 + 0x80; in b43_nphy_set_rf_sequence()
657 * Radio 0x2057
725 case 0 ... 4: in b43_radio_2057_setup()
728 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); in b43_radio_2057_setup()
729 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
730 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
731 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
733 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); in b43_radio_2057_setup()
734 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
735 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); in b43_radio_2057_setup()
736 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); in b43_radio_2057_setup()
740 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); in b43_radio_2057_setup()
741 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); in b43_radio_2057_setup()
743 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); in b43_radio_2057_setup()
744 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); in b43_radio_2057_setup()
751 0x3c); in b43_radio_2057_setup()
754 0x3c); in b43_radio_2057_setup()
759 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); in b43_radio_2057_setup()
760 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); in b43_radio_2057_setup()
761 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); in b43_radio_2057_setup()
762 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); in b43_radio_2057_setup()
767 u16 txmix2g_tune_boost_pu = 0; in b43_radio_2057_setup()
768 u16 pad2g_tune_pus = 0; in b43_radio_2057_setup()
773 txmix2g_tune_boost_pu = 0x0041; in b43_radio_2057_setup()
777 txmix2g_tune_boost_pu = 0x21; in b43_radio_2057_setup()
778 pad2g_tune_pus = 0x23; in b43_radio_2057_setup()
800 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); in b43_radio_2057_setup()
801 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); in b43_radio_2057_setup()
802 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); in b43_radio_2057_setup()
803 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); in b43_radio_2057_setup()
833 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) in b43_radio_2057_rcal()
835 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) in b43_radio_2057_rcal()
839 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) in b43_radio_2057_rcal()
840 b43_phy_write(dev, phy_to_store[i], 0); in b43_radio_2057_rcal()
841 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); in b43_radio_2057_rcal()
842 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); in b43_radio_2057_rcal()
843 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); in b43_radio_2057_rcal()
844 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); in b43_radio_2057_rcal()
845 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); in b43_radio_2057_rcal()
846 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); in b43_radio_2057_rcal()
850 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); in b43_radio_2057_rcal()
852 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
853 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); in b43_radio_2057_rcal()
856 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
857 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
858 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
859 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); in b43_radio_2057_rcal()
862 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); in b43_radio_2057_rcal()
864 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); in b43_radio_2057_rcal()
865 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); in b43_radio_2057_rcal()
866 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); in b43_radio_2057_rcal()
867 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); in b43_radio_2057_rcal()
872 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); in b43_radio_2057_rcal()
876 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); in b43_radio_2057_rcal()
880 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); in b43_radio_2057_rcal()
884 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rcal()
885 return 0; in b43_radio_2057_rcal()
887 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; in b43_radio_2057_rcal()
890 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); in b43_radio_2057_rcal()
893 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) in b43_radio_2057_rcal()
895 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) in b43_radio_2057_rcal()
899 case 0 ... 4: in b43_radio_2057_rcal()
901 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); in b43_radio_2057_rcal()
902 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, in b43_radio_2057_rcal()
906 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); in b43_radio_2057_rcal()
907 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); in b43_radio_2057_rcal()
910 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
913 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); in b43_radio_2057_rcal()
918 return tmp & 0x3e; in b43_radio_2057_rcal()
933 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
934 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); in b43_radio_2057_rccal()
936 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); in b43_radio_2057_rccal()
937 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); in b43_radio_2057_rccal()
939 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
942 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
945 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
947 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
952 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
953 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
955 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); in b43_radio_2057_rccal()
956 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); in b43_radio_2057_rccal()
958 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
962 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
966 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); in b43_radio_2057_rccal()
968 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
973 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
974 b43_radio_write(dev, R2057_RCCAL_X1, 0x28); in b43_radio_2057_rccal()
975 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); in b43_radio_2057_rccal()
977 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); in b43_radio_2057_rccal()
978 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); in b43_radio_2057_rccal()
979 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); in b43_radio_2057_rccal()
984 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); in b43_radio_2057_rccal()
988 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); in b43_radio_2057_rccal()
989 return 0; in b43_radio_2057_rccal()
993 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); in b43_radio_2057_rccal()
997 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
999 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); in b43_radio_2057_rccal()
1015 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); in b43_radio_2057_init_post()
1017 if (0) /* FIXME: Is this BCM43217 specific? */ in b43_radio_2057_init_post()
1018 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); in b43_radio_2057_init_post()
1020 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); in b43_radio_2057_init_post()
1021 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); in b43_radio_2057_init_post()
1023 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); in b43_radio_2057_init_post()
1024 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); in b43_radio_2057_init_post()
1030 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); in b43_radio_2057_init_post()
1042 * Radio 0x2056
1147 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1148 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1151 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); in b43_radio_2056_setup()
1152 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); in b43_radio_2056_setup()
1154 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); in b43_radio_2056_setup()
1155 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); in b43_radio_2056_setup()
1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); in b43_radio_2056_setup()
1161 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); in b43_radio_2056_setup()
1162 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); in b43_radio_2056_setup()
1163 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); in b43_radio_2056_setup()
1167 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); in b43_radio_2056_setup()
1168 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); in b43_radio_2056_setup()
1169 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); in b43_radio_2056_setup()
1170 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); in b43_radio_2056_setup()
1174 for (i = 0; i < 2; i++) { in b43_radio_2056_setup()
1178 offset | B2056_TX_PADG_IDAC, 0xcc); in b43_radio_2056_setup()
1182 bias = 0x40; in b43_radio_2056_setup()
1183 cbias = 0x45; in b43_radio_2056_setup()
1184 pag_boost = 0x5; in b43_radio_2056_setup()
1185 pgag_boost = 0x33; in b43_radio_2056_setup()
1186 mixg_boost = 0x55; in b43_radio_2056_setup()
1188 bias = 0x25; in b43_radio_2056_setup()
1189 cbias = 0x20; in b43_radio_2056_setup()
1191 bias = 0x2a; in b43_radio_2056_setup()
1192 cbias = 0x38; in b43_radio_2056_setup()
1194 pag_boost = 0x4; in b43_radio_2056_setup()
1195 pgag_boost = 0x03; in b43_radio_2056_setup()
1196 mixg_boost = 0x65; in b43_radio_2056_setup()
1198 padg_boost = 0x77; in b43_radio_2056_setup()
1222 bias = b43_is_40mhz(dev) ? 0x40 : 0x20; in b43_radio_2056_setup()
1231 0x30); in b43_radio_2056_setup()
1233 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); in b43_radio_2056_setup()
1238 paa_boost = 0xA; in b43_radio_2056_setup()
1239 pada_boost = 0x77; in b43_radio_2056_setup()
1240 pgaa_boost = 0xF; in b43_radio_2056_setup()
1241 mixa_boost = 0xF; in b43_radio_2056_setup()
1243 paa_boost = 0x8; in b43_radio_2056_setup()
1244 pada_boost = 0x77; in b43_radio_2056_setup()
1245 pgaa_boost = 0xFB; in b43_radio_2056_setup()
1246 mixa_boost = 0xF; in b43_radio_2056_setup()
1248 paa_boost = 0x0; in b43_radio_2056_setup()
1249 pada_boost = 0x77; in b43_radio_2056_setup()
1250 pgaa_boost = 0xB; in b43_radio_2056_setup()
1251 mixa_boost = 0xF; in b43_radio_2056_setup()
1253 paa_boost = 0x0; in b43_radio_2056_setup()
1254 pada_boost = 0x77; in b43_radio_2056_setup()
1259 mixa_boost = 0xF; in b43_radio_2056_setup()
1262 cbias = is_pkg_fab_smic ? 0x35 : 0x30; in b43_radio_2056_setup()
1264 for (i = 0; i < 2; i++) { in b43_radio_2056_setup()
1276 offset | B2056_TX_TXSPARE1, 0x30); in b43_radio_2056_setup()
1278 offset | B2056_TX_PA_SPARE2, 0xee); in b43_radio_2056_setup()
1280 offset | B2056_TX_PADA_CASCBIAS, 0x03); in b43_radio_2056_setup()
1282 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30); in b43_radio_2056_setup()
1284 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30); in b43_radio_2056_setup()
1292 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); in b43_radio_2056_setup()
1293 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1294 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); in b43_radio_2056_setup()
1295 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); in b43_radio_2056_setup()
1296 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); in b43_radio_2056_setup()
1306 return 0; in b43_radio_2056_rcal()
1309 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); in b43_radio_2056_rcal()
1312 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1314 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); in b43_radio_2056_rcal()
1316 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, in b43_radio_2056_rcal()
1319 return 0; in b43_radio_2056_rcal()
1322 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); in b43_radio_2056_rcal()
1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); in b43_radio_2056_rcal()
1328 return tmp & 0x1f; in b43_radio_2056_rcal()
1346 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); in b43_radio_init2056_post()
1347 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); in b43_radio_init2056_post()
1348 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); in b43_radio_init2056_post()
1350 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); in b43_radio_init2056_post()
1351 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); in b43_radio_init2056_post()
1352 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); in b43_radio_init2056_post()
1364 b2056_upload_inittabs(dev, 0, 0); in b43_radio_init2056()
1369 * Radio 0x2055
1417 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); in b43_radio_2055_setup()
1418 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); in b43_radio_2055_setup()
1420 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); in b43_radio_2055_setup()
1444 && dev->dev->board_rev >= 0x41); in b43_radio_init2055_post()
1449 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); in b43_radio_init2055_post()
1451 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1452 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); in b43_radio_init2055_post()
1454 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); in b43_radio_init2055_post()
1455 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); in b43_radio_init2055_post()
1456 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); in b43_radio_init2055_post()
1457 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); in b43_radio_init2055_post()
1458 b43_radio_set(dev, B2055_CAL_MISC, 0x1); in b43_radio_init2055_post()
1460 b43_radio_set(dev, B2055_CAL_MISC, 0x40); in b43_radio_init2055_post()
1461 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) in b43_radio_init2055_post()
1463 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); in b43_radio_init2055_post()
1465 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1466 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); in b43_radio_init2055_post()
1467 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1468 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); in b43_radio_init2055_post()
1469 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1470 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); in b43_radio_init2055_post()
1472 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1473 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); in b43_radio_init2055_post()
1475 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1476 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); in b43_radio_init2055_post()
1490 b2055_upload_inittab(dev, 0, 0); in b43_radio_init2055()
1493 b2055_upload_inittab(dev, ghz5, 0); in b43_radio_init2055()
1517 for (i = 0; i < len; i++) { in b43_nphy_load_samples()
1518 data[i] = (samples[i].i & 0x3FF << 10); in b43_nphy_load_samples()
1519 data[i] |= samples[i].q & 0x3FF; in b43_nphy_load_samples()
1521 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); in b43_nphy_load_samples()
1525 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_load_samples()
1526 return 0; in b43_nphy_load_samples()
1555 return 0; in b43_nphy_gen_load_samples()
1558 angle = 0; in b43_nphy_gen_load_samples()
1560 for (i = 0; i < len; i++) { in b43_nphy_gen_load_samples()
1569 return (i < 0) ? 0 : len; in b43_nphy_gen_load_samples()
1588 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; in b43_nphy_run_samples()
1589 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; in b43_nphy_run_samples()
1594 u16 value = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_run_samples()
1596 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, in b43_nphy_run_samples()
1597 0, false, 1); in b43_nphy_run_samples()
1599 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, in b43_nphy_run_samples()
1600 0, false, 1); in b43_nphy_run_samples()
1605 if ((nphy->bb_mult_save & 0x80000000) == 0) { in b43_nphy_run_samples()
1607 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; in b43_nphy_run_samples()
1611 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; in b43_nphy_run_samples()
1617 if (loops != 0xFFFF) in b43_nphy_run_samples()
1628 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_run_samples()
1629 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); in b43_nphy_run_samples()
1634 for (i = 0; i < 100; i++) { in b43_nphy_run_samples()
1636 i = 0; in b43_nphy_run_samples()
1664 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); in b43_nphy_scale_offset_rssi()
1744 if (code == 0) { in b43_nphy_rev3_rssi_select()
1745 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); in b43_nphy_rev3_rssi_select()
1746 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); in b43_nphy_rev3_rssi_select()
1747 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); in b43_nphy_rev3_rssi_select()
1748 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); in b43_nphy_rev3_rssi_select()
1749 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); in b43_nphy_rev3_rssi_select()
1750 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); in b43_nphy_rev3_rssi_select()
1751 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); in b43_nphy_rev3_rssi_select()
1752 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); in b43_nphy_rev3_rssi_select()
1754 for (i = 0; i < 2; i++) { in b43_nphy_rev3_rssi_select()
1758 reg = (i == 0) ? in b43_nphy_rev3_rssi_select()
1760 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); in b43_nphy_rev3_rssi_select()
1765 reg = (i == 0) ? in b43_nphy_rev3_rssi_select()
1768 b43_phy_maskset(dev, reg, 0xFCFF, 0); in b43_nphy_rev3_rssi_select()
1770 reg = (i == 0) ? in b43_nphy_rev3_rssi_select()
1773 b43_phy_maskset(dev, reg, 0xFFC3, 0); in b43_nphy_rev3_rssi_select()
1783 reg = (i == 0) ? in b43_nphy_rev3_rssi_select()
1786 b43_phy_set(dev, reg, 0x0020); in b43_nphy_rev3_rssi_select()
1789 val = 0x0100; in b43_nphy_rev3_rssi_select()
1791 val = 0x0200; in b43_nphy_rev3_rssi_select()
1793 val = 0x0300; in b43_nphy_rev3_rssi_select()
1795 reg = (i == 0) ? in b43_nphy_rev3_rssi_select()
1799 b43_phy_maskset(dev, reg, 0xFCFF, val); in b43_nphy_rev3_rssi_select()
1800 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); in b43_nphy_rev3_rssi_select()
1809 val = (band == NL80211_BAND_5GHZ) ? 0xC : 0xE; in b43_nphy_rev3_rssi_select()
1811 val = 0x11; in b43_nphy_rev3_rssi_select()
1812 reg = (i == 0) ? B2056_TX0 : B2056_TX1; in b43_nphy_rev3_rssi_select()
1817 reg = (i == 0) ? in b43_nphy_rev3_rssi_select()
1820 b43_phy_set(dev, reg, 0x0200); in b43_nphy_rev3_rssi_select()
1837 val = 0; in b43_nphy_rev2_rssi_select()
1851 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1852 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); in b43_nphy_rev2_rssi_select()
1855 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, in b43_nphy_rev2_rssi_select()
1857 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, in b43_nphy_rev2_rssi_select()
1861 if (code == 0) { in b43_nphy_rev2_rssi_select()
1862 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); in b43_nphy_rev2_rssi_select()
1868 ~(0x1 << 12 | in b43_nphy_rev2_rssi_select()
1869 0x1 << 5 | in b43_nphy_rev2_rssi_select()
1870 0x1 << 1 | in b43_nphy_rev2_rssi_select()
1871 0x1)); in b43_nphy_rev2_rssi_select()
1875 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1878 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); in b43_nphy_rev2_rssi_select()
1886 (0x1 << 12 | in b43_nphy_rev2_rssi_select()
1887 0x1 << 5 | in b43_nphy_rev2_rssi_select()
1888 0x1 << 1 | in b43_nphy_rev2_rssi_select()
1889 0x1)); in b43_nphy_rev2_rssi_select()
1893 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev2_rssi_select()
1915 for (i = 0; i < 2; i++) { in b43_nphy_set_rssi_2055_vcm()
1917 if (i == 0) { in b43_nphy_set_rssi_2055_vcm()
1919 0xFC, buf[0]); in b43_nphy_set_rssi_2055_vcm()
1921 0xFC, buf[1]); in b43_nphy_set_rssi_2055_vcm()
1924 0xFC, buf[2 * i]); in b43_nphy_set_rssi_2055_vcm()
1926 0xFC, buf[2 * i + 1]); in b43_nphy_set_rssi_2055_vcm()
1929 if (i == 0) in b43_nphy_set_rssi_2055_vcm()
1931 0xF3, buf[0] << 2); in b43_nphy_set_rssi_2055_vcm()
1934 0xF3, buf[2 * i + 1] << 2); in b43_nphy_set_rssi_2055_vcm()
1951 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1961 save_regs_phy[8] = 0; in b43_nphy_poll_rssi()
1963 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_poll_rssi()
1970 save_regs_phy[7] = 0; in b43_nphy_poll_rssi()
1971 save_regs_phy[8] = 0; in b43_nphy_poll_rssi()
1981 for (i = 0; i < 4; i++) in b43_nphy_poll_rssi()
1982 buf[i] = 0; in b43_nphy_poll_rssi()
1984 for (i = 0; i < nsamp; i++) { in b43_nphy_poll_rssi()
1986 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); in b43_nphy_poll_rssi()
1989 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); in b43_nphy_poll_rssi()
1993 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; in b43_nphy_poll_rssi()
1994 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; in b43_nphy_poll_rssi()
1995 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; in b43_nphy_poll_rssi()
1996 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; in b43_nphy_poll_rssi()
1998 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | in b43_nphy_poll_rssi()
1999 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); in b43_nphy_poll_rssi()
2005 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2016 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); in b43_nphy_poll_rssi()
2051 0x2ff, in b43_nphy_rev3_rssi_cal()
2065 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; in b43_nphy_rev3_rssi_cal()
2067 u8 vcm_final = 0; in b43_nphy_rev3_rssi_cal()
2089 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev3_rssi_cal()
2094 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev3_rssi_cal()
2096 for (i = 0; i < regs_amount; i++) in b43_nphy_rev3_rssi_cal()
2099 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); in b43_nphy_rev3_rssi_cal()
2105 0, 0, false); in b43_nphy_rev3_rssi_cal()
2108 1, 0, false); in b43_nphy_rev3_rssi_cal()
2109 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2110 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); in b43_nphy_rev3_rssi_cal()
2112 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2113 0); in b43_nphy_rev3_rssi_cal()
2114 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2115 0); in b43_nphy_rev3_rssi_cal()
2117 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, in b43_nphy_rev3_rssi_cal()
2118 0); in b43_nphy_rev3_rssi_cal()
2119 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, in b43_nphy_rev3_rssi_cal()
2120 0); in b43_nphy_rev3_rssi_cal()
2123 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2124 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2125 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2126 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2128 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2129 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2131 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); in b43_nphy_rev3_rssi_cal()
2132 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); in b43_nphy_rev3_rssi_cal()
2137 for (core = 0; core < 2; core++) { in b43_nphy_rev3_rssi_cal()
2141 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, in b43_nphy_rev3_rssi_cal()
2143 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, in b43_nphy_rev3_rssi_cal()
2147 for (vcm = 0; vcm < 8; vcm++) { in b43_nphy_rev3_rssi_cal()
2155 0xE3, vcm << 2); in b43_nphy_rev3_rssi_cal()
2160 for (i = 0; i < 4; i += 2) { in b43_nphy_rev3_rssi_cal()
2162 s32 mind = 0x100000; in b43_nphy_rev3_rssi_cal()
2164 u8 minvcm = 0; in b43_nphy_rev3_rssi_cal()
2167 for (vcm = 0; vcm < 8; vcm++) { in b43_nphy_rev3_rssi_cal()
2189 0xE3, vcm_final << 2); in b43_nphy_rev3_rssi_cal()
2191 for (i = 0; i < 4; i++) { in b43_nphy_rev3_rssi_cal()
2195 if (offset[i] < 0) in b43_nphy_rev3_rssi_cal()
2201 b43_nphy_scale_offset_rssi(dev, 0, offset[i], in b43_nphy_rev3_rssi_cal()
2202 (i / 2 == 0) ? 1 : 2, in b43_nphy_rev3_rssi_cal()
2203 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q, in b43_nphy_rev3_rssi_cal()
2208 for (core = 0; core < 2; core++) { in b43_nphy_rev3_rssi_cal()
2211 for (i = 0; i < 2; i++) { in b43_nphy_rev3_rssi_cal()
2212 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2214 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, in b43_nphy_rev3_rssi_cal()
2217 for (j = 0; j < 4; j++) { in b43_nphy_rev3_rssi_cal()
2220 if (offset[j] < 0) in b43_nphy_rev3_rssi_cal()
2224 b43_nphy_scale_offset_rssi(dev, 0, in b43_nphy_rev3_rssi_cal()
2231 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); in b43_nphy_rev3_rssi_cal()
2236 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); in b43_nphy_rev3_rssi_cal()
2238 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); in b43_nphy_rev3_rssi_cal()
2240 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); in b43_nphy_rev3_rssi_cal()
2242 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); in b43_nphy_rev3_rssi_cal()
2244 for (i = 0; i < regs_amount; i++) in b43_nphy_rev3_rssi_cal()
2256 rssical_radio_regs[0] = b43_radio_read(dev, in b43_nphy_rev3_rssi_cal()
2261 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | in b43_nphy_rev3_rssi_cal()
2266 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); in b43_nphy_rev3_rssi_cal()
2305 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; in b43_nphy_rev2_rssi_cal()
2312 code = 0; in b43_nphy_rev2_rssi_cal()
2322 class = b43_nphy_classifier(dev, 0, 0); in b43_nphy_rev2_rssi_cal()
2328 override = 0x140; in b43_nphy_rev2_rssi_cal()
2330 override = 0x110; in b43_nphy_rev2_rssi_cal()
2332 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); in b43_nphy_rev2_rssi_cal()
2333 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); in b43_nphy_rev2_rssi_cal()
2342 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2343 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; in b43_nphy_rev2_rssi_cal()
2344 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2345 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); in b43_nphy_rev2_rssi_cal()
2346 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2347 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; in b43_nphy_rev2_rssi_cal()
2350 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); in b43_nphy_rev2_rssi_cal()
2351 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); in b43_nphy_rev2_rssi_cal()
2353 for (vcm = 0; vcm < 4; vcm++) { in b43_nphy_rev2_rssi_cal()
2355 for (j = 0; j < 4; j++) in b43_nphy_rev2_rssi_cal()
2361 for (j = 0; j < 2; j++) in b43_nphy_rev2_rssi_cal()
2366 for (i = 0; i < 4; i++) { in b43_nphy_rev2_rssi_cal()
2367 s32 mind = 0x100000; in b43_nphy_rev2_rssi_cal()
2368 u8 minvcm = 0; in b43_nphy_rev2_rssi_cal()
2371 for (vcm = 0; vcm < 4; vcm++) { in b43_nphy_rev2_rssi_cal()
2392 for (i = 0; i < 4; i++) { in b43_nphy_rev2_rssi_cal()
2395 if (offset[i] < 0) in b43_nphy_rev2_rssi_cal()
2406 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, in b43_nphy_rev2_rssi_cal()
2410 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); in b43_nphy_rev2_rssi_cal()
2411 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); in b43_nphy_rev2_rssi_cal()
2440 b43_nphy_rssi_select(dev, 0, type); in b43_nphy_rev2_rssi_cal()
2442 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); in b43_nphy_rev2_rssi_cal()
2443 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); in b43_nphy_rev2_rssi_cal()
2493 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; in b43_nphy_gain_ctl_workarounds_rev3()
2494 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; in b43_nphy_gain_ctl_workarounds_rev3()
2503 rssi_gain = 0x90; in b43_nphy_gain_ctl_workarounds_rev3()
2505 rssi_gain = 0x50; in b43_nphy_gain_ctl_workarounds_rev3()
2507 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); in b43_nphy_gain_ctl_workarounds_rev3()
2514 0x17); in b43_nphy_gain_ctl_workarounds_rev3()
2516 0x17); in b43_nphy_gain_ctl_workarounds_rev3()
2517 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2518 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); in b43_nphy_gain_ctl_workarounds_rev3()
2519 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2520 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); in b43_nphy_gain_ctl_workarounds_rev3()
2526 0x17); in b43_nphy_gain_ctl_workarounds_rev3()
2528 0x17); in b43_nphy_gain_ctl_workarounds_rev3()
2529 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2530 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); in b43_nphy_gain_ctl_workarounds_rev3()
2532 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2534 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2536 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); in b43_nphy_gain_ctl_workarounds_rev3()
2540 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2541 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); in b43_nphy_gain_ctl_workarounds_rev3()
2542 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2543 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); in b43_nphy_gain_ctl_workarounds_rev3()
2548 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, in b43_nphy_gain_ctl_workarounds_rev3()
2558 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); in b43_nphy_gain_ctl_workarounds_rev3()
2559 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); in b43_nphy_gain_ctl_workarounds_rev3()
2560 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); in b43_nphy_gain_ctl_workarounds_rev3()
2567 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev3()
2585 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2586 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); in b43_nphy_gain_ctl_workarounds_rev1_2()
2590 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2591 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); in b43_nphy_gain_ctl_workarounds_rev1_2()
2592 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2593 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); in b43_nphy_gain_ctl_workarounds_rev1_2()
2604 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2606 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2608 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2610 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2613 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); in b43_nphy_gain_ctl_workarounds_rev1_2()
2631 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2633 for (i = 0; i < 4; i++) in b43_nphy_gain_ctl_workarounds_rev1_2()
2634 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); in b43_nphy_gain_ctl_workarounds_rev1_2()
2639 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); in b43_nphy_gain_ctl_workarounds_rev1_2()
2640 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2641 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2642 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2643 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2645 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); in b43_nphy_gain_ctl_workarounds_rev1_2()
2646 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); in b43_nphy_gain_ctl_workarounds_rev1_2()
2647 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2648 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2649 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); in b43_nphy_gain_ctl_workarounds_rev1_2()
2651 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); in b43_nphy_gain_ctl_workarounds_rev1_2()
2653 for (i = 0; i < 4; i++) in b43_nphy_gain_ctl_workarounds_rev1_2()
2655 (code << 8 | 0x74)); in b43_nphy_gain_ctl_workarounds_rev1_2()
2659 for (i = 0; i < 4; i++) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2661 (0x0400 * i) + 0x0020); in b43_nphy_gain_ctl_workarounds_rev1_2()
2662 for (j = 0; j < 21; j++) { in b43_nphy_gain_ctl_workarounds_rev1_2()
2672 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, in b43_nphy_gain_ctl_workarounds_rev1_2()
2673 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); in b43_nphy_gain_ctl_workarounds_rev1_2()
2676 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); in b43_nphy_gain_ctl_workarounds_rev1_2()
2701 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, in b43_nphy_workarounds_rev7plus()
2702 0x1F }; in b43_nphy_workarounds_rev7plus()
2705 static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f }; in b43_nphy_workarounds_rev7plus()
2706 u8 ntab7_138_146[] = { 0x11, 0x11 }; in b43_nphy_workarounds_rev7plus()
2707 u8 ntab7_133[] = { 0x77, 0x11, 0x11 }; in b43_nphy_workarounds_rev7plus()
2723 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev7plus()
2724 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); in b43_nphy_workarounds_rev7plus()
2725 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev7plus()
2726 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); in b43_nphy_workarounds_rev7plus()
2727 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); in b43_nphy_workarounds_rev7plus()
2728 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev7plus()
2731 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); in b43_nphy_workarounds_rev7plus()
2732 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); in b43_nphy_workarounds_rev7plus()
2733 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); in b43_nphy_workarounds_rev7plus()
2734 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); in b43_nphy_workarounds_rev7plus()
2735 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); in b43_nphy_workarounds_rev7plus()
2736 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); in b43_nphy_workarounds_rev7plus()
2737 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); in b43_nphy_workarounds_rev7plus()
2738 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); in b43_nphy_workarounds_rev7plus()
2739 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); in b43_nphy_workarounds_rev7plus()
2740 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); in b43_nphy_workarounds_rev7plus()
2741 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); in b43_nphy_workarounds_rev7plus()
2742 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2743 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2744 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2745 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2746 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); in b43_nphy_workarounds_rev7plus()
2747 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); in b43_nphy_workarounds_rev7plus()
2751 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); in b43_nphy_workarounds_rev7plus()
2752 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); in b43_nphy_workarounds_rev7plus()
2754 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); in b43_nphy_workarounds_rev7plus()
2755 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); in b43_nphy_workarounds_rev7plus()
2759 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); in b43_nphy_workarounds_rev7plus()
2761 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); in b43_nphy_workarounds_rev7plus()
2763 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); in b43_nphy_workarounds_rev7plus()
2764 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); in b43_nphy_workarounds_rev7plus()
2765 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev7plus()
2766 tmp32 &= 0xffffff; in b43_nphy_workarounds_rev7plus()
2767 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev7plus()
2768 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2769 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); in b43_nphy_workarounds_rev7plus()
2774 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev7plus()
2777 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2778 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); in b43_nphy_workarounds_rev7plus()
2780 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2781 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2782 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2783 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); in b43_nphy_workarounds_rev7plus()
2794 /* Check radio version (to be 0) by PHY rev for now */ in b43_nphy_workarounds_rev7plus()
2796 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2801 scap_val_11n_40[core] = 0xc; in b43_nphy_workarounds_rev7plus()
2802 bcap_val_11n_40[core] = 0xc; in b43_nphy_workarounds_rev7plus()
2813 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2819 scap_val_11n_20[core] = 0xc; in b43_nphy_workarounds_rev7plus()
2820 bcap_val_11n_20[core] = 0xc; in b43_nphy_workarounds_rev7plus()
2821 scap_val_11n_40[core] = 0xa; in b43_nphy_workarounds_rev7plus()
2822 bcap_val_11n_40[core] = 0xa; in b43_nphy_workarounds_rev7plus()
2824 scap_val_11n_20[core] = 0x14; in b43_nphy_workarounds_rev7plus()
2825 bcap_val_11n_20[core] = 0x14; in b43_nphy_workarounds_rev7plus()
2826 scap_val_11n_40[core] = 0xf; in b43_nphy_workarounds_rev7plus()
2827 bcap_val_11n_40[core] = 0xf; in b43_nphy_workarounds_rev7plus()
2834 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2861 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2867 bcap_val_11n_20[0] = bcap_val + 20; in b43_nphy_workarounds_rev7plus()
2868 scap_val_11n_20[0] = scap_val + 20; in b43_nphy_workarounds_rev7plus()
2869 lpf_ofdm_20mhz[0] = 3; in b43_nphy_workarounds_rev7plus()
2875 bcap_val_11n_40[0] = bcap_val + 20; in b43_nphy_workarounds_rev7plus()
2876 scap_val_11n_40[0] = scap_val + 20; in b43_nphy_workarounds_rev7plus()
2877 lpf_ofdm_40mhz[0] = 4; in b43_nphy_workarounds_rev7plus()
2888 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2893 scap_val_11n_20[core] = 0x11; in b43_nphy_workarounds_rev7plus()
2894 scap_val_11n_40[core] = 0x11; in b43_nphy_workarounds_rev7plus()
2895 bcap_val_11n_20[core] = 0x13; in b43_nphy_workarounds_rev7plus()
2896 bcap_val_11n_40[core] = 0x13; in b43_nphy_workarounds_rev7plus()
2906 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2907 bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f); in b43_nphy_workarounds_rev7plus()
2908 scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f); in b43_nphy_workarounds_rev7plus()
2909 bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f); in b43_nphy_workarounds_rev7plus()
2910 scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f); in b43_nphy_workarounds_rev7plus()
2911 bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f); in b43_nphy_workarounds_rev7plus()
2912 scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f); in b43_nphy_workarounds_rev7plus()
2928 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2929 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), in b43_nphy_workarounds_rev7plus()
2931 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), in b43_nphy_workarounds_rev7plus()
2933 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), in b43_nphy_workarounds_rev7plus()
2935 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), in b43_nphy_workarounds_rev7plus()
2937 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), in b43_nphy_workarounds_rev7plus()
2939 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), in b43_nphy_workarounds_rev7plus()
2941 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), in b43_nphy_workarounds_rev7plus()
2943 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), in b43_nphy_workarounds_rev7plus()
2948 b43_phy_write(dev, 0x32F, 0x3); in b43_nphy_workarounds_rev7plus()
2951 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); in b43_nphy_workarounds_rev7plus()
2956 b43_radio_write(dev, 0x5, 0x05); in b43_nphy_workarounds_rev7plus()
2957 b43_radio_write(dev, 0x6, 0x30); in b43_nphy_workarounds_rev7plus()
2958 b43_radio_write(dev, 0x7, 0x00); in b43_nphy_workarounds_rev7plus()
2959 b43_radio_set(dev, 0x4f, 0x1); in b43_nphy_workarounds_rev7plus()
2960 b43_radio_set(dev, 0xd4, 0x1); in b43_nphy_workarounds_rev7plus()
2961 bias = 0x1f; in b43_nphy_workarounds_rev7plus()
2962 conv = 0x6f; in b43_nphy_workarounds_rev7plus()
2963 filt = 0xaa; in b43_nphy_workarounds_rev7plus()
2965 bias = 0x2b; in b43_nphy_workarounds_rev7plus()
2966 conv = 0x7f; in b43_nphy_workarounds_rev7plus()
2967 filt = 0xee; in b43_nphy_workarounds_rev7plus()
2970 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2971 if (core == 0) { in b43_nphy_workarounds_rev7plus()
2972 b43_radio_write(dev, 0x5F, bias); in b43_nphy_workarounds_rev7plus()
2973 b43_radio_write(dev, 0x64, conv); in b43_nphy_workarounds_rev7plus()
2974 b43_radio_write(dev, 0x66, filt); in b43_nphy_workarounds_rev7plus()
2976 b43_radio_write(dev, 0xE8, bias); in b43_nphy_workarounds_rev7plus()
2977 b43_radio_write(dev, 0xE9, conv); in b43_nphy_workarounds_rev7plus()
2978 b43_radio_write(dev, 0xEB, filt); in b43_nphy_workarounds_rev7plus()
2988 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
2989 if (core == 0) in b43_nphy_workarounds_rev7plus()
2990 b43_radio_write(dev, 0x51, in b43_nphy_workarounds_rev7plus()
2991 0x7f); in b43_nphy_workarounds_rev7plus()
2993 b43_radio_write(dev, 0xd6, in b43_nphy_workarounds_rev7plus()
2994 0x7f); in b43_nphy_workarounds_rev7plus()
2999 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
3000 if (core == 0) { in b43_nphy_workarounds_rev7plus()
3001 b43_radio_write(dev, 0x64, in b43_nphy_workarounds_rev7plus()
3002 0x13); in b43_nphy_workarounds_rev7plus()
3003 b43_radio_write(dev, 0x5F, in b43_nphy_workarounds_rev7plus()
3004 0x1F); in b43_nphy_workarounds_rev7plus()
3005 b43_radio_write(dev, 0x66, in b43_nphy_workarounds_rev7plus()
3006 0xEE); in b43_nphy_workarounds_rev7plus()
3007 b43_radio_write(dev, 0x59, in b43_nphy_workarounds_rev7plus()
3008 0x8A); in b43_nphy_workarounds_rev7plus()
3009 b43_radio_write(dev, 0x80, in b43_nphy_workarounds_rev7plus()
3010 0x3E); in b43_nphy_workarounds_rev7plus()
3012 b43_radio_write(dev, 0x69, in b43_nphy_workarounds_rev7plus()
3013 0x13); in b43_nphy_workarounds_rev7plus()
3014 b43_radio_write(dev, 0xE8, in b43_nphy_workarounds_rev7plus()
3015 0x1F); in b43_nphy_workarounds_rev7plus()
3016 b43_radio_write(dev, 0xEB, in b43_nphy_workarounds_rev7plus()
3017 0xEE); in b43_nphy_workarounds_rev7plus()
3018 b43_radio_write(dev, 0xDE, in b43_nphy_workarounds_rev7plus()
3019 0x8A); in b43_nphy_workarounds_rev7plus()
3020 b43_radio_write(dev, 0x105, in b43_nphy_workarounds_rev7plus()
3021 0x3E); in b43_nphy_workarounds_rev7plus()
3028 b43_radio_write(dev, 0x5F, 0x14); in b43_nphy_workarounds_rev7plus()
3029 b43_radio_write(dev, 0xE8, 0x12); in b43_nphy_workarounds_rev7plus()
3031 b43_radio_write(dev, 0x5F, 0x16); in b43_nphy_workarounds_rev7plus()
3032 b43_radio_write(dev, 0xE8, 0x16); in b43_nphy_workarounds_rev7plus()
3036 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
3037 int o = core ? 0x85 : 0; in b43_nphy_workarounds_rev7plus()
3039 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); in b43_nphy_workarounds_rev7plus()
3040 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); in b43_nphy_workarounds_rev7plus()
3041 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); in b43_nphy_workarounds_rev7plus()
3042 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); in b43_nphy_workarounds_rev7plus()
3043 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); in b43_nphy_workarounds_rev7plus()
3044 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); in b43_nphy_workarounds_rev7plus()
3045 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); in b43_nphy_workarounds_rev7plus()
3046 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); in b43_nphy_workarounds_rev7plus()
3054 b43_radio_write(dev, 0x7D, 0xFF); in b43_nphy_workarounds_rev7plus()
3055 b43_radio_write(dev, 0xFE, 0xFF); in b43_nphy_workarounds_rev7plus()
3060 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
3061 if (core == 0) { in b43_nphy_workarounds_rev7plus()
3062 b43_radio_write(dev, 0x5c, 0x61); in b43_nphy_workarounds_rev7plus()
3063 b43_radio_write(dev, 0x51, 0x70); in b43_nphy_workarounds_rev7plus()
3065 b43_radio_write(dev, 0xe1, 0x61); in b43_nphy_workarounds_rev7plus()
3066 b43_radio_write(dev, 0xd6, 0x70); in b43_nphy_workarounds_rev7plus()
3073 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); in b43_nphy_workarounds_rev7plus()
3074 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); in b43_nphy_workarounds_rev7plus()
3075 for (core = 0; core < 2; core++) { in b43_nphy_workarounds_rev7plus()
3076 if (core == 0) { in b43_nphy_workarounds_rev7plus()
3077 b43_radio_write(dev, 0x1a1, 0x00); in b43_nphy_workarounds_rev7plus()
3078 b43_radio_write(dev, 0x1a2, 0x3f); in b43_nphy_workarounds_rev7plus()
3079 b43_radio_write(dev, 0x1a6, 0x3f); in b43_nphy_workarounds_rev7plus()
3081 b43_radio_write(dev, 0x1a7, 0x00); in b43_nphy_workarounds_rev7plus()
3082 b43_radio_write(dev, 0x1ab, 0x3f); in b43_nphy_workarounds_rev7plus()
3083 b43_radio_write(dev, 0x1ac, 0x3f); in b43_nphy_workarounds_rev7plus()
3087 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); in b43_nphy_workarounds_rev7plus()
3088 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); in b43_nphy_workarounds_rev7plus()
3089 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); in b43_nphy_workarounds_rev7plus()
3090 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); in b43_nphy_workarounds_rev7plus()
3092 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); in b43_nphy_workarounds_rev7plus()
3093 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); in b43_nphy_workarounds_rev7plus()
3094 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); in b43_nphy_workarounds_rev7plus()
3095 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); in b43_nphy_workarounds_rev7plus()
3096 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); in b43_nphy_workarounds_rev7plus()
3097 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); in b43_nphy_workarounds_rev7plus()
3099 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); in b43_nphy_workarounds_rev7plus()
3100 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); in b43_nphy_workarounds_rev7plus()
3101 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); in b43_nphy_workarounds_rev7plus()
3102 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); in b43_nphy_workarounds_rev7plus()
3105 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); in b43_nphy_workarounds_rev7plus()
3107 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); in b43_nphy_workarounds_rev7plus()
3108 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3109 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); in b43_nphy_workarounds_rev7plus()
3110 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); in b43_nphy_workarounds_rev7plus()
3111 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); in b43_nphy_workarounds_rev7plus()
3112 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); in b43_nphy_workarounds_rev7plus()
3113 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); in b43_nphy_workarounds_rev7plus()
3115 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3116 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3117 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3119 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); in b43_nphy_workarounds_rev7plus()
3120 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; in b43_nphy_workarounds_rev7plus()
3121 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); in b43_nphy_workarounds_rev7plus()
3126 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, in b43_nphy_workarounds_rev7plus()
3128 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, in b43_nphy_workarounds_rev7plus()
3130 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4, in b43_nphy_workarounds_rev7plus()
3132 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4, in b43_nphy_workarounds_rev7plus()
3143 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F }; in b43_nphy_workarounds_rev3plus()
3146 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, in b43_nphy_workarounds_rev3plus()
3147 0x1F }; in b43_nphy_workarounds_rev3plus()
3149 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; in b43_nphy_workarounds_rev3plus()
3153 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */ in b43_nphy_workarounds_rev3plus()
3154 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */ in b43_nphy_workarounds_rev3plus()
3155 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */ in b43_nphy_workarounds_rev3plus()
3156 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */ in b43_nphy_workarounds_rev3plus()
3157 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */ in b43_nphy_workarounds_rev3plus()
3160 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */ in b43_nphy_workarounds_rev3plus()
3161 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */ in b43_nphy_workarounds_rev3plus()
3162 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */ in b43_nphy_workarounds_rev3plus()
3163 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */ in b43_nphy_workarounds_rev3plus()
3164 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */ in b43_nphy_workarounds_rev3plus()
3172 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); in b43_nphy_workarounds_rev3plus()
3173 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); in b43_nphy_workarounds_rev3plus()
3175 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); in b43_nphy_workarounds_rev3plus()
3176 tmp32 &= 0xffffff; in b43_nphy_workarounds_rev3plus()
3177 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); in b43_nphy_workarounds_rev3plus()
3179 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); in b43_nphy_workarounds_rev3plus()
3180 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); in b43_nphy_workarounds_rev3plus()
3181 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); in b43_nphy_workarounds_rev3plus()
3182 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); in b43_nphy_workarounds_rev3plus()
3183 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); in b43_nphy_workarounds_rev3plus()
3184 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); in b43_nphy_workarounds_rev3plus()
3186 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3187 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); in b43_nphy_workarounds_rev3plus()
3195 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, in b43_nphy_workarounds_rev3plus()
3202 rx2tx_events[7] = 0x1F; in b43_nphy_workarounds_rev3plus()
3204 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, in b43_nphy_workarounds_rev3plus()
3209 0x2 : 0x9C40; in b43_nphy_workarounds_rev3plus()
3212 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); in b43_nphy_workarounds_rev3plus()
3215 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); in b43_nphy_workarounds_rev3plus()
3216 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); in b43_nphy_workarounds_rev3plus()
3218 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); in b43_nphy_workarounds_rev3plus()
3219 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); in b43_nphy_workarounds_rev3plus()
3224 b43_ntab_write(dev, B43_NTAB16(8, 0), 2); in b43_nphy_workarounds_rev3plus()
3239 case 0: in b43_nphy_workarounds_rev3plus()
3241 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3242 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3243 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3244 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3249 vmid[3] = 0x94; in b43_nphy_workarounds_rev3plus()
3251 vmid[3] = 0x8e; in b43_nphy_workarounds_rev3plus()
3254 vmid[3] = 0x84; in b43_nphy_workarounds_rev3plus()
3257 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3258 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3259 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3260 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3266 vmid[3] = 0x8e; in b43_nphy_workarounds_rev3plus()
3267 tmp16 = 0x96; in b43_nphy_workarounds_rev3plus()
3268 gain[3] = 0x2; in b43_nphy_workarounds_rev3plus()
3270 vmid[3] = 0x89; in b43_nphy_workarounds_rev3plus()
3271 tmp16 = 0x89; in b43_nphy_workarounds_rev3plus()
3272 gain[3] = 0; in b43_nphy_workarounds_rev3plus()
3276 vmid[3] = 0x89; in b43_nphy_workarounds_rev3plus()
3277 tmp16 = 0x8b; in b43_nphy_workarounds_rev3plus()
3278 gain[3] = 0x2; in b43_nphy_workarounds_rev3plus()
3280 vmid[3] = 0x74; in b43_nphy_workarounds_rev3plus()
3281 tmp16 = 0x70; in b43_nphy_workarounds_rev3plus()
3282 gain[3] = 0; in b43_nphy_workarounds_rev3plus()
3285 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); in b43_nphy_workarounds_rev3plus()
3286 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); in b43_nphy_workarounds_rev3plus()
3288 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); in b43_nphy_workarounds_rev3plus()
3289 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); in b43_nphy_workarounds_rev3plus()
3293 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3294 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); in b43_nphy_workarounds_rev3plus()
3295 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3296 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); in b43_nphy_workarounds_rev3plus()
3297 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3298 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); in b43_nphy_workarounds_rev3plus()
3299 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3300 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); in b43_nphy_workarounds_rev3plus()
3301 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3302 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3303 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3304 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); in b43_nphy_workarounds_rev3plus()
3312 tmp32 = 0x00088888; in b43_nphy_workarounds_rev3plus()
3314 tmp32 = 0x88888888; in b43_nphy_workarounds_rev3plus()
3322 0x70); in b43_nphy_workarounds_rev3plus()
3324 0x70); in b43_nphy_workarounds_rev3plus()
3328 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); in b43_nphy_workarounds_rev3plus()
3329 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); in b43_nphy_workarounds_rev3plus()
3330 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); in b43_nphy_workarounds_rev3plus()
3331 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); in b43_nphy_workarounds_rev3plus()
3332 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3333 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3334 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3335 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3336 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); in b43_nphy_workarounds_rev3plus()
3337 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); in b43_nphy_workarounds_rev3plus()
3338 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); in b43_nphy_workarounds_rev3plus()
3339 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); in b43_nphy_workarounds_rev3plus()
3342 ; /* TODO: 0x0080000000000000 HF */ in b43_nphy_workarounds_rev3plus()
3352 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; in b43_nphy_workarounds_rev1_2()
3353 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; in b43_nphy_workarounds_rev1_2()
3355 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; in b43_nphy_workarounds_rev1_2()
3356 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; in b43_nphy_workarounds_rev1_2()
3360 delays1[0] = 0x1; in b43_nphy_workarounds_rev1_2()
3361 delays1[5] = 0x14; in b43_nphy_workarounds_rev1_2()
3366 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3367 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); in b43_nphy_workarounds_rev1_2()
3369 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3370 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); in b43_nphy_workarounds_rev1_2()
3373 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); in b43_nphy_workarounds_rev1_2()
3374 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); in b43_nphy_workarounds_rev1_2()
3376 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3377 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); in b43_nphy_workarounds_rev1_2()
3381 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); in b43_nphy_workarounds_rev1_2()
3382 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); in b43_nphy_workarounds_rev1_2()
3383 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3384 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); in b43_nphy_workarounds_rev1_2()
3385 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); in b43_nphy_workarounds_rev1_2()
3386 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); in b43_nphy_workarounds_rev1_2()
3389 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_workarounds_rev1_2()
3390 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_workarounds_rev1_2()
3391 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_workarounds_rev1_2()
3392 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_workarounds_rev1_2()
3394 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); in b43_nphy_workarounds_rev1_2()
3400 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) in b43_nphy_workarounds_rev1_2()
3404 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); in b43_nphy_workarounds_rev1_2()
3405 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); in b43_nphy_workarounds_rev1_2()
3413 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); in b43_nphy_workarounds_rev1_2()
3414 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); in b43_nphy_workarounds_rev1_2()
3415 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); in b43_nphy_workarounds_rev1_2()
3416 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); in b43_nphy_workarounds_rev1_2()
3417 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); in b43_nphy_workarounds_rev1_2()
3418 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); in b43_nphy_workarounds_rev1_2()
3422 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); in b43_nphy_workarounds_rev1_2()
3423 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); in b43_nphy_workarounds_rev1_2()
3424 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); in b43_nphy_workarounds_rev1_2()
3425 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); in b43_nphy_workarounds_rev1_2()
3440 b43_nphy_classifier(dev, 1, 0); in b43_nphy_workarounds()
3459 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_workarounds()
3474 if (samp == 0) in b43_nphy_tx_tone()
3476 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, in b43_nphy_tx_tone()
3478 return 0; in b43_nphy_tx_tone()
3487 u16 chain = 0x33; in b43_nphy_update_txrx_chain()
3489 if (nphy->txrx_chain == 0) { in b43_nphy_update_txrx_chain()
3490 chain = 0x11; in b43_nphy_update_txrx_chain()
3493 chain = 0x22; in b43_nphy_update_txrx_chain()
3520 if (tmp & 0x1) in b43_nphy_stop_playback()
3522 else if (tmp & 0x2) in b43_nphy_stop_playback()
3523 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); in b43_nphy_stop_playback()
3525 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); in b43_nphy_stop_playback()
3527 if (nphy->bb_mult_save & 0x80000000) { in b43_nphy_stop_playback()
3528 tmp = nphy->bb_mult_save & 0xFFFF; in b43_nphy_stop_playback()
3530 nphy->bb_mult_save = 0; in b43_nphy_stop_playback()
3535 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, in b43_nphy_stop_playback()
3538 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); in b43_nphy_stop_playback()
3543 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_stop_playback()
3568 for (j = 0; j < 5; j++) in b43_nphy_iq_cal_gain_params()
3569 params->ncorr[j] = 0x79; in b43_nphy_iq_cal_gain_params()
3575 1 : 0; in b43_nphy_iq_cal_gain_params()
3576 for (i = 0; i < 9; i++) in b43_nphy_iq_cal_gain_params()
3577 if (tbl_iqcal_gainparams[indx][i][0] == gain) in b43_nphy_iq_cal_gain_params()
3586 for (j = 0; j < 4; j++) in b43_nphy_iq_cal_gain_params()
3615 nphy->tx_pwr_idx[0] = b43_phy_read(dev, in b43_nphy_tx_power_ctrl()
3616 B43_NPHY_C1_TXPCTL_STAT) & 0x7f; in b43_nphy_tx_power_ctrl()
3618 B43_NPHY_C2_TXPCTL_STAT) & 0x7f; in b43_nphy_tx_power_ctrl()
3621 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); in b43_nphy_tx_power_ctrl()
3622 for (i = 0; i < 84; i++) in b43_nphy_tx_power_ctrl()
3623 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3625 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); in b43_nphy_tx_power_ctrl()
3626 for (i = 0; i < 84; i++) in b43_nphy_tx_power_ctrl()
3627 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); in b43_nphy_tx_power_ctrl()
3635 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_ctrl()
3636 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_ctrl()
3638 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_ctrl()
3643 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53); in b43_nphy_tx_power_ctrl()
3646 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); in b43_nphy_tx_power_ctrl()
3673 0x32); in b43_nphy_tx_power_ctrl()
3676 0x32); in b43_nphy_tx_power_ctrl()
3680 0x64); in b43_nphy_tx_power_ctrl()
3685 0x64); in b43_nphy_tx_power_ctrl()
3690 if (nphy->tx_pwr_idx[0] != 128 && in b43_nphy_tx_power_ctrl()
3695 nphy->tx_pwr_idx[0]); in b43_nphy_tx_power_ctrl()
3699 ~0xff, nphy->tx_pwr_idx[1]); in b43_nphy_tx_power_ctrl()
3708 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); in b43_nphy_tx_power_ctrl()
3709 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); in b43_nphy_tx_power_ctrl()
3711 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); in b43_nphy_tx_power_ctrl()
3715 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); in b43_nphy_tx_power_ctrl()
3717 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); in b43_nphy_tx_power_ctrl()
3723 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); in b43_nphy_tx_power_ctrl()
3724 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); in b43_nphy_tx_power_ctrl()
3729 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_ctrl()
3750 txpi[0] = txpi[1] = 30; in b43_nphy_tx_power_fix()
3752 txpi[0] = 40; in b43_nphy_tx_power_fix()
3755 txpi[0] = 72; in b43_nphy_tx_power_fix()
3759 txpi[0] = sprom->txpid2g[0]; in b43_nphy_tx_power_fix()
3762 txpi[0] = sprom->txpid5gl[0]; in b43_nphy_tx_power_fix()
3765 txpi[0] = sprom->txpid5g[0]; in b43_nphy_tx_power_fix()
3768 txpi[0] = sprom->txpid5gh[0]; in b43_nphy_tx_power_fix()
3771 txpi[0] = 91; in b43_nphy_tx_power_fix()
3776 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100)) in b43_nphy_tx_power_fix()
3777 txpi[0] = txpi[1] = 91; in b43_nphy_tx_power_fix()
3780 for (i = 0; i < 2; i++) { in b43_nphy_tx_power_fix()
3786 for (i = 0; i < 2; i++) { in b43_nphy_tx_power_fix()
3794 radio_gain = (txgain >> 16) & 0x1FFFF; in b43_nphy_tx_power_fix()
3796 radio_gain = (txgain >> 16) & 0x1FFF; in b43_nphy_tx_power_fix()
3799 dac_gain = (txgain >> 8) & 0x7; in b43_nphy_tx_power_fix()
3801 dac_gain = (txgain >> 8) & 0x3F; in b43_nphy_tx_power_fix()
3802 bbmult = txgain & 0xFF; in b43_nphy_tx_power_fix()
3805 if (i == 0) in b43_nphy_tx_power_fix()
3806 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); in b43_nphy_tx_power_fix()
3808 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); in b43_nphy_tx_power_fix()
3810 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); in b43_nphy_tx_power_fix()
3813 if (i == 0) in b43_nphy_tx_power_fix()
3818 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); in b43_nphy_tx_power_fix()
3820 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); in b43_nphy_tx_power_fix()
3821 if (i == 0) in b43_nphy_tx_power_fix()
3822 tmp = (tmp & 0x00FF) | (bbmult << 8); in b43_nphy_tx_power_fix()
3824 tmp = (tmp & 0xFF00) | bbmult; in b43_nphy_tx_power_fix()
3825 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); in b43_nphy_tx_power_fix()
3829 u16 reg = (i == 0) ? in b43_nphy_tx_power_fix()
3833 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); in b43_nphy_tx_power_fix()
3834 b43_phy_set(dev, reg, 0x4); in b43_nphy_tx_power_fix()
3841 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_tx_power_fix()
3854 for (core = 0; core < 2; core++) { in b43_nphy_ipa_internal_tssi_setup()
3855 r = core ? 0x190 : 0x170; in b43_nphy_ipa_internal_tssi_setup()
3857 b43_radio_write(dev, r + 0x5, 0x5); in b43_nphy_ipa_internal_tssi_setup()
3858 b43_radio_write(dev, r + 0x9, 0xE); in b43_nphy_ipa_internal_tssi_setup()
3860 b43_radio_write(dev, r + 0xA, 0); in b43_nphy_ipa_internal_tssi_setup()
3862 b43_radio_write(dev, r + 0xB, 1); in b43_nphy_ipa_internal_tssi_setup()
3864 b43_radio_write(dev, r + 0xB, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3866 b43_radio_write(dev, r + 0x5, 0x9); in b43_nphy_ipa_internal_tssi_setup()
3867 b43_radio_write(dev, r + 0x9, 0xC); in b43_nphy_ipa_internal_tssi_setup()
3868 b43_radio_write(dev, r + 0xB, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3870 b43_radio_write(dev, r + 0xA, 1); in b43_nphy_ipa_internal_tssi_setup()
3872 b43_radio_write(dev, r + 0xA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3874 b43_radio_write(dev, r + 0x6, 0); in b43_nphy_ipa_internal_tssi_setup()
3875 b43_radio_write(dev, r + 0x7, 0); in b43_nphy_ipa_internal_tssi_setup()
3876 b43_radio_write(dev, r + 0x8, 3); in b43_nphy_ipa_internal_tssi_setup()
3877 b43_radio_write(dev, r + 0xC, 0); in b43_nphy_ipa_internal_tssi_setup()
3881 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); in b43_nphy_ipa_internal_tssi_setup()
3883 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); in b43_nphy_ipa_internal_tssi_setup()
3884 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); in b43_nphy_ipa_internal_tssi_setup()
3885 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); in b43_nphy_ipa_internal_tssi_setup()
3887 for (core = 0; core < 2; core++) { in b43_nphy_ipa_internal_tssi_setup()
3890 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); in b43_nphy_ipa_internal_tssi_setup()
3891 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); in b43_nphy_ipa_internal_tssi_setup()
3893 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); in b43_nphy_ipa_internal_tssi_setup()
3895 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); in b43_nphy_ipa_internal_tssi_setup()
3896 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); in b43_nphy_ipa_internal_tssi_setup()
3899 0x5); in b43_nphy_ipa_internal_tssi_setup()
3902 0x00); in b43_nphy_ipa_internal_tssi_setup()
3905 0x31); in b43_nphy_ipa_internal_tssi_setup()
3908 0x11); in b43_nphy_ipa_internal_tssi_setup()
3910 0xE); in b43_nphy_ipa_internal_tssi_setup()
3913 0x9); in b43_nphy_ipa_internal_tssi_setup()
3914 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); in b43_nphy_ipa_internal_tssi_setup()
3915 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); in b43_nphy_ipa_internal_tssi_setup()
3917 0xC); in b43_nphy_ipa_internal_tssi_setup()
3943 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3945 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3947 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); in b43_nphy_tx_power_ctl_idle_tssi()
3950 b43_nphy_tx_tone(dev, 4000, 0, false, false, false); in b43_nphy_tx_power_ctl_idle_tssi()
3955 b43_nphy_rssi_select(dev, 0, N_RSSI_W1); in b43_nphy_tx_power_ctl_idle_tssi()
3958 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3960 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); in b43_nphy_tx_power_ctl_idle_tssi()
3962 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); in b43_nphy_tx_power_ctl_idle_tssi()
3968 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; in b43_nphy_tx_power_ctl_idle_tssi()
3969 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF; in b43_nphy_tx_power_ctl_idle_tssi()
3971 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF; in b43_nphy_tx_power_ctl_idle_tssi()
3972 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF; in b43_nphy_tx_power_ctl_idle_tssi()
3974 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF; in b43_nphy_tx_power_ctl_idle_tssi()
3975 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF; in b43_nphy_tx_power_ctl_idle_tssi()
3992 * Group 0 is for CCK in b43_nphy_tx_prepare_adjusted_power_table()
4000 for (i = 0; i < 4; i++) in b43_nphy_tx_prepare_adjusted_power_table()
4003 for (stf_mode = 0; stf_mode < 4; stf_mode++) { in b43_nphy_tx_prepare_adjusted_power_table()
4004 delta = 0; in b43_nphy_tx_prepare_adjusted_power_table()
4006 case 0: in b43_nphy_tx_prepare_adjusted_power_table()
4025 for (i = 0; i < 20; i++) { in b43_nphy_tx_prepare_adjusted_power_table()
4028 if (i == 0) in b43_nphy_tx_prepare_adjusted_power_table()
4059 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4070 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF); in b43_nphy_tx_power_ctl_setup()
4076 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4079 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g; in b43_nphy_tx_power_ctl_setup()
4081 target[0] = target[1] = 52; in b43_nphy_tx_power_ctl_setup()
4082 a1[0] = a1[1] = -424; in b43_nphy_tx_power_ctl_setup()
4083 b0[0] = b0[1] = 5612; in b43_nphy_tx_power_ctl_setup()
4084 b1[0] = b1[1] = -1393; in b43_nphy_tx_power_ctl_setup()
4087 for (c = 0; c < 2; c++) { in b43_nphy_tx_power_ctl_setup()
4090 a1[c] = sprom->core_pwr_info[c].pa_2g[0]; in b43_nphy_tx_power_ctl_setup()
4095 for (c = 0; c < 2; c++) { in b43_nphy_tx_power_ctl_setup()
4098 a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; in b43_nphy_tx_power_ctl_setup()
4103 for (c = 0; c < 2; c++) { in b43_nphy_tx_power_ctl_setup()
4106 a1[c] = sprom->core_pwr_info[c].pa_5g[0]; in b43_nphy_tx_power_ctl_setup()
4111 for (c = 0; c < 2; c++) { in b43_nphy_tx_power_ctl_setup()
4114 a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; in b43_nphy_tx_power_ctl_setup()
4119 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g; in b43_nphy_tx_power_ctl_setup()
4121 target[0] = target[1] = 52; in b43_nphy_tx_power_ctl_setup()
4122 a1[0] = a1[1] = -424; in b43_nphy_tx_power_ctl_setup()
4123 b0[0] = b0[1] = 5612; in b43_nphy_tx_power_ctl_setup()
4124 b1[0] = b1[1] = -1393; in b43_nphy_tx_power_ctl_setup()
4130 target[0] = ppr_max; in b43_nphy_tx_power_ctl_setup()
4136 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); in b43_nphy_tx_power_ctl_setup()
4138 for (c = 0; c < 2; c++) { in b43_nphy_tx_power_ctl_setup()
4139 r = c ? 0x190 : 0x170; in b43_nphy_tx_power_ctl_setup()
4141 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == NL80211_BAND_2GHZ) ? 0xE : 0xC); in b43_nphy_tx_power_ctl_setup()
4145 tmp = (b43_current_band(dev->wl) == NL80211_BAND_5GHZ) ? 0xC : 0xE; in b43_nphy_tx_power_ctl_setup()
4152 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11); in b43_nphy_tx_power_ctl_setup()
4154 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11); in b43_nphy_tx_power_ctl_setup()
4160 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); in b43_nphy_tx_power_ctl_setup()
4169 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19); in b43_nphy_tx_power_ctl_setup()
4171 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19); in b43_nphy_tx_power_ctl_setup()
4174 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40); in b43_nphy_tx_power_ctl_setup()
4177 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40); in b43_nphy_tx_power_ctl_setup()
4181 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); in b43_nphy_tx_power_ctl_setup()
4184 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT | in b43_nphy_tx_power_ctl_setup()
4187 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT | in b43_nphy_tx_power_ctl_setup()
4191 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT | in b43_nphy_tx_power_ctl_setup()
4194 for (c = 0; c < 2; c++) { in b43_nphy_tx_power_ctl_setup()
4195 for (i = 0; i < 64; i++) { in b43_nphy_tx_power_ctl_setup()
4203 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); in b43_nphy_tx_power_ctl_setup()
4234 #if 0 in b43_nphy_tx_gain_table_upload()
4235 nphy->gmval = (table[0] >> 16) & 0x7000; in b43_nphy_tx_gain_table_upload()
4248 for (i = 0; i < 128; i++) { in b43_nphy_tx_gain_table_upload()
4253 pga_gain = (table[i] >> 24) & 0xf; in b43_nphy_tx_gain_table_upload()
4254 pad_gain = (table[i] >> 19) & 0x1f; in b43_nphy_tx_gain_table_upload()
4260 pga_gain = (table[i] >> 24) & 0xF; in b43_nphy_tx_gain_table_upload()
4264 rfpwr_offset = 0; /* FIXME */ in b43_nphy_tx_gain_table_upload()
4286 tmp = 0x1480; in b43_nphy_pa_override()
4289 tmp = 0x600; in b43_nphy_pa_override()
4291 tmp = 0x480; in b43_nphy_pa_override()
4294 tmp = 0x180; in b43_nphy_pa_override()
4296 tmp = 0x120; in b43_nphy_pa_override()
4369 memset(est, 0, sizeof(*est)); in b43_nphy_rx_iq_est()
4389 #if 0
4396 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
4397 if (core == 0) {
4420 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4421 if (core == 0) {
4437 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4438 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4441 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4450 if (core == 0) {
4451 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
4452 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
4454 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
4455 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
4458 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
4459 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
4462 if (core == 0) {
4492 if (mask == 0) in b43_nphy_calc_rx_iq_comp()
4497 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); in b43_nphy_calc_rx_iq_comp()
4500 for (i = 0; i < 2; i++) { in b43_nphy_calc_rx_iq_comp()
4501 if (i == 0 && (mask & 1)) { in b43_nphy_calc_rx_iq_comp()
4522 if (arsh >= 0) { in b43_nphy_calc_rx_iq_comp()
4529 if (tmp == 0) { in b43_nphy_calc_rx_iq_comp()
4536 if (brsh >= 0) { in b43_nphy_calc_rx_iq_comp()
4543 if (tmp == 0) { in b43_nphy_calc_rx_iq_comp()
4549 if (i == 0 && (mask & 0x1)) { in b43_nphy_calc_rx_iq_comp()
4551 new.a0 = a & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4552 new.b0 = b & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4554 new.a0 = b & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4555 new.b0 = a & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4557 } else if (i == 1 && (mask & 0x2)) { in b43_nphy_calc_rx_iq_comp()
4559 new.a1 = a & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4560 new.b1 = b & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4562 new.a1 = b & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4563 new.b1 = a & 0x3FF; in b43_nphy_calc_rx_iq_comp()
4578 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); in b43_nphy_tx_iq_workaround()
4580 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); in b43_nphy_tx_iq_workaround()
4597 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_spur_workaround()
4615 for (i = 0; i < 2; i++) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4616 tmp = ((buffer[i * 2] & 0x3FF) << 10) | in b43_nphy_tx_pwr_ctrl_coef_setup()
4617 (buffer[i * 2 + 1] & 0x3FF); in b43_nphy_tx_pwr_ctrl_coef_setup()
4620 for (j = 0; j < 128; j++) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4622 ((tmp >> 16) & 0xFFFF)); in b43_nphy_tx_pwr_ctrl_coef_setup()
4624 (tmp & 0xFFFF)); in b43_nphy_tx_pwr_ctrl_coef_setup()
4628 for (i = 0; i < 2; i++) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4630 real_part = (tmp >> 8) & 0xFF; in b43_nphy_tx_pwr_ctrl_coef_setup()
4631 imag_part = (tmp & 0xFF); in b43_nphy_tx_pwr_ctrl_coef_setup()
4638 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); in b43_nphy_tx_pwr_ctrl_coef_setup()
4641 for (j = 0; j < 128; j++) { in b43_nphy_tx_pwr_ctrl_coef_setup()
4645 tmp = ((cur_real & 0xFF) << 8) | in b43_nphy_tx_pwr_ctrl_coef_setup()
4646 (cur_imag & 0xFF); in b43_nphy_tx_pwr_ctrl_coef_setup()
4649 ((tmp >> 16) & 0xFFFF)); in b43_nphy_tx_pwr_ctrl_coef_setup()
4651 (tmp & 0xFFFF)); in b43_nphy_tx_pwr_ctrl_coef_setup()
4657 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); in b43_nphy_tx_pwr_ctrl_coef_setup()
4659 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); in b43_nphy_tx_pwr_ctrl_coef_setup()
4693 rssical_radio_regs[0]); in b43_nphy_restore_rssi_cal()
4697 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4698 rssical_radio_regs[0]); in b43_nphy_restore_rssi_cal()
4699 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, in b43_nphy_restore_rssi_cal()
4703 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); in b43_nphy_restore_rssi_cal()
4732 for (core = 0; core < 2; core++) { in b43_nphy_tx_cal_radio_setup_rev7()
4733 r = core ? 0x20 : 0; in b43_nphy_tx_cal_radio_setup_rev7()
4736 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); in b43_nphy_tx_cal_radio_setup_rev7()
4740 save[off + 4] = 0; in b43_nphy_tx_cal_radio_setup_rev7()
4748 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); in b43_nphy_tx_cal_radio_setup_rev7()
4749 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4750 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4751 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4752 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4754 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); in b43_nphy_tx_cal_radio_setup_rev7()
4755 tmp = true ? 0x31 : 0x21; /* TODO */ in b43_nphy_tx_cal_radio_setup_rev7()
4758 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); in b43_nphy_tx_cal_radio_setup_rev7()
4760 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4761 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); in b43_nphy_tx_cal_radio_setup_rev7()
4762 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); in b43_nphy_tx_cal_radio_setup_rev7()
4763 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4766 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4768 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); in b43_nphy_tx_cal_radio_setup_rev7()
4769 tmp = true ? 0x31 : 0x21; /* TODO */ in b43_nphy_tx_cal_radio_setup_rev7()
4772 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); in b43_nphy_tx_cal_radio_setup_rev7()
4791 for (i = 0; i < 2; i++) { in b43_nphy_tx_cal_radio_setup()
4792 tmp = (i == 0) ? 0x2000 : 0x3000; in b43_nphy_tx_cal_radio_setup()
4795 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); in b43_nphy_tx_cal_radio_setup()
4808 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); in b43_nphy_tx_cal_radio_setup()
4809 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4810 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4811 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4812 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4817 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4818 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); in b43_nphy_tx_cal_radio_setup()
4820 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4822 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); in b43_nphy_tx_cal_radio_setup()
4823 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); in b43_nphy_tx_cal_radio_setup()
4824 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); in b43_nphy_tx_cal_radio_setup()
4825 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4826 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); in b43_nphy_tx_cal_radio_setup()
4827 b43_radio_write(dev, tmp | B2055_XOCTL1, 0); in b43_nphy_tx_cal_radio_setup()
4831 (dev->phy.rev < 5) ? 0x11 : 0x01); in b43_nphy_tx_cal_radio_setup()
4833 b43_radio_write(dev, tmp | B2055_PADDRV, 0); in b43_nphy_tx_cal_radio_setup()
4834 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); in b43_nphy_tx_cal_radio_setup()
4837 b43_radio_write(dev, tmp | B2055_XOREGUL, 0); in b43_nphy_tx_cal_radio_setup()
4838 b43_radio_write(dev, tmp | B2055_XOMISC, 0); in b43_nphy_tx_cal_radio_setup()
4839 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); in b43_nphy_tx_cal_radio_setup()
4842 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); in b43_nphy_tx_cal_radio_setup()
4843 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4846 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4849 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); in b43_nphy_tx_cal_radio_setup()
4852 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); in b43_nphy_tx_cal_radio_setup()
4859 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4860 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); in b43_nphy_tx_cal_radio_setup()
4862 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4863 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); in b43_nphy_tx_cal_radio_setup()
4867 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4868 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); in b43_nphy_tx_cal_radio_setup()
4870 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4871 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); in b43_nphy_tx_cal_radio_setup()
4884 if (core == 0) in b43_nphy_update_tx_cal_ladder()
4886 tmp &= 0xff; in b43_nphy_update_tx_cal_ladder()
4888 for (i = 0; i < 18; i++) { in b43_nphy_update_tx_cal_ladder()
4890 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; in b43_nphy_update_tx_cal_ladder()
4894 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; in b43_nphy_update_tx_cal_ladder()
4906 for (i = 0; i < 15; i++, offset++) in b43_nphy_pa_set_tx_dig_filter()
4913 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, in b43_nphy_ext_pa_set_tx_dig_filters()
4921 static const u16 offset[] = { 0x186, 0x195, 0x2C5 }; in b43_nphy_int_pa_set_tx_dig_filters()
4929 for (i = 0; i < 3; i++) in b43_nphy_int_pa_set_tx_dig_filters()
4935 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4939 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); in b43_nphy_int_pa_set_tx_dig_filters()
4940 b43_nphy_pa_set_tx_dig_filter(dev, 0x195, in b43_nphy_int_pa_set_tx_dig_filters()
4945 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4949 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4952 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, in b43_nphy_int_pa_set_tx_dig_filters()
4971 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); in b43_nphy_get_tx_gains()
4975 for (i = 0; i < 2; ++i) { in b43_nphy_get_tx_gains()
4977 target.ipa[i] = curr_gain[i] & 0x0007; in b43_nphy_get_tx_gains()
4978 target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; in b43_nphy_get_tx_gains()
4979 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; in b43_nphy_get_tx_gains()
4980 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; in b43_nphy_get_tx_gains()
4981 target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; in b43_nphy_get_tx_gains()
4983 target.ipa[i] = curr_gain[i] & 0x000F; in b43_nphy_get_tx_gains()
4984 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; in b43_nphy_get_tx_gains()
4985 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; in b43_nphy_get_tx_gains()
4986 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; in b43_nphy_get_tx_gains()
4988 target.ipa[i] = curr_gain[i] & 0x0003; in b43_nphy_get_tx_gains()
4989 target.pad[i] = (curr_gain[i] & 0x000C) >> 2; in b43_nphy_get_tx_gains()
4990 target.pga[i] = (curr_gain[i] & 0x0070) >> 4; in b43_nphy_get_tx_gains()
4991 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; in b43_nphy_get_tx_gains()
4997 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & in b43_nphy_get_tx_gains()
5004 for (i = 0; i < 2; ++i) { in b43_nphy_get_tx_gains()
5010 target.ipa[i] = (table[index[i]] >> 16) & 0x7; in b43_nphy_get_tx_gains()
5011 target.pad[i] = (table[index[i]] >> 19) & 0x1F; in b43_nphy_get_tx_gains()
5012 target.pga[i] = (table[index[i]] >> 24) & 0xF; in b43_nphy_get_tx_gains()
5013 target.txgm[i] = (table[index[i]] >> 28) & 0x7; in b43_nphy_get_tx_gains()
5014 target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; in b43_nphy_get_tx_gains()
5016 target.ipa[i] = (table[index[i]] >> 16) & 0xF; in b43_nphy_get_tx_gains()
5017 target.pad[i] = (table[index[i]] >> 20) & 0xF; in b43_nphy_get_tx_gains()
5018 target.pga[i] = (table[index[i]] >> 24) & 0xF; in b43_nphy_get_tx_gains()
5019 target.txgm[i] = (table[index[i]] >> 28) & 0xF; in b43_nphy_get_tx_gains()
5021 target.ipa[i] = (table[index[i]] >> 16) & 0x3; in b43_nphy_get_tx_gains()
5022 target.pad[i] = (table[index[i]] >> 18) & 0x3; in b43_nphy_get_tx_gains()
5023 target.pga[i] = (table[index[i]] >> 20) & 0x7; in b43_nphy_get_tx_gains()
5024 target.txgm[i] = (table[index[i]] >> 23) & 0x7; in b43_nphy_get_tx_gains()
5038 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5051 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); in b43_nphy_tx_cal_phy_cleanup()
5052 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); in b43_nphy_tx_cal_phy_cleanup()
5069 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); in b43_nphy_tx_cal_phy_setup()
5072 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5073 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); in b43_nphy_tx_cal_phy_setup()
5077 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5081 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); in b43_nphy_tx_cal_phy_setup()
5085 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); in b43_nphy_tx_cal_phy_setup()
5089 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); in b43_nphy_tx_cal_phy_setup()
5093 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); in b43_nphy_tx_cal_phy_setup()
5102 0, 3); in b43_nphy_tx_cal_phy_setup()
5108 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5109 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); in b43_nphy_tx_cal_phy_setup()
5111 tmp = b43_nphy_read_lpf_ctl(dev, 0); in b43_nphy_tx_cal_phy_setup()
5113 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5116 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, in b43_nphy_tx_cal_phy_setup()
5121 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5122 false, 0); in b43_nphy_tx_cal_phy_setup()
5124 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, in b43_nphy_tx_cal_phy_setup()
5125 false, 0); in b43_nphy_tx_cal_phy_setup()
5129 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5130 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5132 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5133 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); in b43_nphy_tx_cal_phy_setup()
5138 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5139 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); in b43_nphy_tx_cal_phy_setup()
5142 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); in b43_nphy_tx_cal_phy_setup()
5145 tmp |= 0x2000; in b43_nphy_tx_cal_phy_setup()
5149 tmp |= 0x2000; in b43_nphy_tx_cal_phy_setup()
5154 tmp = 0x0180; in b43_nphy_tx_cal_phy_setup()
5156 tmp = 0x0120; in b43_nphy_tx_cal_phy_setup()
5193 txcal_radio_regs[0] = b43_radio_read(dev, in b43_nphy_save_cal()
5210 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); in b43_nphy_save_cal()
5211 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); in b43_nphy_save_cal()
5212 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); in b43_nphy_save_cal()
5213 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); in b43_nphy_save_cal()
5214 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); in b43_nphy_save_cal()
5215 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); in b43_nphy_save_cal()
5216 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); in b43_nphy_save_cal()
5217 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); in b43_nphy_save_cal()
5219 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); in b43_nphy_save_cal()
5220 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); in b43_nphy_save_cal()
5221 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); in b43_nphy_save_cal()
5222 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); in b43_nphy_save_cal()
5230 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_save_cal()
5261 for (i = 0; i < 4; i++) { in b43_nphy_restore_cal()
5265 coef[i] = 0; in b43_nphy_restore_cal()
5288 txcal_radio_regs[0]); in b43_nphy_restore_cal()
5304 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5305 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5306 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5307 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5308 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); in b43_nphy_restore_cal()
5309 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); in b43_nphy_restore_cal()
5310 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); in b43_nphy_restore_cal()
5311 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); in b43_nphy_restore_cal()
5313 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); in b43_nphy_restore_cal()
5314 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); in b43_nphy_restore_cal()
5315 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); in b43_nphy_restore_cal()
5316 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); in b43_nphy_restore_cal()
5329 int error = 0; in b43_nphy_cal_tx_iq_lo()
5333 u16 tmp, core, type, count, max, numb, last = 0, cmd; in b43_nphy_cal_tx_iq_lo()
5338 u16 diq_start = 0; in b43_nphy_cal_tx_iq_lo()
5351 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5353 for (i = 0; i < 2; i++) { in b43_nphy_cal_tx_iq_lo()
5358 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); in b43_nphy_cal_tx_iq_lo()
5368 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5373 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, in b43_nphy_cal_tx_iq_lo()
5383 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); in b43_nphy_cal_tx_iq_lo()
5385 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); in b43_nphy_cal_tx_iq_lo()
5395 0xFFFF, 0, true, false, false); in b43_nphy_cal_tx_iq_lo()
5399 if (error == 0) { in b43_nphy_cal_tx_iq_lo()
5442 count = 0; in b43_nphy_cal_tx_iq_lo()
5459 core = (cmd & 0x3000) >> 12; in b43_nphy_cal_tx_iq_lo()
5460 type = (cmd & 0x0F00) >> 8; in b43_nphy_cal_tx_iq_lo()
5467 tmp = (params[core].ncorr[type] << 8) | 0x66; in b43_nphy_cal_tx_iq_lo()
5471 buffer[0] = b43_ntab_read(dev, in b43_nphy_cal_tx_iq_lo()
5473 diq_start = buffer[0]; in b43_nphy_cal_tx_iq_lo()
5474 buffer[0] = 0; in b43_nphy_cal_tx_iq_lo()
5476 0); in b43_nphy_cal_tx_iq_lo()
5480 for (i = 0; i < 2000; i++) { in b43_nphy_cal_tx_iq_lo()
5482 if (tmp & 0xC000) in b43_nphy_cal_tx_iq_lo()
5493 buffer[0] = diq_start; in b43_nphy_cal_tx_iq_lo()
5497 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; in b43_nphy_cal_tx_iq_lo()
5505 buffer[0] = 0; in b43_nphy_cal_tx_iq_lo()
5506 buffer[1] = 0; in b43_nphy_cal_tx_iq_lo()
5507 buffer[2] = 0; in b43_nphy_cal_tx_iq_lo()
5508 buffer[3] = 0; in b43_nphy_cal_tx_iq_lo()
5537 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); in b43_nphy_cal_tx_iq_lo()
5541 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); in b43_nphy_cal_tx_iq_lo()
5568 for (i = 0; i < 4; i++) { in b43_nphy_reapply_tx_cal_coeffs()
5578 for (i = 0; i < 4; i++) in b43_nphy_reapply_tx_cal_coeffs()
5579 buffer[i] = 0; in b43_nphy_reapply_tx_cal_coeffs()
5605 u16 hpf1[3] = { 7, 2, 0 }; in b43_nphy_rev2_cal_rx_iq()
5606 u16 hpf2[3] = { 2, 0, 0 }; in b43_nphy_rev2_cal_rx_iq()
5612 int ret = 0; in b43_nphy_rev2_cal_rx_iq()
5620 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5621 for (i = 0; i < 2; i++) { in b43_nphy_rev2_cal_rx_iq()
5625 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); in b43_nphy_rev2_cal_rx_iq()
5627 for (i = 0; i < 2; i++) { in b43_nphy_rev2_cal_rx_iq()
5628 if (i == 0) { in b43_nphy_rev2_cal_rx_iq()
5629 rfctl[0] = B43_NPHY_RFCTL_INTC1; in b43_nphy_rev2_cal_rx_iq()
5633 rfctl[0] = B43_NPHY_RFCTL_INTC2; in b43_nphy_rev2_cal_rx_iq()
5641 tmp[4] = b43_phy_read(dev, rfctl[0]); in b43_nphy_rev2_cal_rx_iq()
5645 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, in b43_nphy_rev2_cal_rx_iq()
5649 b43_phy_set(dev, afectl_core, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5650 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); in b43_nphy_rev2_cal_rx_iq()
5654 if (nphy->rxcalparams & 0xFF000000) { in b43_nphy_rev2_cal_rx_iq()
5656 b43_phy_write(dev, rfctl[0], 0x140); in b43_nphy_rev2_cal_rx_iq()
5658 b43_phy_write(dev, rfctl[0], 0x110); in b43_nphy_rev2_cal_rx_iq()
5661 b43_phy_write(dev, rfctl[0], 0x180); in b43_nphy_rev2_cal_rx_iq()
5663 b43_phy_write(dev, rfctl[0], 0x120); in b43_nphy_rev2_cal_rx_iq()
5667 b43_phy_write(dev, rfctl[1], 0x148); in b43_nphy_rev2_cal_rx_iq()
5669 b43_phy_write(dev, rfctl[1], 0x114); in b43_nphy_rev2_cal_rx_iq()
5671 if (nphy->rxcalparams & 0x10000) { in b43_nphy_rev2_cal_rx_iq()
5672 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5674 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, in b43_nphy_rev2_cal_rx_iq()
5678 for (j = 0; j < 4; j++) { in b43_nphy_rev2_cal_rx_iq()
5689 if (power[0] > 10000) { in b43_nphy_rev2_cal_rx_iq()
5694 index = 0; in b43_nphy_rev2_cal_rx_iq()
5703 cur_hpf = clamp_val(cur_hpf, 0, 10); in b43_nphy_rev2_cal_rx_iq()
5710 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | in b43_nphy_rev2_cal_rx_iq()
5712 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, in b43_nphy_rev2_cal_rx_iq()
5719 (nphy->rxcalparams & 0xFFFF), in b43_nphy_rev2_cal_rx_iq()
5723 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, in b43_nphy_rev2_cal_rx_iq()
5727 if (ret == 0) { in b43_nphy_rev2_cal_rx_iq()
5731 if (i == 0) { in b43_nphy_rev2_cal_rx_iq()
5745 if (ret != 0) in b43_nphy_rev2_cal_rx_iq()
5749 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5750 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); in b43_nphy_rev2_cal_rx_iq()
5752 b43_phy_write(dev, rfctl[0], tmp[4]); in b43_nphy_rev2_cal_rx_iq()
5757 if (ret != 0) in b43_nphy_rev2_cal_rx_iq()
5761 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); in b43_nphy_rev2_cal_rx_iq()
5763 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); in b43_nphy_rev2_cal_rx_iq()
5765 b43_nphy_stay_in_carrier_search(dev, 0); in b43_nphy_rev2_cal_rx_iq()
5781 type = 0; in b43_nphy_cal_rx_iq()
5798 if (0 /* FIXME clk */) in b43_nphy_set_rx_core_state()
5807 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); in b43_nphy_set_rx_core_state()
5809 if ((mask & 0x3) != 0x3) { in b43_nphy_set_rx_core_state()
5815 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); in b43_nphy_set_rx_core_state()
5858 #if 0 in b43_nphy_op_recalc_txpower()
5875 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); in b43_nphy_op_recalc_txpower()
5881 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); in b43_nphy_op_recalc_txpower()
5914 val = 0x1E1F; in b43_nphy_bphy_init()
5915 for (i = 0; i < 16; i++) { in b43_nphy_bphy_init()
5916 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); in b43_nphy_bphy_init()
5917 val -= 0x202; in b43_nphy_bphy_init()
5919 val = 0x3E3F; in b43_nphy_bphy_init()
5920 for (i = 0; i < 16; i++) { in b43_nphy_bphy_init()
5921 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); in b43_nphy_bphy_init()
5922 val -= 0x202; in b43_nphy_bphy_init()
5924 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); in b43_nphy_bphy_init()
5936 if (0 /* FIXME */) { in b43_nphy_superswitch_init()
5937 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); in b43_nphy_superswitch_init()
5938 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); in b43_nphy_superswitch_init()
5939 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); in b43_nphy_superswitch_init()
5940 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); in b43_nphy_superswitch_init()
5943 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); in b43_nphy_superswitch_init()
5944 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); in b43_nphy_superswitch_init()
5950 0xFC00, 0xFC00); in b43_nphy_superswitch_init()
5956 0xFC00, 0xFC00); in b43_nphy_superswitch_init()
5961 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); in b43_nphy_superswitch_init()
5962 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); in b43_nphy_superswitch_init()
5963 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), in b43_nphy_superswitch_init()
5964 0); in b43_nphy_superswitch_init()
5967 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); in b43_nphy_superswitch_init()
5968 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); in b43_nphy_superswitch_init()
5969 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); in b43_nphy_superswitch_init()
5970 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); in b43_nphy_superswitch_init()
5996 BCMA_CC_CHIPCTL, 0x40); in b43_phy_initn()
6002 SSB_CHIPCO_CHIPCTL, 0x40); in b43_phy_initn()
6011 nphy->deaf_count = 0; in b43_phy_initn()
6018 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); in b43_phy_initn()
6019 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6021 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); in b43_phy_initn()
6022 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); in b43_phy_initn()
6023 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); in b43_phy_initn()
6024 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); in b43_phy_initn()
6030 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); in b43_phy_initn()
6031 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); in b43_phy_initn()
6033 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); in b43_phy_initn()
6035 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); in b43_phy_initn()
6036 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); in b43_phy_initn()
6038 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); in b43_phy_initn()
6039 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); in b43_phy_initn()
6045 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); in b43_phy_initn()
6046 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); in b43_phy_initn()
6049 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; in b43_phy_initn()
6054 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); in b43_phy_initn()
6055 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); in b43_phy_initn()
6060 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); in b43_phy_initn()
6062 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); in b43_phy_initn()
6063 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); in b43_phy_initn()
6064 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); in b43_phy_initn()
6065 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); in b43_phy_initn()
6073 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); in b43_phy_initn()
6074 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); in b43_phy_initn()
6078 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); in b43_phy_initn()
6079 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, in b43_phy_initn()
6080 nphy->papd_epsilon_offset[0] << 7); in b43_phy_initn()
6081 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); in b43_phy_initn()
6082 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, in b43_phy_initn()
6096 b43_phy_force_clock(dev, 0); in b43_phy_initn()
6107 b43_nphy_classifier(dev, 0, 0); in b43_phy_initn()
6121 if (nphy->mphase_cal_phase_id > 0) { in b43_phy_initn()
6140 if (!((nphy->measure_hold & 0x6) != 0)) { in b43_phy_initn()
6157 nphy->cal_orig_pwr_idx[0] = in b43_phy_initn()
6158 nphy->txpwrindex[0].index_internal; in b43_phy_initn()
6165 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) in b43_phy_initn()
6167 } else if (nphy->mphase_cal_phase_id == 0) { in b43_phy_initn()
6177 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); in b43_phy_initn()
6178 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); in b43_phy_initn()
6180 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); in b43_phy_initn()
6185 return 0; in b43_phy_initn()
6249 ~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX) & 0xffff); in b43_nphy_channel_setup()
6256 b43_nphy_classifier(dev, 2, 0); in b43_nphy_channel_setup()
6257 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); in b43_nphy_channel_setup()
6261 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); in b43_nphy_channel_setup()
6274 u8 spuravoid = 0; in b43_nphy_channel_setup()
6301 spuravoid = dev->dev->chip_id == 0x4716; in b43_nphy_channel_setup()
6316 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); in b43_nphy_channel_setup()
6323 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); in b43_nphy_channel_setup()
6367 #if 0 in b43_nphy_set_channel()
6376 b43_phy_set(dev, 0x310, 0x8000); in b43_nphy_set_channel()
6380 b43_phy_mask(dev, 0x310, 0x7fff); in b43_nphy_set_channel()
6390 tmp = (channel->band == NL80211_BAND_5GHZ) ? 2 : 0; in b43_nphy_set_channel()
6398 tmp = (channel->band == NL80211_BAND_5GHZ) ? 4 : 0; in b43_nphy_set_channel()
6399 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); in b43_nphy_set_channel()
6403 tmp = (channel->band == NL80211_BAND_5GHZ) ? 0x0020 : 0x0050; in b43_nphy_set_channel()
6404 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); in b43_nphy_set_channel()
6409 return 0; in b43_nphy_set_channel()
6426 return 0; in b43_nphy_op_allocate()
6435 memset(nphy, 0, sizeof(*nphy)); in b43_nphy_op_prepare_structs()
6441 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ in b43_nphy_op_prepare_structs()
6445 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ in b43_nphy_op_prepare_structs()
6446 nphy->tx_pwr_idx[0] = 128; in b43_nphy_op_prepare_structs()
6466 if (pdev->device == 0x4328 || in b43_nphy_op_prepare_structs()
6467 pdev->device == 0x432a) in b43_nphy_op_prepare_structs()
6502 "0x%04X on N-PHY\n", offset); in check_phyreg()
6508 "0x%04X on N-PHY\n", offset); in check_phyreg()
6529 reg |= 0x200; /* Radio 0x2057 */ in b43_nphy_op_radio_read()
6531 reg |= 0x100; in b43_nphy_op_radio_read()
6567 b43_radio_mask(dev, 0x09, ~0x2); in b43_nphy_op_software_rfkill()
6569 b43_radio_write(dev, 0x204D, 0); in b43_nphy_op_software_rfkill()
6570 b43_radio_write(dev, 0x2053, 0); in b43_nphy_op_software_rfkill()
6571 b43_radio_write(dev, 0x2058, 0); in b43_nphy_op_software_rfkill()
6572 b43_radio_write(dev, 0x205E, 0); in b43_nphy_op_software_rfkill()
6573 b43_radio_mask(dev, 0x2062, ~0xF0); in b43_nphy_op_software_rfkill()
6574 b43_radio_write(dev, 0x2064, 0); in b43_nphy_op_software_rfkill()
6576 b43_radio_write(dev, 0x304D, 0); in b43_nphy_op_software_rfkill()
6577 b43_radio_write(dev, 0x3053, 0); in b43_nphy_op_software_rfkill()
6578 b43_radio_write(dev, 0x3058, 0); in b43_nphy_op_software_rfkill()
6579 b43_radio_write(dev, 0x305E, 0); in b43_nphy_op_software_rfkill()
6580 b43_radio_mask(dev, 0x3062, ~0xF0); in b43_nphy_op_software_rfkill()
6581 b43_radio_write(dev, 0x3064, 0); in b43_nphy_op_software_rfkill()
6604 u16 override = on ? 0x0 : 0x7FFF; in b43_nphy_op_switch_analog()
6605 u16 core = on ? 0xD : 0x00FD; in b43_nphy_op_switch_analog()