Lines Matching +full:0 +full:x938
66 b43_radio_set(dev, 0x09d, 0x4); in b43_radio_2064_channel_setup()
67 b43_radio_write(dev, 0x09e, 0xf); in b43_radio_2064_channel_setup()
70 b43_radio_write(dev, 0x02a, 0xb); in b43_radio_2064_channel_setup()
71 b43_radio_maskset(dev, 0x030, ~0x3, 0xa); in b43_radio_2064_channel_setup()
72 b43_radio_maskset(dev, 0x091, ~0x3, 0); in b43_radio_2064_channel_setup()
73 b43_radio_maskset(dev, 0x038, ~0xf, 0x7); in b43_radio_2064_channel_setup()
74 b43_radio_maskset(dev, 0x030, ~0xc, 0x8); in b43_radio_2064_channel_setup()
75 b43_radio_maskset(dev, 0x05e, ~0xf, 0x8); in b43_radio_2064_channel_setup()
76 b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80); in b43_radio_2064_channel_setup()
77 b43_radio_write(dev, 0x06c, 0x80); in b43_radio_2064_channel_setup()
79 save[0] = b43_radio_read(dev, 0x044); in b43_radio_2064_channel_setup()
80 save[1] = b43_radio_read(dev, 0x12b); in b43_radio_2064_channel_setup()
82 b43_radio_set(dev, 0x044, 0x7); in b43_radio_2064_channel_setup()
83 b43_radio_set(dev, 0x12b, 0xe); in b43_radio_2064_channel_setup()
87 b43_radio_write(dev, 0x040, 0xfb); in b43_radio_2064_channel_setup()
89 b43_radio_write(dev, 0x041, 0x9a); in b43_radio_2064_channel_setup()
90 b43_radio_write(dev, 0x042, 0xa3); in b43_radio_2064_channel_setup()
91 b43_radio_write(dev, 0x043, 0x0c); in b43_radio_2064_channel_setup()
95 b43_radio_set(dev, 0x044, 0x0c); in b43_radio_2064_channel_setup()
98 b43_radio_write(dev, 0x044, save[0]); in b43_radio_2064_channel_setup()
99 b43_radio_write(dev, 0x12b, save[1]); in b43_radio_2064_channel_setup()
102 /* brcmsmac uses outdated 0x3 for 0x038 */ in b43_radio_2064_channel_setup()
103 b43_radio_write(dev, 0x038, 0x0); in b43_radio_2064_channel_setup()
104 b43_radio_write(dev, 0x091, 0x7); in b43_radio_2064_channel_setup()
112 b43_radio_write(dev, 0x09c, 0x0020); in b43_radio_2064_init()
113 b43_radio_write(dev, 0x105, 0x0008); in b43_radio_2064_init()
117 b43_radio_write(dev, 0x032, 0x0062); in b43_radio_2064_init()
118 b43_radio_write(dev, 0x033, 0x0019); in b43_radio_2064_init()
119 b43_radio_write(dev, 0x090, 0x0010); in b43_radio_2064_init()
120 b43_radio_write(dev, 0x010, 0x0000); in b43_radio_2064_init()
122 b43_radio_write(dev, 0x060, 0x007f); in b43_radio_2064_init()
123 b43_radio_write(dev, 0x061, 0x0072); in b43_radio_2064_init()
124 b43_radio_write(dev, 0x062, 0x007f); in b43_radio_2064_init()
126 b43_radio_write(dev, 0x01d, 0x0002); in b43_radio_2064_init()
127 b43_radio_write(dev, 0x01e, 0x0006); in b43_radio_2064_init()
129 b43_phy_write(dev, 0x4ea, 0x4688); in b43_radio_2064_init()
130 b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2); in b43_radio_2064_init()
131 b43_phy_mask(dev, 0x4eb, ~0x01c0); in b43_radio_2064_init()
132 b43_phy_maskset(dev, 0x46a, 0xff00, 0x19); in b43_radio_2064_init()
134 b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0); in b43_radio_2064_init()
136 b43_radio_mask(dev, 0x05b, (u16) ~0xff02); in b43_radio_2064_init()
137 b43_radio_set(dev, 0x004, 0x40); in b43_radio_2064_init()
138 b43_radio_set(dev, 0x120, 0x10); in b43_radio_2064_init()
139 b43_radio_set(dev, 0x078, 0x80); in b43_radio_2064_init()
140 b43_radio_set(dev, 0x129, 0x2); in b43_radio_2064_init()
141 b43_radio_set(dev, 0x057, 0x1); in b43_radio_2064_init()
142 b43_radio_set(dev, 0x05b, 0x2); in b43_radio_2064_init()
145 b43_radio_read(dev, 0x05c); in b43_radio_2064_init()
147 b43_radio_mask(dev, 0x05b, (u16) ~0xff02); in b43_radio_2064_init()
148 b43_radio_mask(dev, 0x057, (u16) ~0xff01); in b43_radio_2064_init()
150 b43_phy_write(dev, 0x933, 0x2d6b); in b43_radio_2064_init()
151 b43_phy_write(dev, 0x934, 0x2d6b); in b43_radio_2064_init()
152 b43_phy_write(dev, 0x935, 0x2d6b); in b43_radio_2064_init()
153 b43_phy_write(dev, 0x936, 0x2d6b); in b43_radio_2064_init()
154 b43_phy_write(dev, 0x937, 0x016b); in b43_radio_2064_init()
156 b43_radio_mask(dev, 0x057, (u16) ~0xff02); in b43_radio_2064_init()
157 b43_radio_write(dev, 0x0c2, 0x006f); in b43_radio_2064_init()
170 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1); in b43_phy_lcn_afe_set_unset()
171 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1); in b43_phy_lcn_afe_set_unset()
173 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1); in b43_phy_lcn_afe_set_unset()
174 b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1); in b43_phy_lcn_afe_set_unset()
183 return (b43_phy_read(dev, 0x4fb) & 0x7f00) >> 8; in b43_phy_lcn_get_pa_gain()
191 dac_ctrl = b43_phy_read(dev, 0x439); in b43_phy_lcn_set_dac_gain()
192 dac_ctrl = dac_ctrl & 0xc7f; in b43_phy_lcn_set_dac_gain()
194 b43_phy_maskset(dev, 0x439, ~0xfff, dac_ctrl); in b43_phy_lcn_set_dac_gain()
200 b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x57), m0 << 8); in b43_phy_lcn_set_bbmult()
209 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340); in b43_phy_lcn_clear_tx_power_offsets()
210 for (i = 0; i < 30; i++) { in b43_phy_lcn_clear_tx_power_offsets()
211 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0); in b43_phy_lcn_clear_tx_power_offsets()
212 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0); in b43_phy_lcn_clear_tx_power_offsets()
216 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80); in b43_phy_lcn_clear_tx_power_offsets()
217 for (i = 0; i < 64; i++) { in b43_phy_lcn_clear_tx_power_offsets()
218 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0); in b43_phy_lcn_clear_tx_power_offsets()
219 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0); in b43_phy_lcn_clear_tx_power_offsets()
226 b43_radio_write(dev, 0x11c, 0); in b43_phy_lcn_rev0_baseband_init()
228 b43_phy_write(dev, 0x43b, 0); in b43_phy_lcn_rev0_baseband_init()
229 b43_phy_write(dev, 0x43c, 0); in b43_phy_lcn_rev0_baseband_init()
230 b43_phy_write(dev, 0x44c, 0); in b43_phy_lcn_rev0_baseband_init()
231 b43_phy_write(dev, 0x4e6, 0); in b43_phy_lcn_rev0_baseband_init()
232 b43_phy_write(dev, 0x4f9, 0); in b43_phy_lcn_rev0_baseband_init()
233 b43_phy_write(dev, 0x4b0, 0); in b43_phy_lcn_rev0_baseband_init()
234 b43_phy_write(dev, 0x938, 0); in b43_phy_lcn_rev0_baseband_init()
235 b43_phy_write(dev, 0x4b0, 0); in b43_phy_lcn_rev0_baseband_init()
236 b43_phy_write(dev, 0x44e, 0); in b43_phy_lcn_rev0_baseband_init()
238 b43_phy_set(dev, 0x567, 0x03); in b43_phy_lcn_rev0_baseband_init()
240 b43_phy_set(dev, 0x44a, 0x44); in b43_phy_lcn_rev0_baseband_init()
241 b43_phy_write(dev, 0x44a, 0x80); in b43_phy_lcn_rev0_baseband_init()
245 b43_phy_maskset(dev, 0x634, ~0xff, 0xc); in b43_phy_lcn_rev0_baseband_init()
247 b43_phy_maskset(dev, 0x634, ~0xff, 0xa); in b43_phy_lcn_rev0_baseband_init()
248 b43_phy_write(dev, 0x910, 0x1); in b43_phy_lcn_rev0_baseband_init()
251 b43_phy_write(dev, 0x910, 0x1); in b43_phy_lcn_rev0_baseband_init()
253 b43_phy_maskset(dev, 0x448, ~0x300, 0x100); in b43_phy_lcn_rev0_baseband_init()
254 b43_phy_maskset(dev, 0x608, ~0xff, 0x17); in b43_phy_lcn_rev0_baseband_init()
255 b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea); in b43_phy_lcn_rev0_baseband_init()
261 b43_phy_set(dev, 0x805, 0x1); in b43_phy_lcn_bu_tweaks()
263 b43_phy_maskset(dev, 0x42f, ~0x7, 0x3); in b43_phy_lcn_bu_tweaks()
264 b43_phy_maskset(dev, 0x030, ~0x7, 0x3); in b43_phy_lcn_bu_tweaks()
266 b43_phy_write(dev, 0x414, 0x1e10); in b43_phy_lcn_bu_tweaks()
267 b43_phy_write(dev, 0x415, 0x0640); in b43_phy_lcn_bu_tweaks()
269 b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700); in b43_phy_lcn_bu_tweaks()
271 b43_phy_set(dev, 0x44a, 0x44); in b43_phy_lcn_bu_tweaks()
272 b43_phy_write(dev, 0x44a, 0x80); in b43_phy_lcn_bu_tweaks()
274 b43_phy_maskset(dev, 0x434, ~0xff, 0xfd); in b43_phy_lcn_bu_tweaks()
275 b43_phy_maskset(dev, 0x420, ~0xff, 0x10); in b43_phy_lcn_bu_tweaks()
277 if (dev->dev->bus_sprom->board_rev >= 0x1204) in b43_phy_lcn_bu_tweaks()
278 b43_radio_set(dev, 0x09b, 0xf0); in b43_phy_lcn_bu_tweaks()
280 b43_phy_write(dev, 0x7d6, 0x0902); in b43_phy_lcn_bu_tweaks()
282 b43_phy_maskset(dev, 0x429, ~0xf, 0x9); in b43_phy_lcn_bu_tweaks()
283 b43_phy_maskset(dev, 0x429, ~(0x3f << 4), 0xe << 4); in b43_phy_lcn_bu_tweaks()
286 b43_phy_maskset(dev, 0x423, ~0xff, 0x46); in b43_phy_lcn_bu_tweaks()
287 b43_phy_maskset(dev, 0x411, ~0xff, 1); in b43_phy_lcn_bu_tweaks()
288 b43_phy_set(dev, 0x434, 0xff); /* FIXME: update to wl */ in b43_phy_lcn_bu_tweaks()
290 /* TODO: wl operates on PHY 0x416, brcmsmac is outdated here */ in b43_phy_lcn_bu_tweaks()
292 b43_phy_maskset(dev, 0x656, ~0xf, 2); in b43_phy_lcn_bu_tweaks()
293 b43_phy_set(dev, 0x44d, 4); in b43_phy_lcn_bu_tweaks()
295 b43_radio_set(dev, 0x0f7, 0x4); in b43_phy_lcn_bu_tweaks()
296 b43_radio_mask(dev, 0x0f1, ~0x3); in b43_phy_lcn_bu_tweaks()
297 b43_radio_maskset(dev, 0x0f2, ~0xf8, 0x90); in b43_phy_lcn_bu_tweaks()
298 b43_radio_maskset(dev, 0x0f3, ~0x3, 0x2); in b43_phy_lcn_bu_tweaks()
299 b43_radio_maskset(dev, 0x0f3, ~0xf0, 0xa0); in b43_phy_lcn_bu_tweaks()
301 b43_radio_set(dev, 0x11f, 0x2); in b43_phy_lcn_bu_tweaks()
319 { 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 }, in b43_phy_lcn_sense_setup()
320 { 0x025, 0 }, { 0x112, 0 }, in b43_phy_lcn_sense_setup()
323 { 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 }, in b43_phy_lcn_sense_setup()
324 { 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 }, in b43_phy_lcn_sense_setup()
325 { 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 }, in b43_phy_lcn_sense_setup()
326 { 0x40d, 0 }, { 0x4a2, 0 }, in b43_phy_lcn_sense_setup()
333 for (i = 0; i < 6; i++) in b43_phy_lcn_sense_setup()
335 save_radio_regs[i][0]); in b43_phy_lcn_sense_setup()
336 for (i = 0; i < 14; i++) in b43_phy_lcn_sense_setup()
337 save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]); in b43_phy_lcn_sense_setup()
339 save_radio_4a4 = b43_radio_read(dev, 0x4a4); in b43_phy_lcn_sense_setup()
345 b43_radio_set(dev, 0x007, 0x1); in b43_phy_lcn_sense_setup()
346 b43_radio_set(dev, 0x0ff, 0x10); in b43_phy_lcn_sense_setup()
347 b43_radio_set(dev, 0x11f, 0x4); in b43_phy_lcn_sense_setup()
349 b43_phy_mask(dev, 0x503, ~0x1); in b43_phy_lcn_sense_setup()
350 b43_phy_mask(dev, 0x503, ~0x4); in b43_phy_lcn_sense_setup()
351 b43_phy_mask(dev, 0x4a4, ~0x4000); in b43_phy_lcn_sense_setup()
352 b43_phy_mask(dev, 0x4a4, (u16) ~0x8000); in b43_phy_lcn_sense_setup()
353 b43_phy_mask(dev, 0x4d0, ~0x20); in b43_phy_lcn_sense_setup()
354 b43_phy_set(dev, 0x4a5, 0xff); in b43_phy_lcn_sense_setup()
355 b43_phy_maskset(dev, 0x4a5, ~0x7000, 0x5000); in b43_phy_lcn_sense_setup()
356 b43_phy_mask(dev, 0x4a5, ~0x700); in b43_phy_lcn_sense_setup()
357 b43_phy_maskset(dev, 0x40d, ~0xff, 64); in b43_phy_lcn_sense_setup()
358 b43_phy_maskset(dev, 0x40d, ~0x700, 0x600); in b43_phy_lcn_sense_setup()
359 b43_phy_maskset(dev, 0x4a2, ~0xff, 64); in b43_phy_lcn_sense_setup()
360 b43_phy_maskset(dev, 0x4a2, ~0x700, 0x600); in b43_phy_lcn_sense_setup()
361 b43_phy_maskset(dev, 0x4d9, ~0x70, 0x20); in b43_phy_lcn_sense_setup()
362 b43_phy_maskset(dev, 0x4d9, ~0x700, 0x300); in b43_phy_lcn_sense_setup()
363 b43_phy_maskset(dev, 0x4d9, ~0x7000, 0x1000); in b43_phy_lcn_sense_setup()
364 b43_phy_mask(dev, 0x4da, ~0x1000); in b43_phy_lcn_sense_setup()
365 b43_phy_set(dev, 0x4da, 0x2000); in b43_phy_lcn_sense_setup()
366 b43_phy_set(dev, 0x4a6, 0x8000); in b43_phy_lcn_sense_setup()
368 b43_radio_write(dev, 0x025, 0xc); in b43_phy_lcn_sense_setup()
369 b43_radio_set(dev, 0x005, 0x8); in b43_phy_lcn_sense_setup()
370 b43_phy_set(dev, 0x938, 0x4); in b43_phy_lcn_sense_setup()
371 b43_phy_set(dev, 0x939, 0x4); in b43_phy_lcn_sense_setup()
372 b43_phy_set(dev, 0x4a4, 0x1000); in b43_phy_lcn_sense_setup()
375 b43_lcntab_write(dev, B43_LCNTAB16(0x8, 0x6), 0x640); in b43_phy_lcn_sense_setup()
379 b43_phy_set(dev, 0x4d7, 0x8); in b43_phy_lcn_sense_setup()
380 b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x1000); in b43_phy_lcn_sense_setup()
382 auxpga_vmidfine = 0x4; in b43_phy_lcn_sense_setup()
384 b43_radio_set(dev, 0x082, 0x20); in b43_phy_lcn_sense_setup()
387 b43_phy_set(dev, 0x4d7, 0x8); in b43_phy_lcn_sense_setup()
388 b43_phy_maskset(dev, 0x4d7, ~0x7000, 0x3000); in b43_phy_lcn_sense_setup()
390 auxpga_vmidfine = 0xa; in b43_phy_lcn_sense_setup()
394 auxpga_vmid = (0x200 | (auxpga_vmidcourse << 4) | auxpga_vmidfine); in b43_phy_lcn_sense_setup()
396 b43_phy_set(dev, 0x4d8, 0x1); in b43_phy_lcn_sense_setup()
397 b43_phy_maskset(dev, 0x4d8, ~(0x3ff << 2), auxpga_vmid << 2); in b43_phy_lcn_sense_setup()
398 b43_phy_set(dev, 0x4d8, 0x2); in b43_phy_lcn_sense_setup()
399 b43_phy_maskset(dev, 0x4d8, ~(0x7 << 12), auxpga_gain << 12); in b43_phy_lcn_sense_setup()
400 b43_phy_set(dev, 0x4d0, 0x20); in b43_phy_lcn_sense_setup()
401 b43_radio_write(dev, 0x112, 0x6); in b43_phy_lcn_sense_setup()
405 if (!(b43_phy_read(dev, 0x476) & 0x8000)) in b43_phy_lcn_sense_setup()
409 for (i = 0; i < 6; i++) in b43_phy_lcn_sense_setup()
410 b43_radio_write(dev, save_radio_regs[i][0], in b43_phy_lcn_sense_setup()
412 for (i = 0; i < 14; i++) in b43_phy_lcn_sense_setup()
413 b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]); in b43_phy_lcn_sense_setup()
415 b43_radio_write(dev, 0x4a4, save_radio_4a4); in b43_phy_lcn_sense_setup()
426 u16 phy_regs[] = { 0x910, 0x91e, 0x91f, 0x924, 0x925, 0x926, 0x920, in b43_phy_lcn_load_tx_iir_cck_filter()
427 0x921, 0x927, 0x928, 0x929, 0x922, 0x923, 0x930, in b43_phy_lcn_load_tx_iir_cck_filter()
428 0x931, 0x932 }; in b43_phy_lcn_load_tx_iir_cck_filter()
432 { 0, { 1, 415, 1874, 64, 128, 64, 792, 1656, 64, 128, 64, 778, in b43_phy_lcn_load_tx_iir_cck_filter()
462 for (i = 0; i < ARRAY_SIZE(tx_iir_filters_cck); i++) { in b43_phy_lcn_load_tx_iir_cck_filter()
464 for (j = 0; j < 16; j++) in b43_phy_lcn_load_tx_iir_cck_filter()
478 u16 phy_regs[] = { 0x90f, 0x900, 0x901, 0x906, 0x907, 0x908, 0x902, in b43_phy_lcn_load_tx_iir_ofdm_filter()
479 0x903, 0x909, 0x90a, 0x90b, 0x904, 0x905, 0x90c, in b43_phy_lcn_load_tx_iir_ofdm_filter()
480 0x90d, 0x90e }; in b43_phy_lcn_load_tx_iir_ofdm_filter()
482 { 0, { 0, 0xa2, 0x0, 0x100, 0x100, 0x0, 0x0, 0x0, 0x100, 0x0, in b43_phy_lcn_load_tx_iir_ofdm_filter()
483 0x0, 0x278, 0xfea0, 0x80, 0x100, 0x80 } }, in b43_phy_lcn_load_tx_iir_ofdm_filter()
484 { 1, { 0, 374, 0xFF79, 16, 32, 16, 799, 0xFE74, 50, 32, 50, 750, in b43_phy_lcn_load_tx_iir_ofdm_filter()
485 0xFE2B, 212, 0xFFCE, 212 } }, in b43_phy_lcn_load_tx_iir_ofdm_filter()
486 { 2, { 0, 375, 0xFF16, 37, 76, 37, 799, 0xFE74, 32, 20, 32, 748, in b43_phy_lcn_load_tx_iir_ofdm_filter()
487 0xFEF2, 128, 0xFFE2, 128 } }, in b43_phy_lcn_load_tx_iir_ofdm_filter()
490 for (i = 0; i < ARRAY_SIZE(tx_iir_filters_ofdm); i++) { in b43_phy_lcn_load_tx_iir_ofdm_filter()
492 for (j = 0; j < 16; j++) in b43_phy_lcn_load_tx_iir_ofdm_filter()
505 b43_phy_maskset(dev, 0x4b0, ~(0x1 << 7), enable << 7); in b43_phy_lcn_set_tx_gain_override()
506 b43_phy_maskset(dev, 0x4b0, ~(0x1 << 14), enable << 14); in b43_phy_lcn_set_tx_gain_override()
507 b43_phy_maskset(dev, 0x43b, ~(0x1 << 6), enable << 6); in b43_phy_lcn_set_tx_gain_override()
516 b43_phy_write(dev, 0x4b5, in b43_phy_lcn_set_tx_gain()
518 b43_phy_maskset(dev, 0x4fb, ~0x7fff, in b43_phy_lcn_set_tx_gain()
520 b43_phy_write(dev, 0x4fc, in b43_phy_lcn_set_tx_gain()
522 b43_phy_maskset(dev, 0x4fd, ~0x7fff, in b43_phy_lcn_set_tx_gain()
542 tx_gains.dac_gain = 0; in b43_phy_lcn_tx_pwr_ctl_init()
548 tx_gains.dac_gain = 0; in b43_phy_lcn_tx_pwr_ctl_init()
566 b43_phy_write(dev, 0x942, 0x7); in b43_phy_lcn_txrx_spur_avoidance_mode()
567 b43_phy_write(dev, 0x93b, ((1 << 13) + 23)); in b43_phy_lcn_txrx_spur_avoidance_mode()
568 b43_phy_write(dev, 0x93c, ((1 << 13) + 1989)); in b43_phy_lcn_txrx_spur_avoidance_mode()
570 b43_phy_write(dev, 0x44a, 0x084); in b43_phy_lcn_txrx_spur_avoidance_mode()
571 b43_phy_write(dev, 0x44a, 0x080); in b43_phy_lcn_txrx_spur_avoidance_mode()
572 b43_phy_write(dev, 0x6d3, 0x2222); in b43_phy_lcn_txrx_spur_avoidance_mode()
573 b43_phy_write(dev, 0x6d3, 0x2220); in b43_phy_lcn_txrx_spur_avoidance_mode()
575 b43_phy_write(dev, 0x942, 0x0); in b43_phy_lcn_txrx_spur_avoidance_mode()
576 b43_phy_write(dev, 0x93b, ((0 << 13) + 23)); in b43_phy_lcn_txrx_spur_avoidance_mode()
577 b43_phy_write(dev, 0x93c, ((0 << 13) + 1989)); in b43_phy_lcn_txrx_spur_avoidance_mode()
591 b43_phy_maskset(dev, 0x448, ~0x300, (channel == 14) ? 0x200 : 0x100); in b43_phy_lcn_set_channel_tweaks()
595 bcma_chipco_pll_write(cc, 0x2, 0x03000c04); in b43_phy_lcn_set_channel_tweaks()
596 bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x0); in b43_phy_lcn_set_channel_tweaks()
597 bcma_chipco_pll_write(cc, 0x4, 0x200005c0); in b43_phy_lcn_set_channel_tweaks()
599 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400); in b43_phy_lcn_set_channel_tweaks()
601 b43_phy_write(dev, 0x942, 0); in b43_phy_lcn_set_channel_tweaks()
604 b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1b00); in b43_phy_lcn_set_channel_tweaks()
605 b43_phy_write(dev, 0x425, 0x5907); in b43_phy_lcn_set_channel_tweaks()
607 bcma_chipco_pll_write(cc, 0x2, 0x03140c04); in b43_phy_lcn_set_channel_tweaks()
608 bcma_chipco_pll_maskset(cc, 0x3, 0x00ffffff, 0x333333); in b43_phy_lcn_set_channel_tweaks()
609 bcma_chipco_pll_write(cc, 0x4, 0x202c2820); in b43_phy_lcn_set_channel_tweaks()
611 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 0x400); in b43_phy_lcn_set_channel_tweaks()
613 b43_phy_write(dev, 0x942, 0); in b43_phy_lcn_set_channel_tweaks()
616 b43_phy_maskset(dev, 0x424, (u16) ~0xff00, 0x1f00); in b43_phy_lcn_set_channel_tweaks()
617 b43_phy_write(dev, 0x425, 0x590a); in b43_phy_lcn_set_channel_tweaks()
620 b43_phy_set(dev, 0x44a, 0x44); in b43_phy_lcn_set_channel_tweaks()
621 b43_phy_write(dev, 0x44a, 0x80); in b43_phy_lcn_set_channel_tweaks()
637 b43_phy_set(dev, 0x44a, 0x44); in b43_phy_lcn_set_channel()
638 b43_phy_write(dev, 0x44a, 0x80); in b43_phy_lcn_set_channel()
645 b43_phy_write(dev, 0x657, sfo_cfg[channel->hw_value - 1][0]); in b43_phy_lcn_set_channel()
646 b43_phy_write(dev, 0x658, sfo_cfg[channel->hw_value - 1][1]); in b43_phy_lcn_set_channel()
649 b43_phy_maskset(dev, 0x448, ~(0x3 << 8), (2) << 8); in b43_phy_lcn_set_channel()
652 b43_phy_maskset(dev, 0x448, ~(0x3 << 8), (1) << 8); in b43_phy_lcn_set_channel()
656 /* brcmsmac uses filter_type 2, we follow wl with 0 */ in b43_phy_lcn_set_channel()
657 b43_phy_lcn_load_tx_iir_ofdm_filter(dev, 0); in b43_phy_lcn_set_channel()
659 b43_phy_maskset(dev, 0x4eb, ~(0x7 << 3), 0x1 << 3); in b43_phy_lcn_set_channel()
661 return 0; in b43_phy_lcn_set_channel()
677 return 0; in b43_phy_lcn_op_allocate()
694 memset(phy_lcn, 0, sizeof(*phy_lcn)); in b43_phy_lcn_op_prepare_structs()
702 b43_phy_set(dev, 0x44a, 0x80); in b43_phy_lcn_op_init()
703 b43_phy_mask(dev, 0x44a, 0x7f); in b43_phy_lcn_op_init()
704 b43_phy_set(dev, 0x6d1, 0x80); in b43_phy_lcn_op_init()
705 b43_phy_write(dev, 0x6d0, 0x7); in b43_phy_lcn_op_init()
709 b43_phy_write(dev, 0x60a, 0xa0); in b43_phy_lcn_op_init()
710 b43_phy_write(dev, 0x46a, 0x19); in b43_phy_lcn_op_init()
711 b43_phy_maskset(dev, 0x663, 0xFF00, 0x64); in b43_phy_lcn_op_init()
718 if (dev->phy.radio_ver == 0x2064) in b43_phy_lcn_op_init()
728 bcma_chipco_regctl_maskset(cc, 0, 0xf, 0x9); in b43_phy_lcn_op_init()
729 bcma_chipco_chipctl_maskset(cc, 0, 0, 0x03cddddd); in b43_phy_lcn_op_init()
733 b43_phy_set(dev, 0x448, 0x4000); in b43_phy_lcn_op_init()
735 b43_phy_mask(dev, 0x448, ~0x4000); in b43_phy_lcn_op_init()
739 return 0; in b43_phy_lcn_op_init()
749 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00); in b43_phy_lcn_op_software_rfkill()
750 b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00); in b43_phy_lcn_op_software_rfkill()
752 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00); in b43_phy_lcn_op_software_rfkill()
753 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2); in b43_phy_lcn_op_software_rfkill()
754 b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808); in b43_phy_lcn_op_software_rfkill()
756 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8); in b43_phy_lcn_op_software_rfkill()
757 b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8); in b43_phy_lcn_op_software_rfkill()
759 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00); in b43_phy_lcn_op_software_rfkill()
760 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808); in b43_phy_lcn_op_software_rfkill()
761 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8); in b43_phy_lcn_op_software_rfkill()
768 b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7); in b43_phy_lcn_op_switch_analog()
770 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7); in b43_phy_lcn_op_switch_analog()
771 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7); in b43_phy_lcn_op_switch_analog()
823 /* LCN-PHY needs 0x200 for read access */ in b43_phy_lcn_op_radio_read()
824 reg |= 0x200; in b43_phy_lcn_op_radio_read()