Lines Matching refs:wil
75 static void wil6210_mask_irq_tx(struct wil6210_priv *wil) in wil6210_mask_irq_tx() argument
77 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_tx()
81 static void wil6210_mask_irq_tx_edma(struct wil6210_priv *wil) in wil6210_mask_irq_tx_edma() argument
83 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_tx_edma()
87 static void wil6210_mask_irq_rx(struct wil6210_priv *wil) in wil6210_mask_irq_rx() argument
89 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_rx()
93 static void wil6210_mask_irq_rx_edma(struct wil6210_priv *wil) in wil6210_mask_irq_rx_edma() argument
95 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_rx_edma()
99 static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp) in wil6210_mask_irq_misc() argument
101 wil_dbg_irq(wil, "mask_irq_misc: mask_halp(%s)\n", in wil6210_mask_irq_misc()
104 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_irq_misc()
108 void wil6210_mask_halp(struct wil6210_priv *wil) in wil6210_mask_halp() argument
110 wil_dbg_irq(wil, "mask_halp\n"); in wil6210_mask_halp()
112 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS), in wil6210_mask_halp()
116 static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) in wil6210_mask_irq_pseudo() argument
118 wil_dbg_irq(wil, "mask_irq_pseudo\n"); in wil6210_mask_irq_pseudo()
120 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE); in wil6210_mask_irq_pseudo()
122 clear_bit(wil_status_irqen, wil->status); in wil6210_mask_irq_pseudo()
125 void wil6210_unmask_irq_tx(struct wil6210_priv *wil) in wil6210_unmask_irq_tx() argument
127 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_tx()
131 void wil6210_unmask_irq_tx_edma(struct wil6210_priv *wil) in wil6210_unmask_irq_tx_edma() argument
133 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_tx_edma()
137 void wil6210_unmask_irq_rx(struct wil6210_priv *wil) in wil6210_unmask_irq_rx() argument
139 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; in wil6210_unmask_irq_rx()
141 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_rx()
145 void wil6210_unmask_irq_rx_edma(struct wil6210_priv *wil) in wil6210_unmask_irq_rx_edma() argument
147 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_rx_edma()
151 static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp) in wil6210_unmask_irq_misc() argument
153 wil_dbg_irq(wil, "unmask_irq_misc: unmask_halp(%s)\n", in wil6210_unmask_irq_misc()
156 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_irq_misc()
160 static void wil6210_unmask_halp(struct wil6210_priv *wil) in wil6210_unmask_halp() argument
162 wil_dbg_irq(wil, "unmask_halp\n"); in wil6210_unmask_halp()
164 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC), in wil6210_unmask_halp()
168 static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) in wil6210_unmask_irq_pseudo() argument
170 wil_dbg_irq(wil, "unmask_irq_pseudo\n"); in wil6210_unmask_irq_pseudo()
172 set_bit(wil_status_irqen, wil->status); in wil6210_unmask_irq_pseudo()
174 wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK); in wil6210_unmask_irq_pseudo()
177 void wil_mask_irq(struct wil6210_priv *wil) in wil_mask_irq() argument
179 wil_dbg_irq(wil, "mask_irq\n"); in wil_mask_irq()
181 wil6210_mask_irq_tx(wil); in wil_mask_irq()
182 wil6210_mask_irq_tx_edma(wil); in wil_mask_irq()
183 wil6210_mask_irq_rx(wil); in wil_mask_irq()
184 wil6210_mask_irq_rx_edma(wil); in wil_mask_irq()
185 wil6210_mask_irq_misc(wil, true); in wil_mask_irq()
186 wil6210_mask_irq_pseudo(wil); in wil_mask_irq()
189 void wil_unmask_irq(struct wil6210_priv *wil) in wil_unmask_irq() argument
191 wil_dbg_irq(wil, "unmask_irq\n"); in wil_unmask_irq()
193 wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
195 wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
197 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
199 wil_w(wil, RGF_INT_GEN_TX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
201 wil_w(wil, RGF_INT_GEN_RX_ICR + offsetof(struct RGF_ICR, ICC), in wil_unmask_irq()
204 wil6210_unmask_irq_pseudo(wil); in wil_unmask_irq()
205 if (wil->use_enhanced_dma_hw) { in wil_unmask_irq()
206 wil6210_unmask_irq_tx_edma(wil); in wil_unmask_irq()
207 wil6210_unmask_irq_rx_edma(wil); in wil_unmask_irq()
209 wil6210_unmask_irq_tx(wil); in wil_unmask_irq()
210 wil6210_unmask_irq_rx(wil); in wil_unmask_irq()
212 wil6210_unmask_irq_misc(wil, true); in wil_unmask_irq()
215 void wil_configure_interrupt_moderation_edma(struct wil6210_priv *wil) in wil_configure_interrupt_moderation_edma() argument
219 wil_s(wil, RGF_INT_GEN_IDLE_TIME_LIMIT, WIL_EDMA_IDLE_TIME_LIMIT_USEC); in wil_configure_interrupt_moderation_edma()
221 wil_s(wil, RGF_INT_GEN_TIME_UNIT_LIMIT, WIL_EDMA_TIME_UNIT_CLK_CYCLES); in wil_configure_interrupt_moderation_edma()
224 moderation = wil->rx_max_burst_duration | in wil_configure_interrupt_moderation_edma()
226 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_0, moderation); in wil_configure_interrupt_moderation_edma()
227 wil_w(wil, RGF_INT_CTRL_INT_GEN_CFG_1, moderation); in wil_configure_interrupt_moderation_edma()
232 wil_c(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1FE); in wil_configure_interrupt_moderation_edma()
233 wil_s(wil, RGF_INT_COUNT_ON_SPECIAL_EVT, 0x1); in wil_configure_interrupt_moderation_edma()
236 void wil_configure_interrupt_moderation(struct wil6210_priv *wil) in wil_configure_interrupt_moderation() argument
238 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr; in wil_configure_interrupt_moderation()
240 wil_dbg_irq(wil, "configure_interrupt_moderation\n"); in wil_configure_interrupt_moderation()
249 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
250 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
251 wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
252 wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
254 wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, in wil_configure_interrupt_moderation()
258 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
259 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
260 wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
261 wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
263 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN | in wil_configure_interrupt_moderation()
267 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
268 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
269 wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
270 wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
272 wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, in wil_configure_interrupt_moderation()
276 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR); in wil_configure_interrupt_moderation()
277 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
278 wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n", in wil_configure_interrupt_moderation()
279 wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
281 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN | in wil_configure_interrupt_moderation()
287 struct wil6210_priv *wil = cookie; in wil6210_irq_rx() local
291 wil6210_mask_irq_rx(wil); in wil6210_irq_rx()
293 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
298 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx()
301 wil_err_ratelimited(wil, "spurious IRQ: RX\n"); in wil6210_irq_rx()
302 wil6210_unmask_irq_rx(wil); in wil6210_irq_rx()
314 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n", in wil6210_irq_rx()
319 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx()
320 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx()
321 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); in wil6210_irq_rx()
323 napi_schedule(&wil->napi_rx); in wil6210_irq_rx()
326 wil, in wil6210_irq_rx()
330 wil_err_ratelimited(wil, "Got Rx interrupt while in reset\n"); in wil6210_irq_rx()
335 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx()
339 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx()
342 wil6210_unmask_irq_rx(wil); in wil6210_irq_rx()
349 struct wil6210_priv *wil = cookie; in wil6210_irq_rx_edma() local
353 wil6210_mask_irq_rx_edma(wil); in wil6210_irq_rx_edma()
355 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
360 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx_edma()
363 wil_err(wil, "spurious IRQ: RX\n"); in wil6210_irq_rx_edma()
364 wil6210_unmask_irq_rx_edma(wil); in wil6210_irq_rx_edma()
369 wil_dbg_irq(wil, "RX status ring\n"); in wil6210_irq_rx_edma()
371 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx_edma()
372 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx_edma()
373 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n"); in wil6210_irq_rx_edma()
375 napi_schedule(&wil->napi_rx); in wil6210_irq_rx_edma()
377 wil_err(wil, in wil6210_irq_rx_edma()
381 wil_err(wil, "Got Rx interrupt while in reset\n"); in wil6210_irq_rx_edma()
386 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx_edma()
390 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx_edma()
393 wil6210_unmask_irq_rx_edma(wil); in wil6210_irq_rx_edma()
400 struct wil6210_priv *wil = cookie; in wil6210_irq_tx_edma() local
404 wil6210_mask_irq_tx_edma(wil); in wil6210_irq_tx_edma()
406 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
411 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx_edma()
414 wil_err(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx_edma()
415 wil6210_unmask_irq_tx_edma(wil); in wil6210_irq_tx_edma()
420 wil_dbg_irq(wil, "TX status ring\n"); in wil6210_irq_tx_edma()
422 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx_edma()
423 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx_edma()
425 napi_schedule(&wil->napi_tx); in wil6210_irq_tx_edma()
427 wil_err(wil, "Got Tx status ring IRQ while in reset\n"); in wil6210_irq_tx_edma()
432 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); in wil6210_irq_tx_edma()
436 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx_edma()
439 wil6210_unmask_irq_tx_edma(wil); in wil6210_irq_tx_edma()
446 struct wil6210_priv *wil = cookie; in wil6210_irq_tx() local
450 wil6210_mask_irq_tx(wil); in wil6210_irq_tx()
452 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
457 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx()
460 wil_err_ratelimited(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx()
461 wil6210_unmask_irq_tx(wil); in wil6210_irq_tx()
466 wil_dbg_irq(wil, "TX done\n"); in wil6210_irq_tx()
470 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx()
471 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx()
473 napi_schedule(&wil->napi_tx); in wil6210_irq_tx()
475 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n"); in wil6210_irq_tx()
480 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", in wil6210_irq_tx()
485 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx()
488 wil6210_unmask_irq_tx(wil); in wil6210_irq_tx()
493 static void wil_notify_fw_error(struct wil6210_priv *wil) in wil_notify_fw_error() argument
495 struct device *dev = &wil->main_ndev->dev; in wil_notify_fw_error()
501 wil_err(wil, "Notify about firmware error\n"); in wil_notify_fw_error()
505 static void wil_cache_mbox_regs(struct wil6210_priv *wil) in wil_cache_mbox_regs() argument
508 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
510 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); in wil_cache_mbox_regs()
511 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); in wil_cache_mbox_regs()
514 static bool wil_validate_mbox_regs(struct wil6210_priv *wil) in wil_validate_mbox_regs() argument
519 if (wil->mbox_ctl.rx.entry_size < min_size) { in wil_validate_mbox_regs()
520 wil_err(wil, "rx mbox entry too small (%d)\n", in wil_validate_mbox_regs()
521 wil->mbox_ctl.rx.entry_size); in wil_validate_mbox_regs()
524 if (wil->mbox_ctl.tx.entry_size < min_size) { in wil_validate_mbox_regs()
525 wil_err(wil, "tx mbox entry too small (%d)\n", in wil_validate_mbox_regs()
526 wil->mbox_ctl.tx.entry_size); in wil_validate_mbox_regs()
535 struct wil6210_priv *wil = cookie; in wil6210_irq_misc() local
538 wil6210_mask_irq_misc(wil, false); in wil6210_irq_misc()
540 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
545 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); in wil6210_irq_misc()
548 wil_err(wil, "spurious IRQ: MISC\n"); in wil6210_irq_misc()
549 wil6210_unmask_irq_misc(wil, false); in wil6210_irq_misc()
554 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr); in wil6210_irq_misc()
556 wil_r(wil, wil->rgf_ucode_assert_code_addr); in wil6210_irq_misc()
558 wil_err(wil, in wil6210_irq_misc()
561 clear_bit(wil_status_fwready, wil->status); in wil6210_irq_misc()
570 wil_dbg_irq(wil, "IRQ: FW ready\n"); in wil6210_irq_misc()
571 wil_cache_mbox_regs(wil); in wil6210_irq_misc()
572 if (wil_validate_mbox_regs(wil)) in wil6210_irq_misc()
573 set_bit(wil_status_mbox_ready, wil->status); in wil6210_irq_misc()
583 if (wil->halp.handle_icr) { in wil6210_irq_misc()
585 wil->halp.handle_icr = false; in wil6210_irq_misc()
586 wil_dbg_irq(wil, "irq_misc: HALP IRQ invoked\n"); in wil6210_irq_misc()
587 wil6210_mask_irq_misc(wil, true); in wil6210_irq_misc()
588 complete(&wil->halp.comp); in wil6210_irq_misc()
592 wil->isr_misc = isr; in wil6210_irq_misc()
597 wil6210_unmask_irq_misc(wil, false); in wil6210_irq_misc()
604 struct wil6210_priv *wil = cookie; in wil6210_irq_misc_thread() local
605 u32 isr = wil->isr_misc; in wil6210_irq_misc_thread()
608 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); in wil6210_irq_misc_thread()
611 wil->recovery_state = fw_recovery_pending; in wil6210_irq_misc_thread()
612 wil_fw_core_dump(wil); in wil6210_irq_misc_thread()
613 wil_notify_fw_error(wil); in wil6210_irq_misc_thread()
615 if (wil->platform_ops.notify) { in wil6210_irq_misc_thread()
616 wil_err(wil, "notify platform driver about FW crash"); in wil6210_irq_misc_thread()
617 wil->platform_ops.notify(wil->platform_handle, in wil6210_irq_misc_thread()
620 wil_fw_error_recovery(wil); in wil6210_irq_misc_thread()
624 wil_dbg_irq(wil, "MBOX event\n"); in wil6210_irq_misc_thread()
625 wmi_recv_cmd(wil); in wil6210_irq_misc_thread()
630 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); in wil6210_irq_misc_thread()
632 wil->isr_misc = 0; in wil6210_irq_misc_thread()
634 wil6210_unmask_irq_misc(wil, false); in wil6210_irq_misc_thread()
639 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) { in wil6210_irq_misc_thread()
640 wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); in wil6210_irq_misc_thread()
641 wil->suspend_resp_comp = true; in wil6210_irq_misc_thread()
642 wake_up_interruptible(&wil->wq); in wil6210_irq_misc_thread()
651 struct wil6210_priv *wil = cookie; in wil6210_thread_irq() local
653 wil_dbg_irq(wil, "Thread IRQ\n"); in wil6210_thread_irq()
655 if (wil->isr_misc) in wil6210_thread_irq()
658 wil6210_unmask_irq_pseudo(wil); in wil6210_thread_irq()
660 if (wil->suspend_resp_rcvd) { in wil6210_thread_irq()
661 wil_dbg_irq(wil, "set suspend_resp_comp to true\n"); in wil6210_thread_irq()
662 wil->suspend_resp_comp = true; in wil6210_thread_irq()
663 wake_up_interruptible(&wil->wq); in wil6210_thread_irq()
675 static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) in wil6210_debug_irq_mask() argument
681 if (!test_bit(wil_status_irqen, wil->status)) { in wil6210_debug_irq_mask()
682 if (wil->use_enhanced_dma_hw) { in wil6210_debug_irq_mask()
683 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
686 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
689 imv_rx = wil_r(wil, RGF_INT_GEN_RX_ICR + in wil6210_debug_irq_mask()
691 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
694 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
697 imv_tx = wil_r(wil, RGF_INT_GEN_TX_ICR + in wil6210_debug_irq_mask()
700 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
703 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
706 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR + in wil6210_debug_irq_mask()
708 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
711 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
714 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR + in wil6210_debug_irq_mask()
717 icm_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
720 icr_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
723 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR + in wil6210_debug_irq_mask()
732 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" in wil6210_debug_irq_mask()
750 struct wil6210_priv *wil = cookie; in wil6210_hardirq() local
751 u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE); in wil6210_hardirq()
760 if (unlikely(wil6210_debug_irq_mask(wil, pseudo_cause))) in wil6210_hardirq()
764 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause); in wil6210_hardirq()
766 wil6210_mask_irq_pseudo(wil); in wil6210_hardirq()
782 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
786 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
795 wil6210_unmask_irq_pseudo(wil); in wil6210_hardirq()
800 static int wil6210_request_3msi(struct wil6210_priv *wil, int irq) in wil6210_request_3msi() argument
809 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED, in wil6210_request_3msi()
810 WIL_NAME "_tx", wil); in wil6210_request_3msi()
814 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED, in wil6210_request_3msi()
815 WIL_NAME "_rx", wil); in wil6210_request_3msi()
821 IRQF_SHARED, WIL_NAME "_misc", wil); in wil6210_request_3msi()
827 free_irq(irq + 1, wil); in wil6210_request_3msi()
829 free_irq(irq, wil); in wil6210_request_3msi()
842 void wil6210_clear_irq(struct wil6210_priv *wil) in wil6210_clear_irq() argument
844 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_clear_irq()
846 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_clear_irq()
848 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) + in wil6210_clear_irq()
850 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) + in wil6210_clear_irq()
852 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_clear_irq()
857 void wil6210_set_halp(struct wil6210_priv *wil) in wil6210_set_halp() argument
859 wil_dbg_irq(wil, "set_halp\n"); in wil6210_set_halp()
861 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS), in wil6210_set_halp()
865 void wil6210_clear_halp(struct wil6210_priv *wil) in wil6210_clear_halp() argument
867 wil_dbg_irq(wil, "clear_halp\n"); in wil6210_clear_halp()
869 wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR), in wil6210_clear_halp()
871 wil6210_unmask_halp(wil); in wil6210_clear_halp()
874 int wil6210_init_irq(struct wil6210_priv *wil, int irq) in wil6210_init_irq() argument
878 wil_dbg_misc(wil, "init_irq: %s, n_msi=%d\n", in wil6210_init_irq()
879 wil->n_msi ? "MSI" : "INTx", wil->n_msi); in wil6210_init_irq()
881 if (wil->use_enhanced_dma_hw) { in wil6210_init_irq()
882 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma; in wil6210_init_irq()
883 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma; in wil6210_init_irq()
885 wil->txrx_ops.irq_tx = wil6210_irq_tx; in wil6210_init_irq()
886 wil->txrx_ops.irq_rx = wil6210_irq_rx; in wil6210_init_irq()
889 if (wil->n_msi == 3) in wil6210_init_irq()
890 rc = wil6210_request_3msi(wil, irq); in wil6210_init_irq()
894 wil->n_msi ? 0 : IRQF_SHARED, in wil6210_init_irq()
895 WIL_NAME, wil); in wil6210_init_irq()
899 void wil6210_fini_irq(struct wil6210_priv *wil, int irq) in wil6210_fini_irq() argument
901 wil_dbg_misc(wil, "fini_irq:\n"); in wil6210_fini_irq()
903 wil_mask_irq(wil); in wil6210_fini_irq()
904 free_irq(irq, wil); in wil6210_fini_irq()
905 if (wil->n_msi == 3) { in wil6210_fini_irq()
906 free_irq(irq + 1, wil); in wil6210_fini_irq()
907 free_irq(irq + 2, wil); in wil6210_fini_irq()