Lines Matching +full:un +full:- +full:masked
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
15 * There is ISR pseudo-cause register,
16 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
48 /* configure to Clear-On-Read mode */
56 /* configure to Write-1-to-Clear mode */
122 clear_bit(wil_status_irqen, wil->status); in wil6210_mask_irq_pseudo()
139 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; in wil6210_unmask_irq_rx()
172 set_bit(wil_status_irqen, wil->status); in wil6210_unmask_irq_pseudo()
182 if (wil->use_enhanced_dma_hw) in wil_mask_irq()
185 if (wil->use_enhanced_dma_hw) in wil_mask_irq()
195 if (wil->use_enhanced_dma_hw) { in wil_unmask_irq()
209 if (wil->use_enhanced_dma_hw) { in wil_unmask_irq()
228 moderation = wil->rx_max_burst_duration | in wil_configure_interrupt_moderation_edma()
234 * (set bit 0 to 0x1 and clear bits 1-8) in wil_configure_interrupt_moderation_edma()
242 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr; in wil_configure_interrupt_moderation()
249 if (wdev->iftype == NL80211_IFTYPE_MONITOR) in wil_configure_interrupt_moderation()
254 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
256 wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
263 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
265 wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
272 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
274 wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
281 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
283 wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
297 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
313 * action is always the same - should empty the accumulated in wil6210_irq_rx()
323 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx()
324 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx()
327 napi_schedule(&wil->napi_rx); in wil6210_irq_rx()
339 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx()
343 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx()
359 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
375 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx_edma()
376 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx_edma()
379 napi_schedule(&wil->napi_rx); in wil6210_irq_rx_edma()
390 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx_edma()
394 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx_edma()
410 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
426 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx_edma()
429 napi_schedule(&wil->napi_tx); in wil6210_irq_tx_edma()
436 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); in wil6210_irq_tx_edma()
440 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx_edma()
456 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
473 isr &= ~(BIT(25) - 1UL); in wil6210_irq_tx()
474 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx()
477 napi_schedule(&wil->napi_tx); in wil6210_irq_tx()
484 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", in wil6210_irq_tx()
489 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx()
499 struct device *dev = &wil->main_ndev->dev; in wil_notify_fw_error()
506 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp); in wil_notify_fw_error()
512 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
514 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); in wil_cache_mbox_regs()
515 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); in wil_cache_mbox_regs()
523 if (wil->mbox_ctl.rx.entry_size < min_size) { in wil_validate_mbox_regs()
525 wil->mbox_ctl.rx.entry_size); in wil_validate_mbox_regs()
528 if (wil->mbox_ctl.tx.entry_size < min_size) { in wil_validate_mbox_regs()
530 wil->mbox_ctl.tx.entry_size); in wil_validate_mbox_regs()
544 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
558 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr); in wil6210_irq_misc()
560 wil_r(wil, wil->rgf_ucode_assert_code_addr); in wil6210_irq_misc()
565 clear_bit(wil_status_fwready, wil->status); in wil6210_irq_misc()
567 * do not clear @isr here - we do 2-nd part in thread in wil6210_irq_misc()
569 * in non-atomic context in wil6210_irq_misc()
577 set_bit(wil_status_mbox_ready, wil->status); in wil6210_irq_misc()
587 if (wil->halp.handle_icr) { in wil6210_irq_misc()
589 wil->halp.handle_icr = false; in wil6210_irq_misc()
592 complete(&wil->halp.comp); in wil6210_irq_misc()
596 wil->isr_misc = isr; in wil6210_irq_misc()
609 u32 isr = wil->isr_misc; in wil6210_irq_misc_thread()
615 wil->recovery_state = fw_recovery_pending; in wil6210_irq_misc_thread()
619 if (wil->platform_ops.notify) { in wil6210_irq_misc_thread()
621 wil->platform_ops.notify(wil->platform_handle, in wil6210_irq_misc_thread()
634 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); in wil6210_irq_misc_thread()
636 wil->isr_misc = 0; in wil6210_irq_misc_thread()
640 /* in non-triple MSI case, this is done inside wil6210_thread_irq in wil6210_irq_misc_thread()
643 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) { in wil6210_irq_misc_thread()
645 wil->suspend_resp_comp = true; in wil6210_irq_misc_thread()
646 wake_up_interruptible(&wil->wq); in wil6210_irq_misc_thread()
659 if (wil->isr_misc) in wil6210_thread_irq()
664 if (wil->suspend_resp_rcvd) { in wil6210_thread_irq()
666 wil->suspend_resp_comp = true; in wil6210_thread_irq()
667 wake_up_interruptible(&wil->wq); in wil6210_thread_irq()
675 * masked. It is quite rare and hard to debug.
685 if (!test_bit(wil_status_irqen, wil->status)) { in wil6210_debug_irq_mask()
686 if (wil->use_enhanced_dma_hw) { in wil6210_debug_irq_mask()
687 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
690 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
695 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
698 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
704 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
707 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
712 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
715 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
721 icm_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
724 icr_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
731 * masked in wil6210_debug_irq_mask()
736 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" in wil6210_debug_irq_mask()
745 return -EINVAL; in wil6210_debug_irq_mask()
758 * pseudo_cause is Clear-On-Read, no need to ACK in wil6210_hardirq()
774 * - hard IRQ handler called right here in wil6210_hardirq()
775 * - threaded handler called later in wil6210_hardirq()
783 * voting for wake thread - need at least 1 vote in wil6210_hardirq()
786 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
790 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
809 * - Tx in wil6210_request_3msi()
810 * - Rx in wil6210_request_3msi()
811 * - Misc in wil6210_request_3msi()
813 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED, in wil6210_request_3msi()
818 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED, in wil6210_request_3msi()
848 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_clear_irq()
850 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_clear_irq()
852 if (wil->use_enhanced_dma_hw) { in wil6210_clear_irq()
853 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) + in wil6210_clear_irq()
855 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) + in wil6210_clear_irq()
858 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_clear_irq()
885 wil->n_msi ? "MSI" : "INTx", wil->n_msi); in wil6210_init_irq()
887 if (wil->use_enhanced_dma_hw) { in wil6210_init_irq()
888 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma; in wil6210_init_irq()
889 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma; in wil6210_init_irq()
891 wil->txrx_ops.irq_tx = wil6210_irq_tx; in wil6210_init_irq()
892 wil->txrx_ops.irq_rx = wil6210_irq_rx; in wil6210_init_irq()
895 if (wil->n_msi == 3) in wil6210_init_irq()
900 wil->n_msi ? 0 : IRQF_SHARED, in wil6210_init_irq()
911 if (wil->n_msi == 3) { in wil6210_fini_irq()