Lines Matching +full:tx +full:- +full:max +full:- +full:burst
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
15 * There is ISR pseudo-cause register,
16 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
18 * TX, RX, and MISC.
48 /* configure to Clear-On-Read mode */
56 /* configure to Write-1-to-Clear mode */
122 clear_bit(wil_status_irqen, wil->status); in wil6210_mask_irq_pseudo()
139 bool unmask_rx_htrsh = atomic_read(&wil->connected_vifs) > 0; in wil6210_unmask_irq_rx()
172 set_bit(wil_status_irqen, wil->status); in wil6210_unmask_irq_pseudo()
205 if (wil->use_enhanced_dma_hw) { in wil_unmask_irq()
223 /* Update RX and TX moderation */ in wil_configure_interrupt_moderation_edma()
224 moderation = wil->rx_max_burst_duration | in wil_configure_interrupt_moderation_edma()
230 * (set bit 0 to 0x1 and clear bits 1-8) in wil_configure_interrupt_moderation_edma()
238 struct wireless_dev *wdev = wil->main_ndev->ieee80211_ptr; in wil_configure_interrupt_moderation()
245 if (wdev->iftype == NL80211_IFTYPE_MONITOR) in wil_configure_interrupt_moderation()
248 /* Disable and clear tx counter before (re)configuration */ in wil_configure_interrupt_moderation()
250 wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
252 wil->tx_max_burst_duration); in wil_configure_interrupt_moderation()
253 /* Configure TX max burst duration timer to use usec units */ in wil_configure_interrupt_moderation()
257 /* Disable and clear tx idle counter before (re)configuration */ in wil_configure_interrupt_moderation()
259 wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
261 wil->tx_interframe_timeout); in wil_configure_interrupt_moderation()
262 /* Configure TX max burst duration timer to use usec units */ in wil_configure_interrupt_moderation()
268 wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
270 wil->rx_max_burst_duration); in wil_configure_interrupt_moderation()
271 /* Configure TX max burst duration timer to use usec units */ in wil_configure_interrupt_moderation()
277 wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
279 wil->rx_interframe_timeout); in wil_configure_interrupt_moderation()
280 /* Configure TX max burst duration timer to use usec units */ in wil_configure_interrupt_moderation()
293 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
309 * action is always the same - should empty the accumulated in wil6210_irq_rx()
319 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx()
320 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx()
323 napi_schedule(&wil->napi_rx); in wil6210_irq_rx()
335 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx()
339 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx()
355 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
371 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_rx_edma()
372 if (likely(test_bit(wil_status_napi_en, wil->status))) { in wil6210_irq_rx_edma()
375 napi_schedule(&wil->napi_rx); in wil6210_irq_rx_edma()
386 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx_edma()
390 atomic_inc(&wil->isr_count_rx); in wil6210_irq_rx_edma()
406 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
411 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx_edma()
414 wil_err(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx_edma()
420 wil_dbg_irq(wil, "TX status ring\n"); in wil6210_irq_tx_edma()
422 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx_edma()
423 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx_edma()
425 napi_schedule(&wil->napi_tx); in wil6210_irq_tx_edma()
427 wil_err(wil, "Got Tx status ring IRQ while in reset\n"); in wil6210_irq_tx_edma()
432 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); in wil6210_irq_tx_edma()
434 /* Tx IRQ will be enabled when NAPI processing finished */ in wil6210_irq_tx_edma()
436 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx_edma()
452 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
457 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx()
460 wil_err_ratelimited(wil, "spurious IRQ: TX\n"); in wil6210_irq_tx()
466 wil_dbg_irq(wil, "TX done\n"); in wil6210_irq_tx()
469 isr &= ~(BIT(25) - 1UL); in wil6210_irq_tx()
470 if (likely(test_bit(wil_status_fwready, wil->status))) { in wil6210_irq_tx()
471 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n"); in wil6210_irq_tx()
473 napi_schedule(&wil->napi_tx); in wil6210_irq_tx()
475 wil_err_ratelimited(wil, "Got Tx interrupt while in reset\n"); in wil6210_irq_tx()
480 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", in wil6210_irq_tx()
483 /* Tx IRQ will be enabled when NAPI processing finished */ in wil6210_irq_tx()
485 atomic_inc(&wil->isr_count_tx); in wil6210_irq_tx()
495 struct device *dev = &wil->main_ndev->dev; in wil_notify_fw_error()
502 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp); in wil_notify_fw_error()
508 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX, in wil_cache_mbox_regs()
510 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx); in wil_cache_mbox_regs()
511 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx); in wil_cache_mbox_regs()
519 if (wil->mbox_ctl.rx.entry_size < min_size) { in wil_validate_mbox_regs()
521 wil->mbox_ctl.rx.entry_size); in wil_validate_mbox_regs()
524 if (wil->mbox_ctl.tx.entry_size < min_size) { in wil_validate_mbox_regs()
525 wil_err(wil, "tx mbox entry too small (%d)\n", in wil_validate_mbox_regs()
526 wil->mbox_ctl.tx.entry_size); in wil_validate_mbox_regs()
540 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
554 u32 fw_assert_code = wil_r(wil, wil->rgf_fw_assert_code_addr); in wil6210_irq_misc()
556 wil_r(wil, wil->rgf_ucode_assert_code_addr); in wil6210_irq_misc()
561 clear_bit(wil_status_fwready, wil->status); in wil6210_irq_misc()
563 * do not clear @isr here - we do 2-nd part in thread in wil6210_irq_misc()
565 * in non-atomic context in wil6210_irq_misc()
573 set_bit(wil_status_mbox_ready, wil->status); in wil6210_irq_misc()
583 if (wil->halp.handle_icr) { in wil6210_irq_misc()
585 wil->halp.handle_icr = false; in wil6210_irq_misc()
588 complete(&wil->halp.comp); in wil6210_irq_misc()
592 wil->isr_misc = isr; in wil6210_irq_misc()
605 u32 isr = wil->isr_misc; in wil6210_irq_misc_thread()
611 wil->recovery_state = fw_recovery_pending; in wil6210_irq_misc_thread()
615 if (wil->platform_ops.notify) { in wil6210_irq_misc_thread()
617 wil->platform_ops.notify(wil->platform_handle, in wil6210_irq_misc_thread()
630 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); in wil6210_irq_misc_thread()
632 wil->isr_misc = 0; in wil6210_irq_misc_thread()
636 /* in non-triple MSI case, this is done inside wil6210_thread_irq in wil6210_irq_misc_thread()
639 if (wil->n_msi == 3 && wil->suspend_resp_rcvd) { in wil6210_irq_misc_thread()
641 wil->suspend_resp_comp = true; in wil6210_irq_misc_thread()
642 wake_up_interruptible(&wil->wq); in wil6210_irq_misc_thread()
655 if (wil->isr_misc) in wil6210_thread_irq()
660 if (wil->suspend_resp_rcvd) { in wil6210_thread_irq()
662 wil->suspend_resp_comp = true; in wil6210_thread_irq()
663 wake_up_interruptible(&wil->wq); in wil6210_thread_irq()
681 if (!test_bit(wil_status_irqen, wil->status)) { in wil6210_debug_irq_mask()
682 if (wil->use_enhanced_dma_hw) { in wil6210_debug_irq_mask()
683 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
686 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
691 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
694 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
700 icm_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
703 icr_rx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
708 icm_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
711 icr_tx = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
717 icm_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
720 icr_misc = wil_ioread32_and_clear(wil->csr + in wil6210_debug_irq_mask()
734 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" in wil6210_debug_irq_mask()
741 return -EINVAL; in wil6210_debug_irq_mask()
754 * pseudo_cause is Clear-On-Read, no need to ACK in wil6210_hardirq()
770 * - hard IRQ handler called right here in wil6210_hardirq()
771 * - threaded handler called later in wil6210_hardirq()
779 * voting for wake thread - need at least 1 vote in wil6210_hardirq()
782 (wil->txrx_ops.irq_rx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
786 (wil->txrx_ops.irq_tx(irq, cookie) == IRQ_WAKE_THREAD)) in wil6210_hardirq()
805 * - Tx in wil6210_request_3msi()
806 * - Rx in wil6210_request_3msi()
807 * - Misc in wil6210_request_3msi()
809 rc = request_irq(irq, wil->txrx_ops.irq_tx, IRQF_SHARED, in wil6210_request_3msi()
814 rc = request_irq(irq + 1, wil->txrx_ops.irq_rx, IRQF_SHARED, in wil6210_request_3msi()
844 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + in wil6210_clear_irq()
846 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + in wil6210_clear_irq()
848 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_RX_ICR) + in wil6210_clear_irq()
850 wil_clear32(wil->csr + HOSTADDR(RGF_INT_GEN_TX_ICR) + in wil6210_clear_irq()
852 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + in wil6210_clear_irq()
879 wil->n_msi ? "MSI" : "INTx", wil->n_msi); in wil6210_init_irq()
881 if (wil->use_enhanced_dma_hw) { in wil6210_init_irq()
882 wil->txrx_ops.irq_tx = wil6210_irq_tx_edma; in wil6210_init_irq()
883 wil->txrx_ops.irq_rx = wil6210_irq_rx_edma; in wil6210_init_irq()
885 wil->txrx_ops.irq_tx = wil6210_irq_tx; in wil6210_init_irq()
886 wil->txrx_ops.irq_rx = wil6210_irq_rx; in wil6210_init_irq()
889 if (wil->n_msi == 3) in wil6210_init_irq()
894 wil->n_msi ? 0 : IRQF_SHARED, in wil6210_init_irq()
905 if (wil->n_msi == 3) { in wil6210_fini_irq()