Lines Matching full:isr

15  * There is ISR pseudo-cause register,
17 * Its bits represents OR'ed bits from 3 real ISR registers:
24 * real ISR registers, or hardware may malfunction.
292 u32 isr; in wil6210_irq_rx() local
297 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx()
301 trace_wil6210_irq_rx(isr); in wil6210_irq_rx()
302 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx()
304 if (unlikely(!isr)) { in wil6210_irq_rx()
316 if (likely(isr & (BIT_DMA_EP_RX_ICR_RX_DONE | in wil6210_irq_rx()
318 wil_dbg_irq(wil, "RX done / RX_HTRSH received, ISR (0x%x)\n", in wil6210_irq_rx()
319 isr); in wil6210_irq_rx()
321 isr &= ~(BIT_DMA_EP_RX_ICR_RX_DONE | in wil6210_irq_rx()
338 if (unlikely(isr)) in wil6210_irq_rx()
339 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx()
354 u32 isr; in wil6210_irq_rx_edma() local
359 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_rx_edma()
363 trace_wil6210_irq_rx(isr); in wil6210_irq_rx_edma()
364 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr); in wil6210_irq_rx_edma()
366 if (unlikely(!isr)) { in wil6210_irq_rx_edma()
372 if (likely(isr & BIT_RX_STATUS_IRQ)) { in wil6210_irq_rx_edma()
374 isr &= ~BIT_RX_STATUS_IRQ; in wil6210_irq_rx_edma()
389 if (unlikely(isr)) in wil6210_irq_rx_edma()
390 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr); in wil6210_irq_rx_edma()
405 u32 isr; in wil6210_irq_tx_edma() local
410 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx_edma()
414 trace_wil6210_irq_tx(isr); in wil6210_irq_tx_edma()
415 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx_edma()
417 if (unlikely(!isr)) { in wil6210_irq_tx_edma()
423 if (likely(isr & BIT_TX_STATUS_IRQ)) { in wil6210_irq_tx_edma()
425 isr &= ~BIT_TX_STATUS_IRQ; in wil6210_irq_tx_edma()
435 if (unlikely(isr)) in wil6210_irq_tx_edma()
436 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr); in wil6210_irq_tx_edma()
451 u32 isr; in wil6210_irq_tx() local
456 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_tx()
460 trace_wil6210_irq_tx(isr); in wil6210_irq_tx()
461 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr); in wil6210_irq_tx()
463 if (unlikely(!isr)) { in wil6210_irq_tx()
469 if (likely(isr & BIT_DMA_EP_TX_ICR_TX_DONE)) { in wil6210_irq_tx()
471 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE; in wil6210_irq_tx()
473 isr &= ~(BIT(25) - 1UL); in wil6210_irq_tx()
483 if (unlikely(isr)) in wil6210_irq_tx()
484 wil_err_ratelimited(wil, "un-handled TX ISR bits 0x%08x\n", in wil6210_irq_tx()
485 isr); in wil6210_irq_tx()
540 u32 isr; in wil6210_irq_misc() local
544 isr = wil_ioread32_and_clear(wil->csr + in wil6210_irq_misc()
548 trace_wil6210_irq_misc(isr); in wil6210_irq_misc()
549 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr); in wil6210_irq_misc()
551 if (!isr) { in wil6210_irq_misc()
557 if (isr & ISR_MISC_FW_ERROR) { in wil6210_irq_misc()
567 * do not clear @isr here - we do 2-nd part in thread in wil6210_irq_misc()
573 if (isr & ISR_MISC_FW_READY) { in wil6210_irq_misc()
582 isr &= ~ISR_MISC_FW_READY; in wil6210_irq_misc()
585 if (isr & BIT_DMA_EP_MISC_ICR_HALP) { in wil6210_irq_misc()
586 isr &= ~BIT_DMA_EP_MISC_ICR_HALP; in wil6210_irq_misc()
596 wil->isr_misc = isr; in wil6210_irq_misc()
598 if (isr) { in wil6210_irq_misc()
609 u32 isr = wil->isr_misc; in wil6210_irq_misc_thread() local
611 trace_wil6210_irq_misc_thread(isr); in wil6210_irq_misc_thread()
612 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr); in wil6210_irq_misc_thread()
614 if (isr & ISR_MISC_FW_ERROR) { in wil6210_irq_misc_thread()
618 isr &= ~ISR_MISC_FW_ERROR; in wil6210_irq_misc_thread()
627 if (isr & ISR_MISC_MBOX_EVT) { in wil6210_irq_misc_thread()
630 isr &= ~ISR_MISC_MBOX_EVT; in wil6210_irq_misc_thread()
633 if (isr) in wil6210_irq_misc_thread()
634 wil_dbg_irq(wil, "un-handled MISC ISR bits 0x%08x\n", isr); in wil6210_irq_misc_thread()
777 * Hard IRQ handler reads and clears ISR. in wil6210_hardirq()
780 * returns IRQ_WAKE_THREAD and saves ISR register value in wil6210_hardirq()