17 /* DXE - DMA transfer engine
130 	/* DXE control block allocation */  in wcn36xx_dxe_alloc_ctl_blks()
155 	wcn36xx_err("Failed to allocate DXE control blocks\n");  in wcn36xx_dxe_alloc_ctl_blks()
245 		/* Only every second dxe needs a bd pointer,  in wcn36xx_dxe_init_tx_bd()
295 	struct wcn36xx_dxe_desc *dxe = ctl->desc;  in wcn36xx_dxe_fill_skb()  local
302 	dxe->dst_addr_l = dma_map_single(dev,  in wcn36xx_dxe_fill_skb()
306 	if (dma_mapping_error(dev, dxe->dst_addr_l)) {  in wcn36xx_dxe_fill_skb()
368 	wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ack status: %d\n", status);  in wcn36xx_dxe_tx_ack_ind()
475 			wcn36xx_err("DXE IRQ reported error: 0x%x in high TX channel\n",  in wcn36xx_irq_tx_complete()
491 		wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high, reason %08x\n",  in wcn36xx_irq_tx_complete()
514 			wcn36xx_err("DXE IRQ reported error: 0x%x in low TX channel\n",  in wcn36xx_irq_tx_complete()
530 		wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low, reason %08x\n",  in wcn36xx_irq_tx_complete()
587 	struct wcn36xx_dxe_desc *dxe;  in wcn36xx_rx_handle_packets()  local
602 		wcn36xx_err("DXE IRQ reported error on RX channel\n");  in wcn36xx_rx_handle_packets()
622 	dxe = ctl->desc;  in wcn36xx_rx_handle_packets()
624 	while (!(READ_ONCE(dxe->ctrl) & WCN36xx_DXE_CTRL_VLD)) {  in wcn36xx_rx_handle_packets()
630 		dma_addr = dxe->dst_addr_l;  in wcn36xx_rx_handle_packets()
646 		dxe->ctrl = ctrl;  in wcn36xx_rx_handle_packets()
649 		dxe = ctl->desc;  in wcn36xx_rx_handle_packets()
683 		wcn36xx_warn("No DXE interrupt pending\n");  in wcn36xx_dxe_rx_frame()
776 		wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n");  in wcn36xx_dxe_tx_frame()
794 	wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n");  in wcn36xx_dxe_tx_frame()
1065 	/* Put the DXE block into reset before freeing memory */  in wcn36xx_dxe_deinit()