Lines Matching full:pcap
1546 struct ath9k_hw_capabilities *pCap = &ah->caps;
1552 if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1790 struct ath9k_hw_capabilities *pCap = &ah->caps;
1812 if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
2131 struct ath9k_hw_capabilities *pCap = &ah->caps;
2135 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2316 struct ath9k_hw_capabilities *pCap = &ah->caps;
2358 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2422 struct ath9k_hw_capabilities *pCap = &ah->caps;
2425 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2426 pCap->gpio_mask = AR9271_GPIO_MASK;
2428 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2429 pCap->gpio_mask = AR7010_GPIO_MASK;
2431 pCap->num_gpio_pins = AR9287_NUM_GPIO;
2432 pCap->gpio_mask = AR9287_GPIO_MASK;
2434 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2435 pCap->gpio_mask = AR9285_GPIO_MASK;
2437 pCap->num_gpio_pins = AR9280_NUM_GPIO;
2438 pCap->gpio_mask = AR9280_GPIO_MASK;
2440 pCap->num_gpio_pins = AR9300_NUM_GPIO;
2441 pCap->gpio_mask = AR9300_GPIO_MASK;
2443 pCap->num_gpio_pins = AR9330_NUM_GPIO;
2444 pCap->gpio_mask = AR9330_GPIO_MASK;
2446 pCap->num_gpio_pins = AR9340_NUM_GPIO;
2447 pCap->gpio_mask = AR9340_GPIO_MASK;
2449 pCap->num_gpio_pins = AR9462_NUM_GPIO;
2450 pCap->gpio_mask = AR9462_GPIO_MASK;
2452 pCap->num_gpio_pins = AR9485_NUM_GPIO;
2453 pCap->gpio_mask = AR9485_GPIO_MASK;
2455 pCap->num_gpio_pins = AR9531_NUM_GPIO;
2456 pCap->gpio_mask = AR9531_GPIO_MASK;
2458 pCap->num_gpio_pins = AR9550_NUM_GPIO;
2459 pCap->gpio_mask = AR9550_GPIO_MASK;
2461 pCap->num_gpio_pins = AR9561_NUM_GPIO;
2462 pCap->gpio_mask = AR9561_GPIO_MASK;
2464 pCap->num_gpio_pins = AR9565_NUM_GPIO;
2465 pCap->gpio_mask = AR9565_GPIO_MASK;
2467 pCap->num_gpio_pins = AR9580_NUM_GPIO;
2468 pCap->gpio_mask = AR9580_GPIO_MASK;
2470 pCap->num_gpio_pins = AR_NUM_GPIO;
2471 pCap->gpio_mask = AR_GPIO_MASK;
2477 struct ath9k_hw_capabilities *pCap = &ah->caps;
2504 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2511 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2514 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2525 pCap->chip_chainmask = 1;
2527 pCap->chip_chainmask = 7;
2532 pCap->chip_chainmask = 3;
2534 pCap->chip_chainmask = 7;
2536 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2545 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2547 pCap->rx_chainmask = 0x7;
2550 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2552 pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2553 pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2554 ah->txchainmask = pCap->tx_chainmask;
2555 ah->rxchainmask = pCap->rx_chainmask;
2566 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2568 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2571 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2573 pCap->rts_aggr_limit = (8 * 1024);
2583 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2587 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2589 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2592 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2594 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2597 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2600 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2602 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2603 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2604 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2605 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2606 pCap->txs_len = sizeof(struct ar9003_txs);
2608 pCap->tx_desc_len = sizeof(struct ath_desc);
2610 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2614 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2622 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2629 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2637 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2643 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2649 pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2651 tx_chainmask = pCap->tx_chainmask;
2652 rx_chainmask = pCap->rx_chainmask;
2655 pCap->max_txchains++;
2657 pCap->max_rxchains++;
2665 pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2668 pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2673 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;