Lines Matching +full:recv +full:- +full:not +full:- +full:empty
2 * Copyright (c) 2007-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
23 #include "hif-ops.h"
37 buf = req->virt_dma_buf; in ath6kl_hif_cp_scat_dma_buf()
39 for (i = 0; i < req->scat_entries; i++) { in ath6kl_hif_cp_scat_dma_buf()
41 memcpy(req->scat_list[i].buf, buf, in ath6kl_hif_cp_scat_dma_buf()
42 req->scat_list[i].len); in ath6kl_hif_cp_scat_dma_buf()
44 memcpy(buf, req->scat_list[i].buf, in ath6kl_hif_cp_scat_dma_buf()
45 req->scat_list[i].len); in ath6kl_hif_cp_scat_dma_buf()
47 buf += req->scat_list[i].len; in ath6kl_hif_cp_scat_dma_buf()
60 packet->status = status; in ath6kl_hif_rw_comp_handler()
61 packet->completion(packet->context, packet); in ath6kl_hif_rw_comp_handler()
78 address = TARG_VTOP(ar->target_type, address); in ath6kl_hif_dump_fw_crash()
91 regdump_addr = TARG_VTOP(ar->target_type, regdump_addr); in ath6kl_hif_dump_fw_crash()
102 ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version, in ath6kl_hif_dump_fw_crash()
103 ar->wiphy->fw_version); in ath6kl_hif_dump_fw_crash()
128 ret = hif_read_write_sync(dev->ar, COUNT_DEC_ADDRESS, in ath6kl_hif_proc_dbg_intr()
133 ath6kl_hif_dump_fw_crash(dev->ar); in ath6kl_hif_proc_dbg_intr()
134 ath6kl_read_fwlogs(dev->ar); in ath6kl_hif_proc_dbg_intr()
135 ath6kl_recovery_err_notify(dev->ar, ATH6KL_FW_ASSERT); in ath6kl_hif_proc_dbg_intr()
140 /* mailbox recv message polling */
148 for (i = timeout / ATH6KL_TIME_QUANTUM; i > 0; i--) { in ath6kl_hif_poll_mboxmsg_rx()
150 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, in ath6kl_hif_poll_mboxmsg_rx()
151 (u8 *) &dev->irq_proc_reg, in ath6kl_hif_poll_mboxmsg_rx()
152 sizeof(dev->irq_proc_reg), in ath6kl_hif_poll_mboxmsg_rx()
161 if (dev->irq_proc_reg.host_int_status & htc_mbox) { in ath6kl_hif_poll_mboxmsg_rx()
162 if (dev->irq_proc_reg.rx_lkahd_valid & in ath6kl_hif_poll_mboxmsg_rx()
168 rg = &dev->irq_proc_reg; in ath6kl_hif_poll_mboxmsg_rx()
170 le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); in ath6kl_hif_poll_mboxmsg_rx()
181 ath6kl_err("timeout waiting for recv message\n"); in ath6kl_hif_poll_mboxmsg_rx()
182 status = -ETIME; in ath6kl_hif_poll_mboxmsg_rx()
184 if (dev->irq_proc_reg.counter_int_status & in ath6kl_hif_poll_mboxmsg_rx()
209 spin_lock_bh(&dev->lock); in ath6kl_hif_rx_control()
212 dev->irq_en_reg.int_status_en |= in ath6kl_hif_rx_control()
215 dev->irq_en_reg.int_status_en &= in ath6kl_hif_rx_control()
218 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); in ath6kl_hif_rx_control()
220 spin_unlock_bh(&dev->lock); in ath6kl_hif_rx_control()
222 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, in ath6kl_hif_rx_control()
236 scat_req->req = HIF_RD_SYNC_BLOCK_FIX; in ath6kl_hif_submit_scat_req()
237 scat_req->addr = dev->ar->mbox_info.htc_addr; in ath6kl_hif_submit_scat_req()
239 scat_req->req = HIF_WR_ASYNC_BLOCK_INC; in ath6kl_hif_submit_scat_req()
241 scat_req->addr = in ath6kl_hif_submit_scat_req()
242 (scat_req->len > HIF_MBOX_WIDTH) ? in ath6kl_hif_submit_scat_req()
243 dev->ar->mbox_info.htc_ext_addr : in ath6kl_hif_submit_scat_req()
244 dev->ar->mbox_info.htc_addr; in ath6kl_hif_submit_scat_req()
249 scat_req->scat_entries, scat_req->len, in ath6kl_hif_submit_scat_req()
250 scat_req->addr, !read ? "async" : "sync", in ath6kl_hif_submit_scat_req()
253 if (!read && scat_req->virt_scat) { in ath6kl_hif_submit_scat_req()
256 scat_req->status = status; in ath6kl_hif_submit_scat_req()
257 scat_req->complete(dev->ar->htc_target, scat_req); in ath6kl_hif_submit_scat_req()
262 status = ath6kl_hif_scat_req_rw(dev->ar, scat_req); in ath6kl_hif_submit_scat_req()
266 scat_req->status = status; in ath6kl_hif_submit_scat_req()
267 if (!status && scat_req->virt_scat) in ath6kl_hif_submit_scat_req()
268 scat_req->status = in ath6kl_hif_submit_scat_req()
281 counter_int_status = dev->irq_proc_reg.counter_int_status & in ath6kl_hif_proc_counter_intr()
282 dev->irq_en_reg.cntr_int_status_en; in ath6kl_hif_proc_counter_intr()
307 error_int_status = dev->irq_proc_reg.error_int_status & 0x0F; in ath6kl_hif_proc_err_intr()
310 return -EIO; in ath6kl_hif_proc_err_intr()
327 dev->irq_proc_reg.error_int_status &= ~error_int_status; in ath6kl_hif_proc_err_intr()
335 status = hif_read_write_sync(dev->ar, ERROR_INT_STATUS_ADDRESS, in ath6kl_hif_proc_err_intr()
351 cpu_int_status = dev->irq_proc_reg.cpu_int_status & in ath6kl_hif_proc_cpu_intr()
352 dev->irq_en_reg.cpu_int_status_en; in ath6kl_hif_proc_cpu_intr()
355 return -EIO; in ath6kl_hif_proc_cpu_intr()
363 dev->irq_proc_reg.cpu_int_status &= ~cpu_int_status; in ath6kl_hif_proc_cpu_intr()
367 * this is done to make the access 4-byte aligned to mitigate issues in ath6kl_hif_proc_cpu_intr()
369 * be a multiple of 4-bytes. in ath6kl_hif_proc_cpu_intr()
374 /* the remaining are set to zero which have no-effect */ in ath6kl_hif_proc_cpu_intr()
379 status = hif_read_write_sync(dev->ar, CPU_INT_STATUS_ADDRESS, in ath6kl_hif_proc_cpu_intr()
410 if (dev->irq_en_reg.int_status_en) { in proc_pending_irqs()
426 status = hif_read_write_sync(dev->ar, HOST_INT_STATUS_ADDRESS, in proc_pending_irqs()
427 (u8 *) &dev->irq_proc_reg, in proc_pending_irqs()
428 sizeof(dev->irq_proc_reg), in proc_pending_irqs()
433 ath6kl_dump_registers(dev, &dev->irq_proc_reg, in proc_pending_irqs()
434 &dev->irq_en_reg); in proc_pending_irqs()
435 trace_ath6kl_sdio_irq(&dev->irq_en_reg, in proc_pending_irqs()
436 sizeof(dev->irq_en_reg)); in proc_pending_irqs()
439 host_int_status = dev->irq_proc_reg.host_int_status & in proc_pending_irqs()
440 dev->irq_en_reg.int_status_en; in proc_pending_irqs()
449 if (dev->irq_proc_reg.rx_lkahd_valid & in proc_pending_irqs()
451 rg = &dev->irq_proc_reg; in proc_pending_irqs()
452 lk_ahd = le32_to_cpu(rg->rx_lkahd[HTC_MAILBOX]); in proc_pending_irqs()
471 * requests to empty the mailbox. When emptying the recv in proc_pending_irqs()
477 status = ath6kl_htc_rxmsg_pending_handler(dev->htc_cnxt, in proc_pending_irqs()
484 * HTC could not pull any messages out due to lack in proc_pending_irqs()
487 dev->htc_cnxt->chk_irq_status_cnt = 0; in proc_pending_irqs()
516 * unecessarily which can re-wake the target, if upper layers in proc_pending_irqs()
517 * determine that we are in a low-throughput mode, we can rely on in proc_pending_irqs()
518 * taking another interrupt rather than re-checking the status in proc_pending_irqs()
519 * registers which can re-wake the target. in proc_pending_irqs()
522 * mbox messages at hif can not use this optimization due to in proc_pending_irqs()
528 "bypassing irq status re-check, forcing done\n"); in proc_pending_irqs()
530 if (!dev->htc_cnxt->chk_irq_status_cnt) in proc_pending_irqs()
542 struct ath6kl_device *dev = ar->htc_target->dev; in ath6kl_hif_intr_bh_handler()
548 * Reset counter used to flag a re-scan of IRQ status registers on in ath6kl_hif_intr_bh_handler()
551 dev->htc_cnxt->chk_irq_status_cnt = 0; in ath6kl_hif_intr_bh_handler()
555 * re-read. in ath6kl_hif_intr_bh_handler()
573 spin_lock_bh(&dev->lock); in ath6kl_hif_enable_intrs()
576 dev->irq_en_reg.int_status_en = in ath6kl_hif_enable_intrs()
585 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
588 dev->irq_en_reg.cpu_int_status_en = 0; in ath6kl_hif_enable_intrs()
591 dev->irq_en_reg.err_int_status_en = in ath6kl_hif_enable_intrs()
599 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
601 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); in ath6kl_hif_enable_intrs()
603 spin_unlock_bh(&dev->lock); in ath6kl_hif_enable_intrs()
605 status = hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, in ath6kl_hif_enable_intrs()
620 spin_lock_bh(&dev->lock); in ath6kl_hif_disable_intrs()
622 dev->irq_en_reg.int_status_en = 0; in ath6kl_hif_disable_intrs()
623 dev->irq_en_reg.cpu_int_status_en = 0; in ath6kl_hif_disable_intrs()
624 dev->irq_en_reg.err_int_status_en = 0; in ath6kl_hif_disable_intrs()
625 dev->irq_en_reg.cntr_int_status_en = 0; in ath6kl_hif_disable_intrs()
626 memcpy(®s, &dev->irq_en_reg, sizeof(regs)); in ath6kl_hif_disable_intrs()
627 spin_unlock_bh(&dev->lock); in ath6kl_hif_disable_intrs()
629 return hif_read_write_sync(dev->ar, INT_STATUS_ENABLE_ADDRESS, in ath6kl_hif_disable_intrs()
650 ath6kl_hif_irq_enable(dev->ar); in ath6kl_hif_unmask_intrs()
664 ath6kl_hif_irq_disable(dev->ar); in ath6kl_hif_mask_intrs()
673 spin_lock_init(&dev->lock); in ath6kl_hif_setup()
680 dev->htc_cnxt->block_sz = dev->ar->mbox_info.block_size; in ath6kl_hif_setup()
683 if ((dev->htc_cnxt->block_sz & (dev->htc_cnxt->block_sz - 1)) != 0) { in ath6kl_hif_setup()
685 status = -EINVAL; in ath6kl_hif_setup()
690 dev->htc_cnxt->block_mask = dev->htc_cnxt->block_sz - 1; in ath6kl_hif_setup()
693 dev->htc_cnxt->block_sz, dev->ar->mbox_info.htc_addr); in ath6kl_hif_setup()