Lines Matching +full:rom +full:- +full:val
2 * Copyright (c) 2004-2011 Atheros Communications Inc.
37 * command-specific data.
45 * BMI handles all required Target-side cache flushing.
104 * Semantics: Read a 32-bit Target SOC register.
114 * Semantics: Write a 32-bit Target SOC register.
126 * Semantics: Fetch the 4-byte Target information
141 * Semantics: Install a ROM Patch.
144 * u32 Target ROM Address
147 * u32 Activate? 1-->activate;
148 * 0-->install but do not activate
155 * Semantics: Uninstall a previously-installed ROM Patch,
166 * Semantics: Activate a list of previously-installed ROM Patches.
177 * Semantics: Deactivate a list of active ROM Patches.
189 * Semantics: Begin an LZ-compressed stream of input
198 * Note: Not supported on all versions of ROM firmware.
203 * Semantics: Host writes ATH6KL memory with LZ-compressed
214 * Note: Not supported on all versions of ROM firmware.
226 #define ath6kl_bmi_write_hi32(ar, item, val) \ argument
232 v = cpu_to_le32(val); \
236 #define ath6kl_bmi_read_hi32(ar, item, val) \ argument
238 u32 addr, *check_type = val; \
242 (void) (check_type == val); \
246 *val = le32_to_cpu(tmp); \