Lines Matching +full:tx +full:- +full:termination +full:- +full:fix
2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
71 #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
72 #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
73 #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
75 #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
79 #define AR5K_CFG_TXCNT 0x00007800 /* Tx frame count (?) [5210] */
81 #define AR5K_CFG_TXFSTAT 0x00008000 /* Tx frame status (?) [5210] */
104 #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */
135 * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
144 #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */
172 #define AR5K_TXCFG_TXFSTP 0x00000008 /* TX DMA full Stop [5210] */
173 #define AR5K_TXCFG_TXFULL 0x000003f0 /* TX Trigger level mask */
182 #define AR5K_TXCFG_JUMBO_DESC_EN 0x00000400 /* Enable jumbo tx descriptors [5211+] */
198 #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
254 * (reserved0-3)
270 * (reserved4-5)
285 * the logical OR from per-queue interrupt bits found on SISR registers
297 #define AR5K_ISR_TXDESC 0x00000080 /* TX descriptor request */
300 * NOTE: We don't have per-queue info for this
301 * one, but we can enable it per-queue through
303 #define AR5K_ISR_TXEOL 0x00000400 /* Empty TX descriptor */
336 * Secondary status registers [5211+] (0 - 4)
338 * These give the status for each QCU, only QCUs 0-9 are
378 * Shadow read-and-clear interrupt status registers [5211+]
402 #define AR5K_IMR_TXDESC 0x00000080 /* TX descriptor request*/
405 #define AR5K_IMR_TXEOL 0x00000400 /* Empty TX descriptor*/
430 * Secondary interrupt mask registers [5211+] (0 - 4)
469 * DMA Debug registers 0-7
470 * 0xe0 - 0xfc
545 * Card has 12 TX Queues but i see that only 0-9 are used (?)
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
548 * configuration register (0x08c0 - 0x08ec), a ready time configuration
549 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
550 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
606 #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
612 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
632 #define AR5K_QCU_MISC_DCU_EARLY 0x00000800 /* DCU early termination */
640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
673 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
674 * a retry limit register (0x1080 - 0x10ac), a channel time register
675 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
676 * a sequence number register (0x1140 - 0x116c). It seems that "global"
685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
729 * with pending frames. Intra-frame lockout means we wait until
736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
745 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
747 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
755 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */
759 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
794 * and it's used for generating pseudo-random
798 * used for idle sensing -multiplied with cwmin/max etc-)
816 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
817 #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
824 #define AR5K_DCU_TXP_M 0x000003ff /* Tx pause mask */
825 #define AR5K_DCU_TXP_STATUS 0x00010000 /* Tx pause status */
830 * 128bit tx filter for each DCU (4 slices per DCU)
856 #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */
892 * TODO: Fix LED stuff
909 #define AR5K_PCICFG_CBEFIX_DIS 0x00000400 /* Disable CBE fix */
912 #define AR5K_PCICFG_RETRY_FIX 0x00001000 /* Enable pci core retry fix */
936 * Mode 0 -> always input
937 * Mode 1 -> output when GPIODO for this GPIO is set to 0
938 * Mode 2 -> output when GPIODO for this GPIO is set to 1
939 * Mode 3 -> always output
989 * on 5424 and newer pci-e chips. */
999 * PCI-E Power management configuration
1020 * PCI-E Workaround enable register
1025 * PCI-E Serializer/Deserializer
1036 * Here we got a difference between 5210/5211-12
1043 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1048 * 5211 - write offset to AR5K_EEPROM_BASE
1054 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1057 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
1064 * file posted in madwifi-devel mailing list.
1075 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
1091 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
1120 * Range 0x7000 - 0x7ce0
1145 #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
1151 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
1207 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
1215 * easier we define a macro based on ah->ah_version for common
1241 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
1261 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
1275 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
1283 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
1291 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
1299 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
1307 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
1336 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
1344 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
1359 ((ah->ah_version == AR5K_AR5211 ? \
1362 ((ah->ah_version == AR5K_AR5211 ? \
1370 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
1378 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
1410 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
1420 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
1422 #define AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 /* TX Data Loopback (i guess it goes with DIS_TX) [5…
1424 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1426 #define AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 /* Generate invalid TX FCS */
1428 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1432 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1436 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1444 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1445 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1459 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
1467 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
1479 #define AR5K_ADDAC_TEST_TXCONT 0x00000001 /* Test continuous tx */
1515 * Back-off status register [5210]
1528 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
1543 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
1551 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1559 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
1567 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1575 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
1636 #define AR5K_XRSTOMP_TX 0x00000001 /* Stomp Tx (?) */
1638 #define AR5K_XRSTOMP_TX_RSSI 0x00000004 /* Stomp Tx RSSI (?) */
1639 #define AR5K_XRSTOMP_TX_BSSID 0x00000008 /* Stomp Tx BSSID (?) */
1673 * TX power control (TPC) register
1679 #define AR5K_TXPC_ACK_M 0x0000003f /* ACK tx power */
1681 #define AR5K_TXPC_CTS_M 0x00003f00 /* CTS tx power */
1683 #define AR5K_TXPC_CHIRP_M 0x003f0000 /* CHIRP tx power */
1697 #define AR5K_PROFCNT_TX 0x80ec /* Tx count */
1773 #define AR5K_MISC_MODE_COMBINED_MIC 0x00000004 /* use rx/tx MIC key */
1805 * Range: 0x8147 - 0x818c
1809 * Rate -> ACK SIFS mapping table (32 entries)
1817 * Rate -> duration mapping table (32 entries)
1823 * Rate -> db mapping table
1830 * db -> Rate mapping table
1860 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
1894 #define AR5K_PHY_TST1_TXHOLD 0x00003800 /* Set tx hold (?) */
1926 #define AR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f /* TX frame to TX data start */
1930 #define AR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 /* TX end to XLNA on */
1943 #define AR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 /* TX frame to XPA A on (field) */
1944 #define AR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 /* TX frame to XPA B on (field) */
1945 #define AR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 /* TX end to XPA A off (field) */
1946 #define AR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 /* TX end to XPA B off (field) */
1949 * Pre-Amplifier control register
1950 * (XPA -> external pre-amplifier)
1971 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */
1977 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
2028 #define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */
2085 /* 40MHz -> 5GHz band */
2089 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
2091 /* 44MHz -> 2.4GHz band */
2094 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
2155 #define AR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 /* Enable TX/RX (?) */
2194 * OFDM Self-correlator Cyclic RSSI threshold params
2207 * PHY-only warm reset register
2212 * PHY-only control register
2216 #define AR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 /* Late tx signal symbol (?) */
2218 #define AR5K_PHY_CTL_TX_ANT_SEL 0x00000008 /* TX antenna select */
2219 #define AR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 /* Static TX antenna */
2246 * PHY TX rate power registers [5112+]
2260 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
2262 /*---[5111+]---*/
2265 #define AR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 /* Mask for tx clip (?) */
2270 /*---[5110/5111]---*/
2276 #define AR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 /* TX underrun */
2286 * PHY Tx Power adjustment register [5212A+]
2301 5-bits, units unknown {0..31}
2306 6-bits, dBm range {0..63}
2311 6-bits, dBm range {0..63}
2316 6-bits, dBm range {0..63}
2322 7-bits, standard power range
2358 * RF Bus access request register (for synth-only channel switching)
2441 * PHY Illegal TX rate register [5112+]
2485 * PHY PCDAC TX power table
2518 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
2576 * PHY PDADC Tx power table