2  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5  * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
33 #include "reg.h"
42  * Here we handle the low-level functions related to baseband
48  * - Channel setting/switching
50  * - Automatic Gain Control (AGC) calibration
52  * - Noise Floor calibration
54  * - I/Q imbalance calibration (QAM correction)
56  * - Calibration due to thermal changes (gain_F)
58  * - Spur noise mitigation
60  * - RF/PHY initialization for the various operating modes and bwmodes
62  * - Antenna control
64  * - TX power control per channel/rate/packet type
77  * ath5k_hw_radio_revision() - Get the PHY Chip revision
113 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_radio_revision()
129  * ath5k_channel_ok() - Check if a channel is supported by the hw
139 	u16 freq = channel->center_freq;  in ath5k_channel_ok()
142 	if (channel->band == NL80211_BAND_2GHZ) {  in ath5k_channel_ok()
143 		if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&  in ath5k_channel_ok()
144 		    (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))  in ath5k_channel_ok()
146 	} else if (channel->band == NL80211_BAND_5GHZ)  in ath5k_channel_ok()
147 		if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&  in ath5k_channel_ok()
148 		    (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))  in ath5k_channel_ok()
155  * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise
165 	if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_chan_has_spur_noise()
166 	(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_chan_has_spur_noise()
167 	(ah->ah_radio == AR5K_RF2413) ||  in ath5k_hw_chan_has_spur_noise()
168 	(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))  in ath5k_hw_chan_has_spur_noise()
173 	if ((channel->center_freq % refclk_freq != 0) &&  in ath5k_hw_chan_has_spur_noise()
174 	((channel->center_freq % refclk_freq < 10) ||  in ath5k_hw_chan_has_spur_noise()
175 	(channel->center_freq % refclk_freq > 22)))  in ath5k_hw_chan_has_spur_noise()
182  * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer
206 	rfb = ah->ah_rf_banks;  in ath5k_hw_rfb_op()
208 	for (i = 0; i < ah->ah_rf_regs_count; i++) {  in ath5k_hw_rfb_op()
221 	bank = rfreg->bank;  in ath5k_hw_rfb_op()
222 	num_bits = rfreg->field.len;  in ath5k_hw_rfb_op()
223 	first_bit = rfreg->field.pos;  in ath5k_hw_rfb_op()
224 	col = rfreg->field.col;  in ath5k_hw_rfb_op()
230 	offset = ah->ah_offset[bank];  in ath5k_hw_rfb_op()
238 	entry = ((first_bit - 1) / 8) + offset;  in ath5k_hw_rfb_op()
239 	position = (first_bit - 1) % 8;  in ath5k_hw_rfb_op()
250 		mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<  in ath5k_hw_rfb_op()
256 			data >>= (8 - position);  in ath5k_hw_rfb_op()
260 			bits_shifted += last_bit - position;  in ath5k_hw_rfb_op()
263 		bits_left -= 8 - position;  in ath5k_hw_rfb_op()
272  * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212
293 	BUG_ON(!(ah->ah_version == AR5K_AR5212) ||  in ath5k_hw_write_ofdm_timings()
294 		(channel->hw_value == AR5K_MODE_11B));  in ath5k_hw_write_ofdm_timings()
300 	switch (ah->ah_bwmode) {  in ath5k_hw_write_ofdm_timings()
314 	coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;  in ath5k_hw_write_ofdm_timings()
317 	 * ALGO: coef_exp = 14 - highest set bit position */  in ath5k_hw_write_ofdm_timings()
322 		return -EINVAL;  in ath5k_hw_write_ofdm_timings()
325 	coef_exp = 14 - (coef_exp - 24);  in ath5k_hw_write_ofdm_timings()
331 		(1 << (24 - coef_exp - 1));  in ath5k_hw_write_ofdm_timings()
335 	ds_coef_man = coef_man >> (24 - coef_exp);  in ath5k_hw_write_ofdm_timings()
336 	ds_coef_exp = coef_exp - 16;  in ath5k_hw_write_ofdm_timings()
347  * ath5k_hw_phy_disable() - Disable PHY
359  * ath5k_hw_wait_for_synth() - Wait for synth to settle
368 	 * On 5211+ read activation -> rx delay  in ath5k_hw_wait_for_synth()
371 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_wait_for_synth()
375 		delay = (channel->hw_value == AR5K_MODE_11B) ?  in ath5k_hw_wait_for_synth()
377 		if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)  in ath5k_hw_wait_for_synth()
379 		if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)  in ath5k_hw_wait_for_synth()
401  * auto adjustment on hw -notice they have a much smaller BANK 7 and
402  * no gain optimization ladder-.
409  * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
413  * "http://madwifi-project.org/ticket/1659"
418  * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach
424 	switch (ah->ah_radio) {  in ath5k_hw_rfgain_opt_init()
426 		ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;  in ath5k_hw_rfgain_opt_init()
427 		ah->ah_gain.g_low = 20;  in ath5k_hw_rfgain_opt_init()
428 		ah->ah_gain.g_high = 35;  in ath5k_hw_rfgain_opt_init()
429 		ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;  in ath5k_hw_rfgain_opt_init()
432 		ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;  in ath5k_hw_rfgain_opt_init()
433 		ah->ah_gain.g_low = 20;  in ath5k_hw_rfgain_opt_init()
434 		ah->ah_gain.g_high = 85;  in ath5k_hw_rfgain_opt_init()
435 		ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;  in ath5k_hw_rfgain_opt_init()
438 		return -EINVAL;  in ath5k_hw_rfgain_opt_init()
445  * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet
463 	if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)  in ath5k_hw_request_rfgain_probe()
468 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,  in ath5k_hw_request_rfgain_probe()
472 	ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;  in ath5k_hw_request_rfgain_probe()
477  * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction
492 	if ((ah->ah_radio != AR5K_RF5112) ||  in ath5k_hw_rf_gainf_corr()
493 	(ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))  in ath5k_hw_rf_gainf_corr()
498 	ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);  in ath5k_hw_rf_gainf_corr()
500 	g_step = &go->go_step[ah->ah_gain.g_step_idx];  in ath5k_hw_rf_gainf_corr()
502 	if (ah->ah_rf_banks == NULL)  in ath5k_hw_rf_gainf_corr()
505 	ah->ah_gain.g_f_corr = 0;  in ath5k_hw_rf_gainf_corr()
515 	mix = g_step->gos_param[0];  in ath5k_hw_rf_gainf_corr()
519 		ah->ah_gain.g_f_corr = step * 2;  in ath5k_hw_rf_gainf_corr()
522 		ah->ah_gain.g_f_corr = (step - 5) * 2;  in ath5k_hw_rf_gainf_corr()
525 		ah->ah_gain.g_f_corr = step;  in ath5k_hw_rf_gainf_corr()
528 		ah->ah_gain.g_f_corr = 0;  in ath5k_hw_rf_gainf_corr()
532 	return ah->ah_gain.g_f_corr;  in ath5k_hw_rf_gainf_corr()
536  * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector
552 	if (ah->ah_rf_banks == NULL)  in ath5k_hw_rf_check_gainf_readback()
555 	if (ah->ah_radio == AR5K_RF5111) {  in ath5k_hw_rf_check_gainf_readback()
558 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);  in ath5k_hw_rf_check_gainf_readback()
568 		ah->ah_gain.g_high = level[3] -  in ath5k_hw_rf_check_gainf_readback()
569 			(step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);  in ath5k_hw_rf_check_gainf_readback()
570 		ah->ah_gain.g_low = level[0] +  in ath5k_hw_rf_check_gainf_readback()
575 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);  in ath5k_hw_rf_check_gainf_readback()
586 			ah->ah_gain.g_high = 55;  in ath5k_hw_rf_check_gainf_readback()
590 	return (ah->ah_gain.g_current >= level[0] &&  in ath5k_hw_rf_check_gainf_readback()
591 			ah->ah_gain.g_current <= level[1]) ||  in ath5k_hw_rf_check_gainf_readback()
592 		(ah->ah_gain.g_current >= level[2] &&  in ath5k_hw_rf_check_gainf_readback()
593 			ah->ah_gain.g_current <= level[3]);  in ath5k_hw_rf_check_gainf_readback()
597  * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment
610 	switch (ah->ah_radio) {  in ath5k_hw_rf_gainf_adjust()
621 	g_step = &go->go_step[ah->ah_gain.g_step_idx];  in ath5k_hw_rf_gainf_adjust()
623 	if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {  in ath5k_hw_rf_gainf_adjust()
626 		if (ah->ah_gain.g_step_idx == 0)  in ath5k_hw_rf_gainf_adjust()
627 			return -1;  in ath5k_hw_rf_gainf_adjust()
629 		for (ah->ah_gain.g_target = ah->ah_gain.g_current;  in ath5k_hw_rf_gainf_adjust()
630 				ah->ah_gain.g_target >=  ah->ah_gain.g_high &&  in ath5k_hw_rf_gainf_adjust()
631 				ah->ah_gain.g_step_idx > 0;  in ath5k_hw_rf_gainf_adjust()
632 				g_step = &go->go_step[ah->ah_gain.g_step_idx])  in ath5k_hw_rf_gainf_adjust()
633 			ah->ah_gain.g_target -= 2 *  in ath5k_hw_rf_gainf_adjust()
634 			    (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -  in ath5k_hw_rf_gainf_adjust()
635 			    g_step->gos_gain);  in ath5k_hw_rf_gainf_adjust()
641 	if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {  in ath5k_hw_rf_gainf_adjust()
644 		if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))  in ath5k_hw_rf_gainf_adjust()
645 			return -2;  in ath5k_hw_rf_gainf_adjust()
647 		for (ah->ah_gain.g_target = ah->ah_gain.g_current;  in ath5k_hw_rf_gainf_adjust()
648 				ah->ah_gain.g_target <= ah->ah_gain.g_low &&  in ath5k_hw_rf_gainf_adjust()
649 				ah->ah_gain.g_step_idx < go->go_steps_count - 1;  in ath5k_hw_rf_gainf_adjust()
650 				g_step = &go->go_step[ah->ah_gain.g_step_idx])  in ath5k_hw_rf_gainf_adjust()
651 			ah->ah_gain.g_target -= 2 *  in ath5k_hw_rf_gainf_adjust()
652 			    (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -  in ath5k_hw_rf_gainf_adjust()
653 			    g_step->gos_gain);  in ath5k_hw_rf_gainf_adjust()
662 		ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,  in ath5k_hw_rf_gainf_adjust()
663 		ah->ah_gain.g_target);  in ath5k_hw_rf_gainf_adjust()
669  * ath5k_hw_gainf_calibrate() - Do a gain_F calibration
682 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_gainf_calibrate()
684 	if (ah->ah_rf_banks == NULL ||  in ath5k_hw_gainf_calibrate()
685 	ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)  in ath5k_hw_gainf_calibrate()
690 	if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)  in ath5k_hw_gainf_calibrate()
699 		ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;  in ath5k_hw_gainf_calibrate()
705 			if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)  in ath5k_hw_gainf_calibrate()
706 				ah->ah_gain.g_current +=  in ath5k_hw_gainf_calibrate()
707 					ee->ee_cck_ofdm_gain_delta;  in ath5k_hw_gainf_calibrate()
709 				ah->ah_gain.g_current +=  in ath5k_hw_gainf_calibrate()
715 		if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {  in ath5k_hw_gainf_calibrate()
717 			ah->ah_gain.g_current =  in ath5k_hw_gainf_calibrate()
718 				ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?  in ath5k_hw_gainf_calibrate()
719 				(ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :  in ath5k_hw_gainf_calibrate()
727 		AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&  in ath5k_hw_gainf_calibrate()
729 			ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;  in ath5k_hw_gainf_calibrate()
731 			ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;  in ath5k_hw_gainf_calibrate()
736 	return ah->ah_gain.g_state;  in ath5k_hw_gainf_calibrate()
740  * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw
755 	switch (ah->ah_radio) {  in ath5k_hw_rfgain_init()
782 		return -EINVAL;  in ath5k_hw_rfgain_init()
802  * ath5k_hw_rfregs_init() - Initialize RF register settings
819 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_rfregs_init()
822 	int i, obdb = -1, bank = -1;  in ath5k_hw_rfregs_init()
824 	switch (ah->ah_radio) {  in ath5k_hw_rfregs_init()
827 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);  in ath5k_hw_rfregs_init()
829 		ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);  in ath5k_hw_rfregs_init()
833 		if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {  in ath5k_hw_rfregs_init()
835 			ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);  in ath5k_hw_rfregs_init()
837 			ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);  in ath5k_hw_rfregs_init()
840 			ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);  in ath5k_hw_rfregs_init()
842 			ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);  in ath5k_hw_rfregs_init()
848 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);  in ath5k_hw_rfregs_init()
850 		ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);  in ath5k_hw_rfregs_init()
854 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);  in ath5k_hw_rfregs_init()
856 		ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);  in ath5k_hw_rfregs_init()
860 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);  in ath5k_hw_rfregs_init()
862 		ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);  in ath5k_hw_rfregs_init()
866 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);  in ath5k_hw_rfregs_init()
868 		ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);  in ath5k_hw_rfregs_init()
872 		ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);  in ath5k_hw_rfregs_init()
873 		if (ah->ah_mac_srev < AR5K_SREV_AR2417) {  in ath5k_hw_rfregs_init()
875 			ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);  in ath5k_hw_rfregs_init()
878 			ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);  in ath5k_hw_rfregs_init()
882 		return -EINVAL;  in ath5k_hw_rfregs_init()
886 	 * ah->ah_rf_banks based on ah->ah_rf_banks_size  in ath5k_hw_rfregs_init()
888 	if (ah->ah_rf_banks == NULL) {  in ath5k_hw_rfregs_init()
889 		ah->ah_rf_banks = kmalloc_array(ah->ah_rf_banks_size,  in ath5k_hw_rfregs_init()
892 		if (ah->ah_rf_banks == NULL) {  in ath5k_hw_rfregs_init()
894 			return -ENOMEM;  in ath5k_hw_rfregs_init()
899 	rfb = ah->ah_rf_banks;  in ath5k_hw_rfregs_init()
901 	for (i = 0; i < ah->ah_rf_banks_size; i++) {  in ath5k_hw_rfregs_init()
904 			return -EINVAL;  in ath5k_hw_rfregs_init()
910 			ah->ah_offset[bank] = i;  in ath5k_hw_rfregs_init()
917 	if (channel->band == NL80211_BAND_2GHZ) {  in ath5k_hw_rfregs_init()
919 		if (channel->hw_value == AR5K_MODE_11B)  in ath5k_hw_rfregs_init()
926 		 * in eeprom on ee->ee_ob[ee_mode][0]  in ath5k_hw_rfregs_init()
930 		 * 802.11a on ee->ee_ob[ee_mode][1] */  in ath5k_hw_rfregs_init()
931 		if ((ah->ah_radio == AR5K_RF5111) ||  in ath5k_hw_rfregs_init()
932 		(ah->ah_radio == AR5K_RF5112))  in ath5k_hw_rfregs_init()
937 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],  in ath5k_hw_rfregs_init()
940 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],  in ath5k_hw_rfregs_init()
944 	} else if ((channel->band == NL80211_BAND_5GHZ) ||  in ath5k_hw_rfregs_init()
945 			(ah->ah_radio == AR5K_RF5111)) {  in ath5k_hw_rfregs_init()
950 		obdb =	 channel->center_freq >= 5725 ? 3 :  in ath5k_hw_rfregs_init()
951 			(channel->center_freq >= 5500 ? 2 :  in ath5k_hw_rfregs_init()
952 			(channel->center_freq >= 5260 ? 1 :  in ath5k_hw_rfregs_init()
953 			 (channel->center_freq > 4000 ? 0 : -1)));  in ath5k_hw_rfregs_init()
956 			return -EINVAL;  in ath5k_hw_rfregs_init()
958 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],  in ath5k_hw_rfregs_init()
961 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],  in ath5k_hw_rfregs_init()
965 	g_step = &go->go_step[ah->ah_gain.g_step_idx];  in ath5k_hw_rfregs_init()
968 	if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&  in ath5k_hw_rfregs_init()
969 	(ah->ah_radio != AR5K_RF5413))  in ath5k_hw_rfregs_init()
972 	/* Bank Modifications (chip-specific) */  in ath5k_hw_rfregs_init()
973 	if (ah->ah_radio == AR5K_RF5111) {  in ath5k_hw_rfregs_init()
976 		if (channel->hw_value != AR5K_MODE_11B) {  in ath5k_hw_rfregs_init()
980 					g_step->gos_param[0]);  in ath5k_hw_rfregs_init()
982 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],  in ath5k_hw_rfregs_init()
985 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],  in ath5k_hw_rfregs_init()
988 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],  in ath5k_hw_rfregs_init()
993 			ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;  in ath5k_hw_rfregs_init()
999 		ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],  in ath5k_hw_rfregs_init()
1002 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],  in ath5k_hw_rfregs_init()
1005 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],  in ath5k_hw_rfregs_init()
1008 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],  in ath5k_hw_rfregs_init()
1012 		if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||  in ath5k_hw_rfregs_init()
1013 		ah->ah_bwmode == AR5K_BWMODE_10MHZ) {  in ath5k_hw_rfregs_init()
1019 			wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?  in ath5k_hw_rfregs_init()
1030 	if (ah->ah_radio == AR5K_RF5112) {  in ath5k_hw_rfregs_init()
1033 		if (channel->hw_value != AR5K_MODE_11B) {  in ath5k_hw_rfregs_init()
1035 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],  in ath5k_hw_rfregs_init()
1038 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],  in ath5k_hw_rfregs_init()
1041 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],  in ath5k_hw_rfregs_init()
1044 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],  in ath5k_hw_rfregs_init()
1047 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],  in ath5k_hw_rfregs_init()
1050 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],  in ath5k_hw_rfregs_init()
1053 			ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],  in ath5k_hw_rfregs_init()
1058 			ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;  in ath5k_hw_rfregs_init()
1063 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],  in ath5k_hw_rfregs_init()
1066 		if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {  in ath5k_hw_rfregs_init()
1069 						ee->ee_x_gain[ee_mode],  in ath5k_hw_rfregs_init()
1073 			u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];  in ath5k_hw_rfregs_init()
1074 			if (ee->ee_pd_gains[ee_mode] > 1) {  in ath5k_hw_rfregs_init()
1091 			if (ah->ah_radio == AR5K_RF5112 &&  in ath5k_hw_rfregs_init()
1092 			    (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {  in ath5k_hw_rfregs_init()
1107 			if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {  in ath5k_hw_rfregs_init()
1125 		ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],  in ath5k_hw_rfregs_init()
1129 		if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||  in ath5k_hw_rfregs_init()
1130 		ah->ah_bwmode == AR5K_BWMODE_10MHZ) {  in ath5k_hw_rfregs_init()
1133 			pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?  in ath5k_hw_rfregs_init()
1144 	if (ah->ah_radio == AR5K_RF5413 &&  in ath5k_hw_rfregs_init()
1145 	channel->band == NL80211_BAND_2GHZ) {  in ath5k_hw_rfregs_init()
1150 		/* Set optimum value for early revisions (on pci-e chips) */  in ath5k_hw_rfregs_init()
1151 		if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&  in ath5k_hw_rfregs_init()
1152 		ah->ah_mac_srev < AR5K_SREV_AR5413)  in ath5k_hw_rfregs_init()
1159 	for (i = 0; i < ah->ah_rf_banks_size; i++) {  in ath5k_hw_rfregs_init()
1173  * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110
1186 				channel->center_freq) - 24) / 2, 5)  in ath5k_hw_rf5110_chan2athchan()
1192  * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110
1214  * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111
1229 	/* Cast this value to catch negative channel numbers (>= -19) */  in ath5k_hw_rf5111_chan2athchan()
1236 		athchan->a2_athchan = 115 + channel;  in ath5k_hw_rf5111_chan2athchan()
1237 		athchan->a2_flags = 0x46;  in ath5k_hw_rf5111_chan2athchan()
1239 		athchan->a2_athchan = 124;  in ath5k_hw_rf5111_chan2athchan()
1240 		athchan->a2_flags = 0x44;  in ath5k_hw_rf5111_chan2athchan()
1242 		athchan->a2_athchan = ((channel - 14) * 4) + 132;  in ath5k_hw_rf5111_chan2athchan()
1243 		athchan->a2_flags = 0x46;  in ath5k_hw_rf5111_chan2athchan()
1245 		return -EINVAL;  in ath5k_hw_rf5111_chan2athchan()
1251  * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111
1261 		ieee80211_frequency_to_channel(channel->center_freq);  in ath5k_hw_rf5111_channel()
1270 	if (channel->band == NL80211_BAND_2GHZ) {  in ath5k_hw_rf5111_channel()
1273 			ieee80211_frequency_to_channel(channel->center_freq),  in ath5k_hw_rf5111_channel()
1285 		data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |  in ath5k_hw_rf5111_channel()
1289 		data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)  in ath5k_hw_rf5111_channel()
1302  * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer
1321 	c = channel->center_freq;  in ath5k_hw_rf5112_channel()
1329 		/* Channel 14 and all frequencies with 2Hz spacing  in ath5k_hw_rf5112_channel()
1330 		 * below/above (non-standard channels) */  in ath5k_hw_rf5112_channel()
1331 		if (!((c - 2224) % 5)) {  in ath5k_hw_rf5112_channel()
1332 			/* Same as (c - 2224) / 5 */  in ath5k_hw_rf5112_channel()
1333 			data0 = ((2 * (c - 704)) - 3040) / 10;  in ath5k_hw_rf5112_channel()
1335 		/* Channel 1 and all frequencies with 5Hz spacing  in ath5k_hw_rf5112_channel()
1337 		} else if (!((c - 2192) % 5)) {  in ath5k_hw_rf5112_channel()
1338 			/* Same as (c - 2192) / 5 */  in ath5k_hw_rf5112_channel()
1339 			data0 = ((2 * (c - 672)) - 3040) / 10;  in ath5k_hw_rf5112_channel()
1342 			return -EINVAL;  in ath5k_hw_rf5112_channel()
1346 	 * 4 reference clock settings (?) based on frequency spacing  in ath5k_hw_rf5112_channel()
1356 			data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);  in ath5k_hw_rf5112_channel()
1359 			data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);  in ath5k_hw_rf5112_channel()
1362 			data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);  in ath5k_hw_rf5112_channel()
1365 			return -EINVAL;  in ath5k_hw_rf5112_channel()
1367 		data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);  in ath5k_hw_rf5112_channel()
1380  * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425
1395 	c = channel->center_freq;  in ath5k_hw_rf2425_channel()
1398 		data0 = ath5k_hw_bitswap((c - 2272), 8);  in ath5k_hw_rf2425_channel()
1403 			data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);  in ath5k_hw_rf2425_channel()
1405 			data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);  in ath5k_hw_rf2425_channel()
1407 			data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);  in ath5k_hw_rf2425_channel()
1409 			return -EINVAL;  in ath5k_hw_rf2425_channel()
1412 		data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);  in ath5k_hw_rf2425_channel()
1425  * ath5k_hw_channel() - Set a channel on the radio chip
1445 			channel->center_freq);  in ath5k_hw_channel()
1446 		return -EINVAL;  in ath5k_hw_channel()
1452 	switch (ah->ah_radio) {  in ath5k_hw_channel()
1472 	if (channel->center_freq == 2484) {  in ath5k_hw_channel()
1480 	ah->ah_current_channel = channel;  in ath5k_hw_channel()
1496  * sample-and-hold the minimum noise level seen at the antennas.
1520  * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw
1533  * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer
1541 	ah->ah_nfcal_hist.index = 0;  in ath5k_hw_init_nfcal_hist()
1543 		ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;  in ath5k_hw_init_nfcal_hist()
1547  * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer
1553 	struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;  in ath5k_hw_update_nfcal_hist()
1554 	hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);  in ath5k_hw_update_nfcal_hist()
1555 	hist->nfval[hist->index] = noise_floor;  in ath5k_hw_update_nfcal_hist()
1560 	return *(s16 *)a - *(s16 *)b;  in cmps16()
1564  * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer
1573 	memcpy(sorted_nfval, ah->ah_nfcal_hist.nfval, sizeof(sorted_nfval));  in ath5k_hw_get_median_noise_floor()
1579 	return sorted_nfval[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];  in ath5k_hw_get_median_noise_floor()
1583  * ath5k_hw_update_noise_floor() - Update NF on hardware
1593 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_update_noise_floor()
1606 	ah->ah_cal_mask |= AR5K_CALIBRATION_NF;  in ath5k_hw_update_noise_floor()
1608 	ee_mode = ath5k_eeprom_mode_from_channel(ah, ah->ah_current_channel);  in ath5k_hw_update_noise_floor()
1612 	threshold = ee->ee_noise_floor_thr[ee_mode];  in ath5k_hw_update_noise_floor()
1638 	 * Load a high max CCA Power value (-50 dBm in .5 dBm units)  in ath5k_hw_update_noise_floor()
1643 	val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);  in ath5k_hw_update_noise_floor()
1650 	ah->ah_noise_floor = nf;  in ath5k_hw_update_noise_floor()
1652 	ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF;  in ath5k_hw_update_noise_floor()
1659  * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110
1672 	if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL))  in ath5k_hw_rf5110_calibrate()
1714 		AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);  in ath5k_hw_rf5110_calibrate()
1718 		AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |  in ath5k_hw_rf5110_calibrate()
1719 		AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);  in ath5k_hw_rf5110_calibrate()
1750 				channel->center_freq);  in ath5k_hw_rf5110_calibrate()
1755 	 * Re-enable RX/TX and beacons  in ath5k_hw_rf5110_calibrate()
1765  * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer
1776 	if (!ah->ah_iq_cal_needed)  in ath5k_hw_rf511x_iq_calibrate()
1777 		return -EINVAL;  in ath5k_hw_rf511x_iq_calibrate()
1781 		return -EBUSY;  in ath5k_hw_rf511x_iq_calibrate()
1784 	/* Calibration has finished, get the results and re-run */  in ath5k_hw_rf511x_iq_calibrate()
1800 	if (ah->ah_version == AR5K_AR5211)  in ath5k_hw_rf511x_iq_calibrate()
1809 		return -ECANCELED;  in ath5k_hw_rf511x_iq_calibrate()
1813 	i_coff = (-iq_corr) / i_coffd;  in ath5k_hw_rf511x_iq_calibrate()
1814 	i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */  in ath5k_hw_rf511x_iq_calibrate()
1816 	if (ah->ah_version == AR5K_AR5211)  in ath5k_hw_rf511x_iq_calibrate()
1817 		q_coff = (i_pwr / q_coffd) - 64;  in ath5k_hw_rf511x_iq_calibrate()
1819 		q_coff = (i_pwr / q_coffd) - 128;  in ath5k_hw_rf511x_iq_calibrate()
1820 	q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */  in ath5k_hw_rf511x_iq_calibrate()
1831 	/* Re-enable calibration -if we don't we'll commit  in ath5k_hw_rf511x_iq_calibrate()
1841  * ath5k_hw_phy_calibrate() - Perform a PHY calibration
1855 	if (ah->ah_radio == AR5K_RF5110)  in ath5k_hw_phy_calibrate()
1862 			channel->center_freq);  in ath5k_hw_phy_calibrate()
1871 	if ((ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&  in ath5k_hw_phy_calibrate()
1872 	    (ah->ah_radio == AR5K_RF5111 ||  in ath5k_hw_phy_calibrate()
1873 	     ah->ah_radio == AR5K_RF5112) &&  in ath5k_hw_phy_calibrate()
1874 	    channel->hw_value != AR5K_MODE_11B)  in ath5k_hw_phy_calibrate()
1878 	if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF))  in ath5k_hw_phy_calibrate()
1890  * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter
1903 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_set_spur_mitigation_filter()
1915 	if (channel->band == NL80211_BAND_2GHZ) {  in ath5k_hw_set_spur_mitigation_filter()
1916 		chan_fbin = (channel->center_freq - 2300) * 10;  in ath5k_hw_set_spur_mitigation_filter()
1919 		chan_fbin = (channel->center_freq - 4900) * 10;  in ath5k_hw_set_spur_mitigation_filter()
1928 	if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)  in ath5k_hw_set_spur_mitigation_filter()
1932 		spur_chan_fbin = ee->ee_spur_chans[i][freq_band];  in ath5k_hw_set_spur_mitigation_filter()
1941 		if ((chan_fbin - spur_detection_window <=  in ath5k_hw_set_spur_mitigation_filter()
1952 		spur_offset = spur_chan_fbin - chan_fbin;  in ath5k_hw_set_spur_mitigation_filter()
1955 		 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21  in ath5k_hw_set_spur_mitigation_filter()
1956 		 * spur_delta_phase -> spur_offset / chip_freq << 11  in ath5k_hw_set_spur_mitigation_filter()
1959 		switch (ah->ah_bwmode) {  in ath5k_hw_set_spur_mitigation_filter()
1979 			if (channel->band == NL80211_BAND_5GHZ) {  in ath5k_hw_set_spur_mitigation_filter()
1987 				/* sample_freq -> 40MHz chip_freq -> 44MHz  in ath5k_hw_set_spur_mitigation_filter()
2025 				(i == 0 || i == (num_symbol_offsets - 1))  in ath5k_hw_set_spur_mitigation_filter()
2032 					pilot_mask[0] |= 1 << (curr_sym_off - 1);  in ath5k_hw_set_spur_mitigation_filter()
2034 				pilot_mask[1] |= 1 << (curr_sym_off - 33);  in ath5k_hw_set_spur_mitigation_filter()
2037 			if (curr_sym_off >= -1 && curr_sym_off <= 14)  in ath5k_hw_set_spur_mitigation_filter()
2042 					plt_mag_map << (curr_sym_off - 15) * 2;  in ath5k_hw_set_spur_mitigation_filter()
2045 					plt_mag_map << (curr_sym_off - 31) * 2;  in ath5k_hw_set_spur_mitigation_filter()
2048 					plt_mag_map << (curr_sym_off - 47) * 2;  in ath5k_hw_set_spur_mitigation_filter()
2146  * omnidirectional or sectorial and antennas 3-14 sectorial (or directional).
2151  * (0 for automatic selection, 1 - 14 antenna number).
2157  * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX
2161  * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to
2164  * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the
2167  * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames
2172  * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically
2174  * AR5K_ANTMODE_FIXED_A	-> Only antenna A (MAIN) is present
2176  * AR5K_ANTMODE_FIXED_B	-> Only antenna B (AUX) is present
2178  * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap
2180  * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc
2182  * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc
2184  * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx-
2191  * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer
2198 	if (ah->ah_version != AR5K_AR5210)  in ath5k_hw_set_def_antenna()
2203  * ath5k_hw_set_fast_div() -  Enable/disable fast rx antenna diversity
2247  * ath5k_hw_set_antenna_switch() - Set up antenna switch table
2263 	if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)  in ath5k_hw_set_antenna_switch()
2265 	else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)  in ath5k_hw_set_antenna_switch()
2275 			(ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |  in ath5k_hw_set_antenna_switch()
2279 	ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],  in ath5k_hw_set_antenna_switch()
2281 	ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],  in ath5k_hw_set_antenna_switch()
2286  * ath5k_hw_set_antenna_mode() -  Set antenna operating mode
2293 	struct ieee80211_channel *channel = ah->ah_current_channel;  in ath5k_hw_set_antenna_mode()
2303 		ah->ah_ant_mode = ant_mode;  in ath5k_hw_set_antenna_mode()
2307 	def_ant = ah->ah_def_ant;  in ath5k_hw_set_antenna_mode()
2376 	ah->ah_tx_ant = tx_ant;  in ath5k_hw_set_antenna_mode()
2377 	ah->ah_ant_mode = ant_mode;  in ath5k_hw_set_antenna_mode()
2378 	ah->ah_def_ant = def_ant;  in ath5k_hw_set_antenna_mode()
2407  * ath5k_get_interpolated_value() - Get interpolated Y val between two points
2431 	ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));  in ath5k_get_interpolated_value()
2434 	result = y_left + (ratio * (target - x_left) / 100);  in ath5k_get_interpolated_value()
2440  * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the
2469 			pwr_i--;  in ath5k_get_linear_pcdac_min()
2483 			pwr_i--;  in ath5k_get_linear_pcdac_min()
2497  * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve
2542 	for (i = 0; (i <= (u16) (pmax - pmin)) &&  in ath5k_create_power_curve()
2548 		if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {  in ath5k_create_power_curve()
2564  * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers
2571  * Get the surrounding per-channel power calibration piers
2582 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_get_chan_pcal_surrounding_piers()
2586 	u32 target = channel->center_freq;  in ath5k_get_chan_pcal_surrounding_piers()
2591 	switch (channel->hw_value) {  in ath5k_get_chan_pcal_surrounding_piers()
2593 		pcinfo = ee->ee_pwr_cal_a;  in ath5k_get_chan_pcal_surrounding_piers()
2597 		pcinfo = ee->ee_pwr_cal_b;  in ath5k_get_chan_pcal_surrounding_piers()
2602 		pcinfo = ee->ee_pwr_cal_g;  in ath5k_get_chan_pcal_surrounding_piers()
2606 	max = ee->ee_n_piers[mode] - 1;  in ath5k_get_chan_pcal_surrounding_piers()
2643 			idx_l = idx_r - 1;  in ath5k_get_chan_pcal_surrounding_piers()
2654  * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power
2660  * Get the surrounding per-rate power calibration data
2670 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_get_rate_pcal_data()
2674 	u32 target = channel->center_freq;  in ath5k_get_rate_pcal_data()
2679 	switch (channel->hw_value) {  in ath5k_get_rate_pcal_data()
2681 		rpinfo = ee->ee_rate_tpwr_a;  in ath5k_get_rate_pcal_data()
2685 		rpinfo = ee->ee_rate_tpwr_b;  in ath5k_get_rate_pcal_data()
2690 		rpinfo = ee->ee_rate_tpwr_g;  in ath5k_get_rate_pcal_data()
2694 	max = ee->ee_rate_target_pwr_num[mode] - 1;  in ath5k_get_rate_pcal_data()
2697 	 * piers - same as above */  in ath5k_get_rate_pcal_data()
2717 			idx_l = idx_r - 1;  in ath5k_get_rate_pcal_data()
2724 	rates->freq = target;  in ath5k_get_rate_pcal_data()
2726 	rates->target_power_6to24 =  in ath5k_get_rate_pcal_data()
2732 	rates->target_power_36 =  in ath5k_get_rate_pcal_data()
2738 	rates->target_power_48 =  in ath5k_get_rate_pcal_data()
2744 	rates->target_power_54 =  in ath5k_get_rate_pcal_data()
2752  * ath5k_get_max_ctl_power() - Get max edge power for a given frequency
2765 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_get_max_ctl_power()
2766 	struct ath5k_edge_power *rep = ee->ee_ctl_pwr;  in ath5k_get_max_ctl_power()
2767 	u8 *ctl_val = ee->ee_ctl;  in ath5k_get_max_ctl_power()
2768 	s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;  in ath5k_get_max_ctl_power()
2773 	u32 target = channel->center_freq;  in ath5k_get_max_ctl_power()
2775 	ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);  in ath5k_get_max_ctl_power()
2777 	switch (channel->hw_value) {  in ath5k_get_max_ctl_power()
2779 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)  in ath5k_get_max_ctl_power()
2785 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)  in ath5k_get_max_ctl_power()
2797 	for (i = 0; i < ee->ee_ctls; i++) {  in ath5k_get_max_ctl_power()
2827 		ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);  in ath5k_get_max_ctl_power()
2838  * For RF5111 we have an XPD -eXternal Power Detector- curve
2844  * For RF5112 we have 4 XPD -eXternal Power Detector- curves
2845  * for each calibrated channel on 0, -6, -12 and -18dBm but we only
2849  * on hw, we get 4 points for xpd 0 (lower gain -> max power)
2850  * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c)
2854  * -if we don't have calibration data for this specific channel- from the
2864  * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111
2877 	u8	*pcdac_out = ah->ah_txpower.txp_pd_table;  in ath5k_fill_pwr_to_pcdac_table()
2878 	u8	*pcdac_tmp = ah->ah_txpower.tmpL[0];  in ath5k_fill_pwr_to_pcdac_table()
2887 	pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];  in ath5k_fill_pwr_to_pcdac_table()
2909  * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves
2927 	u8	*pcdac_out = ah->ah_txpower.txp_pd_table;  in ath5k_combine_linear_pcdac_curves()
2949 		pcdac_low_pwr = ah->ah_txpower.tmpL[1];  in ath5k_combine_linear_pcdac_curves()
2950 		pcdac_high_pwr = ah->ah_txpower.tmpL[0];  in ath5k_combine_linear_pcdac_curves()
2951 		mid_pwr_idx = table_max[1] - table_min[1] - 1;  in ath5k_combine_linear_pcdac_curves()
2952 		max_pwr_idx = (table_max[0] - table_min[0]) / 2;  in ath5k_combine_linear_pcdac_curves()
2957 		if (table_max[0] - table_min[1] > 126)  in ath5k_combine_linear_pcdac_curves()
2958 			min_pwr_idx = table_max[0] - 126;  in ath5k_combine_linear_pcdac_curves()
2968 		pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */  in ath5k_combine_linear_pcdac_curves()
2969 		pcdac_high_pwr = ah->ah_txpower.tmpL[0];  in ath5k_combine_linear_pcdac_curves()
2971 		max_pwr_idx = (table_max[0] - table_min[0]) / 2;  in ath5k_combine_linear_pcdac_curves()
2977 	ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;  in ath5k_combine_linear_pcdac_curves()
2981 	for (i = 63; i >= 0; i--) {  in ath5k_combine_linear_pcdac_curves()
2986 		(2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {  in ath5k_combine_linear_pcdac_curves()
2993 		 * already switched to the lower power curve -or  in ath5k_combine_linear_pcdac_curves()
2999 				i--;  in ath5k_combine_linear_pcdac_curves()
3007 		 * 126 -this can happen because we OR pcdac_out  in ath5k_combine_linear_pcdac_curves()
3013 		pwr--;  in ath5k_combine_linear_pcdac_curves()
3018  * ath5k_write_pcdac_table() - Write the PCDAC values on hw
3024 	u8	*pcdac_out = ah->ah_txpower.txp_pd_table;  in ath5k_write_pcdac_table()
3062  * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves
3078 	u8 *pdadc_out = ah->ah_txpower.txp_pd_table;  in ath5k_combine_pwr_to_pdadc_curves()
3092 		pdadc_tmp = ah->ah_txpower.tmpL[pdg];  in ath5k_combine_pwr_to_pdadc_curves()
3094 		if (pdg == pdcurves - 1)  in ath5k_combine_pwr_to_pdadc_curves()
3115 			pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -  in ath5k_combine_pwr_to_pdadc_curves()
3119 		if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)  in ath5k_combine_pwr_to_pdadc_curves()
3120 			pwr_step = pdadc_tmp[1] - pdadc_tmp[0];  in ath5k_combine_pwr_to_pdadc_curves()
3133 		pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];  in ath5k_combine_pwr_to_pdadc_curves()
3135 		table_size = pwr_max[pdg] - pwr_min[pdg];  in ath5k_combine_pwr_to_pdadc_curves()
3147 		if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)  in ath5k_combine_pwr_to_pdadc_curves()
3148 			pwr_step = pdadc_tmp[table_size - 1] -  in ath5k_combine_pwr_to_pdadc_curves()
3149 						pdadc_tmp[table_size - 2];  in ath5k_combine_pwr_to_pdadc_curves()
3156 			s16 tmp = pdadc_tmp[table_size - 1] +  in ath5k_combine_pwr_to_pdadc_curves()
3157 					(pdadc_0 - max_idx) * pwr_step;  in ath5k_combine_pwr_to_pdadc_curves()
3164 		gain_boundaries[pdg] = gain_boundaries[pdg - 1];  in ath5k_combine_pwr_to_pdadc_curves()
3169 		pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];  in ath5k_combine_pwr_to_pdadc_curves()
3188 	ah->ah_txpower.txp_min_idx = pwr_min[0];  in ath5k_combine_pwr_to_pdadc_curves()
3193  * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw
3200 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_write_pwr_to_pdadc_table()
3201 	u8 *pdadc_out = ah->ah_txpower.txp_pd_table;  in ath5k_write_pwr_to_pdadc_table()
3202 	u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];  in ath5k_write_pwr_to_pdadc_table()
3203 	u8 pdcurves = ee->ee_pd_gains[ee_mode];  in ath5k_write_pwr_to_pdadc_table()
3204 	u32 reg;  in ath5k_write_pwr_to_pdadc_table()  local
3210 	reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);  in ath5k_write_pwr_to_pdadc_table()
3211 	reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |  in ath5k_write_pwr_to_pdadc_table()
3224 	reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);  in ath5k_write_pwr_to_pdadc_table()
3228 		reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);  in ath5k_write_pwr_to_pdadc_table()
3231 		reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);  in ath5k_write_pwr_to_pdadc_table()
3234 		reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);  in ath5k_write_pwr_to_pdadc_table()
3237 	ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);  in ath5k_write_pwr_to_pdadc_table()
3254  * ath5k_setup_channel_powertable() - Set up power table for this channel
3274 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_setup_channel_powertable()
3275 	u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];  in ath5k_setup_channel_powertable()
3280 	u32 target = channel->center_freq;  in ath5k_setup_channel_powertable()
3290 	for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {  in ath5k_setup_channel_powertable()
3294 		 * to higher power. Use curve -> idx  in ath5k_setup_channel_powertable()
3299 		pdg_L = &pcinfo_L->pd_curves[idx];  in ath5k_setup_channel_powertable()
3300 		pdg_R = &pcinfo_R->pd_curves[idx];  in ath5k_setup_channel_powertable()
3303 		tmpL = ah->ah_txpower.tmpL[pdg];  in ath5k_setup_channel_powertable()
3304 		tmpR = ah->ah_txpower.tmpR[pdg];  in ath5k_setup_channel_powertable()
3312 		table_min[pdg] = min(pdg_L->pd_pwr[0],  in ath5k_setup_channel_powertable()
3313 					pdg_R->pd_pwr[0]) / 2;  in ath5k_setup_channel_powertable()
3315 		table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],  in ath5k_setup_channel_powertable()
3316 				pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;  in ath5k_setup_channel_powertable()
3325 			table_min[pdg] = min(pdg_L->pd_pwr[0],  in ath5k_setup_channel_powertable()
3326 						pdg_R->pd_pwr[0]);  in ath5k_setup_channel_powertable()
3329 				max(pdg_L->pd_pwr[pdg_L->pd_points - 1],  in ath5k_setup_channel_powertable()
3330 					pdg_R->pd_pwr[pdg_R->pd_points - 1]);  in ath5k_setup_channel_powertable()
3337 			if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {  in ath5k_setup_channel_powertable()
3340 					ath5k_get_linear_pcdac_min(pdg_L->pd_step,  in ath5k_setup_channel_powertable()
3341 								pdg_R->pd_step,  in ath5k_setup_channel_powertable()
3342 								pdg_L->pd_pwr,  in ath5k_setup_channel_powertable()
3343 								pdg_R->pd_pwr);  in ath5k_setup_channel_powertable()
3349 				if (table_max[pdg] - table_min[pdg] > 126)  in ath5k_setup_channel_powertable()
3350 					table_min[pdg] = table_max[pdg] - 126;  in ath5k_setup_channel_powertable()
3359 						pdg_L->pd_pwr,  in ath5k_setup_channel_powertable()
3360 						pdg_L->pd_step,  in ath5k_setup_channel_powertable()
3361 						pdg_L->pd_points, tmpL, type);  in ath5k_setup_channel_powertable()
3371 						pdg_R->pd_pwr,  in ath5k_setup_channel_powertable()
3372 						pdg_R->pd_step,  in ath5k_setup_channel_powertable()
3373 						pdg_R->pd_points, tmpR, type);  in ath5k_setup_channel_powertable()
3376 			return -EINVAL;  in ath5k_setup_channel_powertable()
3382 		 * pd gain. Re-use tmpL for interpolation  in ath5k_setup_channel_powertable()
3384 		for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&  in ath5k_setup_channel_powertable()
3387 							(s16) pcinfo_L->freq,  in ath5k_setup_channel_powertable()
3388 							(s16) pcinfo_R->freq,  in ath5k_setup_channel_powertable()
3395 	 * channel on tmpL (x range is table_max - table_min  in ath5k_setup_channel_powertable()
3405 	ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,  in ath5k_setup_channel_powertable()
3406 					(s16) pcinfo_L->freq,  in ath5k_setup_channel_powertable()
3407 					(s16) pcinfo_R->freq,  in ath5k_setup_channel_powertable()
3408 					pcinfo_L->min_pwr, pcinfo_R->min_pwr);  in ath5k_setup_channel_powertable()
3410 	ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,  in ath5k_setup_channel_powertable()
3411 					(s16) pcinfo_L->freq,  in ath5k_setup_channel_powertable()
3412 					(s16) pcinfo_R->freq,  in ath5k_setup_channel_powertable()
3413 					pcinfo_L->max_pwr, pcinfo_R->max_pwr);  in ath5k_setup_channel_powertable()
3422 						ee->ee_pd_gains[ee_mode]);  in ath5k_setup_channel_powertable()
3427 		ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);  in ath5k_setup_channel_powertable()
3435 		ah->ah_txpower.txp_min_idx = 0;  in ath5k_setup_channel_powertable()
3436 		ah->ah_txpower.txp_offset = 0;  in ath5k_setup_channel_powertable()
3442 						ee->ee_pd_gains[ee_mode]);  in ath5k_setup_channel_powertable()
3446 		ah->ah_txpower.txp_offset = table_min[0];  in ath5k_setup_channel_powertable()
3449 		return -EINVAL;  in ath5k_setup_channel_powertable()
3452 	ah->ah_txpower.txp_setup = true;  in ath5k_setup_channel_powertable()
3458  * ath5k_write_channel_powertable() - Set power table for current channel on hw
3474  * DOC: Per-rate tx power setting
3488  * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps -
3490  * rates[0] - rates[7] -> OFDM rates
3491  * rates[8] - rates[14] -> CCK rates
3492  * rates[15] -> XR rates (they all have the same power)
3496  * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power
3514 	max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;  in ath5k_setup_rate_powertable()
3517 	rates = ah->ah_txpower.txp_rates_power_table;  in ath5k_setup_rate_powertable()
3521 		rates[i] = min(max_pwr, rate_info->target_power_6to24);  in ath5k_setup_rate_powertable()
3524 	rates[5] = min(rates[0], rate_info->target_power_36);  in ath5k_setup_rate_powertable()
3525 	rates[6] = min(rates[0], rate_info->target_power_48);  in ath5k_setup_rate_powertable()
3526 	rates[7] = min(rates[0], rate_info->target_power_54);  in ath5k_setup_rate_powertable()
3530 	rates[8] = min(rates[0], rate_info->target_power_6to24);  in ath5k_setup_rate_powertable()
3532 	rates[9] = min(rates[0], rate_info->target_power_36);  in ath5k_setup_rate_powertable()
3534 	rates[10] = min(rates[0], rate_info->target_power_36);  in ath5k_setup_rate_powertable()
3536 	rates[11] = min(rates[0], rate_info->target_power_48);  in ath5k_setup_rate_powertable()
3538 	rates[12] = min(rates[0], rate_info->target_power_48);  in ath5k_setup_rate_powertable()
3540 	rates[13] = min(rates[0], rate_info->target_power_54);  in ath5k_setup_rate_powertable()
3542 	rates[14] = min(rates[0], rate_info->target_power_54);  in ath5k_setup_rate_powertable()
3545 	rates[15] = min(rates[0], rate_info->target_power_6to24);  in ath5k_setup_rate_powertable()
3552 	(ah->ah_phy_revision < AR5K_SREV_PHY_5212A))  in ath5k_setup_rate_powertable()
3554 			rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;  in ath5k_setup_rate_powertable()
3562 	ah->ah_txpower.txp_min_pwr = 2 * rates[7];  in ath5k_setup_rate_powertable()
3563 	ah->ah_txpower.txp_cur_pwr = 2 * rates[0];  in ath5k_setup_rate_powertable()
3566 	 * -that is the txpower for 54Mbit-, it's used for the PAPD  in ath5k_setup_rate_powertable()
3568 	ah->ah_txpower.txp_ofdm = rates[7];  in ath5k_setup_rate_powertable()
3574 		rate_idx_scaled = rates[i] + ah->ah_txpower.txp_offset;  in ath5k_setup_rate_powertable()
3586  * ath5k_hw_txpower() - Set transmission power limit for a given channel
3599 	struct ieee80211_channel *curr_channel = ah->ah_current_channel;  in ath5k_hw_txpower()
3606 		return -EINVAL;  in ath5k_hw_txpower()
3612 	switch (ah->ah_radio) {  in ath5k_hw_txpower()
3630 		return -EINVAL;  in ath5k_hw_txpower()
3637 	if (!ah->ah_txpower.txp_setup ||  in ath5k_hw_txpower()
3638 	    (channel->hw_value != curr_channel->hw_value) ||  in ath5k_hw_txpower()
3639 	    (channel->center_freq != curr_channel->center_freq)) {  in ath5k_hw_txpower()
3642 		int requested_txpower = ah->ah_txpower.txp_requested;  in ath5k_hw_txpower()
3644 		memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));  in ath5k_hw_txpower()
3647 		ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;  in ath5k_hw_txpower()
3649 		ah->ah_txpower.txp_requested = requested_txpower;  in ath5k_hw_txpower()
3670 	/* Get surrounding channels for per-rate power table  in ath5k_hw_txpower()
3695 	if (ah->ah_txpower.txp_tpc) {  in ath5k_hw_txpower()
3713  * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel
3726 	return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);  in ath5k_hw_set_txpower_limit()
3735  * ath5k_hw_phy_init() - Initialize PHY
3762 	curr_channel = ah->ah_current_channel;  in ath5k_hw_phy_init()
3763 	if (fast && (channel->hw_value != curr_channel->hw_value))  in ath5k_hw_phy_init()
3764 		return -EINVAL;  in ath5k_hw_phy_init()
3780 			return -EIO;  in ath5k_hw_phy_init()
3797 	ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_requested ?  in ath5k_hw_phy_init()
3798 					ah->ah_txpower.txp_requested * 2 :  in ath5k_hw_phy_init()
3804 	if (ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_phy_init()
3805 		channel->hw_value != AR5K_MODE_11B) {  in ath5k_hw_phy_init()
3814 		if (ah->ah_mac_srev >= AR5K_SREV_AR5424)  in ath5k_hw_phy_init()
3849 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_phy_init()
3855 		ret = ath5k_hw_rfgain_init(ah, channel->band);  in ath5k_hw_phy_init()
3870 		if (ah->ah_radio == AR5K_RF5111) {  in ath5k_hw_phy_init()
3879 	} else if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_phy_init()
3916 	 * During AGC calibration RX path is re-routed to  in ath5k_hw_phy_init()
3920 	 * used together with on-the fly I/Q calibration (the  in ath5k_hw_phy_init()
3924 	 * While rx path is re-routed to the power detector we also  in ath5k_hw_phy_init()
3936 	 * -no need for CCK- */  in ath5k_hw_phy_init()
3937 	ah->ah_iq_cal_needed = false;  in ath5k_hw_phy_init()
3939 		ah->ah_iq_cal_needed = true;  in ath5k_hw_phy_init()
3951 			channel->center_freq);  in ath5k_hw_phy_init()
3955 	ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);  in ath5k_hw_phy_init()