Lines Matching +full:gain +full:- +full:offset
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
52 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 : in ath5k_eeprom_bin2freq()
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_header()
77 u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX; in ath5k_eeprom_init_header() local
89 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0) in ath5k_eeprom_init_header()
101 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE; in ath5k_eeprom_init_header()
114 return -EIO; in ath5k_eeprom_init_header()
118 for (cksum = 0, offset = 0; offset < eep_max; offset++) { in ath5k_eeprom_init_header()
119 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val); in ath5k_eeprom_init_header()
128 return -EIO; in ath5k_eeprom_init_header()
131 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version), in ath5k_eeprom_init_header()
134 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) { in ath5k_eeprom_init_header()
141 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) in ath5k_eeprom_init_header()
144 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) { in ath5k_eeprom_init_header()
151 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) { in ath5k_eeprom_init_header()
153 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; in ath5k_eeprom_init_header()
154 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; in ath5k_eeprom_init_header()
157 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; in ath5k_eeprom_init_header()
158 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; in ath5k_eeprom_init_header()
163 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val) in ath5k_eeprom_init_header()
164 ee->ee_is_hb63 = true; in ath5k_eeprom_init_header()
166 ee->ee_is_hb63 = false; in ath5k_eeprom_init_header()
169 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL); in ath5k_eeprom_init_header()
170 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false; in ath5k_eeprom_init_header()
179 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ? in ath5k_eeprom_init_header()
189 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset, in ath5k_eeprom_read_ants() argument
192 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_ants()
193 u32 o = *offset; in ath5k_eeprom_read_ants()
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_ants()
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
205 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; in ath5k_eeprom_read_ants()
209 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; in ath5k_eeprom_read_ants()
210 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; in ath5k_eeprom_read_ants()
213 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; in ath5k_eeprom_read_ants()
214 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; in ath5k_eeprom_read_ants()
215 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
216 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
219 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
220 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
221 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
224 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] = in ath5k_eeprom_read_ants()
225 (ee->ee_ant_control[mode][0] << 4); in ath5k_eeprom_read_ants()
226 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] = in ath5k_eeprom_read_ants()
227 ee->ee_ant_control[mode][1] | in ath5k_eeprom_read_ants()
228 (ee->ee_ant_control[mode][2] << 6) | in ath5k_eeprom_read_ants()
229 (ee->ee_ant_control[mode][3] << 12) | in ath5k_eeprom_read_ants()
230 (ee->ee_ant_control[mode][4] << 18) | in ath5k_eeprom_read_ants()
231 (ee->ee_ant_control[mode][5] << 24); in ath5k_eeprom_read_ants()
232 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] = in ath5k_eeprom_read_ants()
233 ee->ee_ant_control[mode][6] | in ath5k_eeprom_read_ants()
234 (ee->ee_ant_control[mode][7] << 6) | in ath5k_eeprom_read_ants()
235 (ee->ee_ant_control[mode][8] << 12) | in ath5k_eeprom_read_ants()
236 (ee->ee_ant_control[mode][9] << 18) | in ath5k_eeprom_read_ants()
237 (ee->ee_ant_control[mode][10] << 24); in ath5k_eeprom_read_ants()
239 /* return new offset */ in ath5k_eeprom_read_ants()
240 *offset = o; in ath5k_eeprom_read_ants()
246 * Read supported modes and some mode-specific calibration data
249 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset, in ath5k_eeprom_read_modes() argument
252 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_modes()
253 u32 o = *offset; in ath5k_eeprom_read_modes()
256 ee->ee_n_piers[mode] = 0; in ath5k_eeprom_read_modes()
258 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); in ath5k_eeprom_read_modes()
261 ee->ee_ob[mode][3] = (val >> 5) & 0x7; in ath5k_eeprom_read_modes()
262 ee->ee_db[mode][3] = (val >> 2) & 0x7; in ath5k_eeprom_read_modes()
263 ee->ee_ob[mode][2] = (val << 1) & 0x7; in ath5k_eeprom_read_modes()
266 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; in ath5k_eeprom_read_modes()
267 ee->ee_db[mode][2] = (val >> 12) & 0x7; in ath5k_eeprom_read_modes()
268 ee->ee_ob[mode][1] = (val >> 9) & 0x7; in ath5k_eeprom_read_modes()
269 ee->ee_db[mode][1] = (val >> 6) & 0x7; in ath5k_eeprom_read_modes()
270 ee->ee_ob[mode][0] = (val >> 3) & 0x7; in ath5k_eeprom_read_modes()
271 ee->ee_db[mode][0] = val & 0x7; in ath5k_eeprom_read_modes()
275 ee->ee_ob[mode][1] = (val >> 4) & 0x7; in ath5k_eeprom_read_modes()
276 ee->ee_db[mode][1] = val & 0x7; in ath5k_eeprom_read_modes()
281 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
282 ee->ee_thr_62[mode] = val & 0xff; in ath5k_eeprom_read_modes()
284 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_read_modes()
285 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; in ath5k_eeprom_read_modes()
288 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
289 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; in ath5k_eeprom_read_modes()
292 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
295 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); in ath5k_eeprom_read_modes()
297 ee->ee_noise_floor_thr[mode] = val & 0xff; in ath5k_eeprom_read_modes()
299 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_read_modes()
300 ee->ee_noise_floor_thr[mode] = in ath5k_eeprom_read_modes()
301 mode == AR5K_EEPROM_MODE_11A ? -54 : -1; in ath5k_eeprom_read_modes()
304 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; in ath5k_eeprom_read_modes()
305 ee->ee_x_gain[mode] = (val >> 1) & 0xf; in ath5k_eeprom_read_modes()
306 ee->ee_xpd[mode] = val & 0x1; in ath5k_eeprom_read_modes()
308 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && in ath5k_eeprom_read_modes()
310 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; in ath5k_eeprom_read_modes()
312 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) { in ath5k_eeprom_read_modes()
314 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; in ath5k_eeprom_read_modes()
317 ee->ee_xr_power[mode] = val & 0x3f; in ath5k_eeprom_read_modes()
320 ee->ee_ob[mode][0] = val & 0x7; in ath5k_eeprom_read_modes()
321 ee->ee_db[mode][0] = (val >> 3) & 0x7; in ath5k_eeprom_read_modes()
325 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) { in ath5k_eeprom_read_modes()
326 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; in ath5k_eeprom_read_modes()
327 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; in ath5k_eeprom_read_modes()
329 ee->ee_i_gain[mode] = (val >> 13) & 0x7; in ath5k_eeprom_read_modes()
332 ee->ee_i_gain[mode] |= (val << 3) & 0x38; in ath5k_eeprom_read_modes()
335 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; in ath5k_eeprom_read_modes()
336 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6) in ath5k_eeprom_read_modes()
337 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; in ath5k_eeprom_read_modes()
341 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 && in ath5k_eeprom_read_modes()
343 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
344 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; in ath5k_eeprom_read_modes()
347 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0) in ath5k_eeprom_read_modes()
355 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1) in ath5k_eeprom_read_modes()
359 ee->ee_margin_tx_rx[mode] = val & 0x3f; in ath5k_eeprom_read_modes()
364 ee->ee_pwr_cal_b[0].freq = in ath5k_eeprom_read_modes()
366 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
367 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
369 ee->ee_pwr_cal_b[1].freq = in ath5k_eeprom_read_modes()
371 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
372 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
375 ee->ee_pwr_cal_b[2].freq = in ath5k_eeprom_read_modes()
377 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
378 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
380 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) in ath5k_eeprom_read_modes()
381 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
386 ee->ee_pwr_cal_g[0].freq = in ath5k_eeprom_read_modes()
388 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
389 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
391 ee->ee_pwr_cal_g[1].freq = in ath5k_eeprom_read_modes()
393 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
394 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
397 ee->ee_turbo_max_power[mode] = val & 0x7f; in ath5k_eeprom_read_modes()
398 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; in ath5k_eeprom_read_modes()
401 ee->ee_pwr_cal_g[2].freq = in ath5k_eeprom_read_modes()
403 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
404 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
406 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) in ath5k_eeprom_read_modes()
407 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
410 ee->ee_i_cal[mode] = (val >> 5) & 0x3f; in ath5k_eeprom_read_modes()
411 ee->ee_q_cal[mode] = val & 0x1f; in ath5k_eeprom_read_modes()
413 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) { in ath5k_eeprom_read_modes()
415 ee->ee_cck_ofdm_gain_delta = val & 0xff; in ath5k_eeprom_read_modes()
423 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0) in ath5k_eeprom_read_modes()
428 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; in ath5k_eeprom_read_modes()
430 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; in ath5k_eeprom_read_modes()
432 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; in ath5k_eeprom_read_modes()
433 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; in ath5k_eeprom_read_modes()
435 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; in ath5k_eeprom_read_modes()
437 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; in ath5k_eeprom_read_modes()
438 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; in ath5k_eeprom_read_modes()
440 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >= 2) in ath5k_eeprom_read_modes()
441 ee->ee_pd_gain_overlap = (val >> 9) & 0xf; in ath5k_eeprom_read_modes()
444 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_modes()
446 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; in ath5k_eeprom_read_modes()
448 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; in ath5k_eeprom_read_modes()
449 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; in ath5k_eeprom_read_modes()
451 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; in ath5k_eeprom_read_modes()
453 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; in ath5k_eeprom_read_modes()
454 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; in ath5k_eeprom_read_modes()
459 /* return new offset */ in ath5k_eeprom_read_modes()
460 *offset = o; in ath5k_eeprom_read_modes()
465 /* Read mode-specific data (except power calibration data) */
469 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_modes()
472 u32 offset; in ath5k_eeprom_init_modes() local
478 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); in ath5k_eeprom_init_modes()
479 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); in ath5k_eeprom_init_modes()
480 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); in ath5k_eeprom_init_modes()
482 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] = in ath5k_eeprom_init_modes()
483 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); in ath5k_eeprom_init_modes()
486 offset = mode_offset[mode]; in ath5k_eeprom_init_modes()
488 ret = ath5k_eeprom_read_ants(ah, &offset, mode); in ath5k_eeprom_init_modes()
492 ret = ath5k_eeprom_read_modes(ah, &offset, mode); in ath5k_eeprom_init_modes()
498 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) { in ath5k_eeprom_init_modes()
499 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15; in ath5k_eeprom_init_modes()
500 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28; in ath5k_eeprom_init_modes()
501 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28; in ath5k_eeprom_init_modes()
510 ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max, in ath5k_eeprom_read_freq_list() argument
513 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_freq_list()
514 int o = *offset; in ath5k_eeprom_read_freq_list()
519 ee->ee_n_piers[mode] = 0; in ath5k_eeprom_read_freq_list()
529 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_freq_list()
537 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_freq_list()
540 /* return new offset */ in ath5k_eeprom_read_freq_list()
541 *offset = o; in ath5k_eeprom_read_freq_list()
548 ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset) in ath5k_eeprom_init_11a_pcal_freq() argument
550 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_11a_pcal_freq()
551 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a; in ath5k_eeprom_init_11a_pcal_freq()
556 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { in ath5k_eeprom_init_11a_pcal_freq()
557 ath5k_eeprom_read_freq_list(ah, &offset, in ath5k_eeprom_init_11a_pcal_freq()
561 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version); in ath5k_eeprom_init_11a_pcal_freq()
563 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_init_11a_pcal_freq()
568 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_init_11a_pcal_freq()
573 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_init_11a_pcal_freq()
578 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_init_11a_pcal_freq()
584 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_init_11a_pcal_freq()
588 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10; in ath5k_eeprom_init_11a_pcal_freq()
601 ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset) in ath5k_eeprom_init_11bg_2413() argument
603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_11bg_2413()
608 pcal = ee->ee_pwr_cal_b; in ath5k_eeprom_init_11bg_2413()
611 pcal = ee->ee_pwr_cal_g; in ath5k_eeprom_init_11bg_2413()
614 return -EINVAL; in ath5k_eeprom_init_11bg_2413()
617 ath5k_eeprom_read_freq_list(ah, &offset, in ath5k_eeprom_init_11bg_2413()
628 * For RF5111 we have an XPD -eXternal Power Detector- curve
636 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
639 * 10% of the pcdac curve -until the curve reaches its maximum-
657 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2) in ath5k_get_pcdac_intercepts()
663 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100; in ath5k_get_pcdac_intercepts()
669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_free_pcal_info()
675 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_free_pcal_info()
677 chinfo = ee->ee_pwr_cal_a; in ath5k_eeprom_free_pcal_info()
680 if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_eeprom_free_pcal_info()
682 chinfo = ee->ee_pwr_cal_b; in ath5k_eeprom_free_pcal_info()
685 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_free_pcal_info()
687 chinfo = ee->ee_pwr_cal_g; in ath5k_eeprom_free_pcal_info()
690 return -EINVAL; in ath5k_eeprom_free_pcal_info()
693 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_free_pcal_info()
701 kfree(pd->pd_step); in ath5k_eeprom_free_pcal_info()
702 kfree(pd->pd_pwr); in ath5k_eeprom_free_pcal_info()
717 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_convert_pcal_info_5111()
721 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_5111()
724 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_5111()
743 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) { in ath5k_eeprom_convert_pcal_info_5111()
752 ee->ee_pd_gains[mode] = 1; in ath5k_eeprom_convert_pcal_info_5111()
756 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111; in ath5k_eeprom_convert_pcal_info_5111()
759 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111, in ath5k_eeprom_convert_pcal_info_5111()
761 if (!pd->pd_step) in ath5k_eeprom_convert_pcal_info_5111()
764 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111, in ath5k_eeprom_convert_pcal_info_5111()
766 if (!pd->pd_pwr) in ath5k_eeprom_convert_pcal_info_5111()
772 for (point = 0; point < pd->pd_points; point++) { in ath5k_eeprom_convert_pcal_info_5111()
775 pd->pd_pwr[point] = 2 * pcinfo->pwr[point]; in ath5k_eeprom_convert_pcal_info_5111()
778 pd->pd_step[point] = pcinfo->pcdac[point]; in ath5k_eeprom_convert_pcal_info_5111()
782 chinfo[pier].min_pwr = pd->pd_pwr[0]; in ath5k_eeprom_convert_pcal_info_5111()
783 chinfo[pier].max_pwr = pd->pd_pwr[10]; in ath5k_eeprom_convert_pcal_info_5111()
791 return -ENOMEM; in ath5k_eeprom_convert_pcal_info_5111()
798 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info_5111()
800 int offset, ret; in ath5k_eeprom_read_pcal_info_5111() local
804 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5111()
807 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5111()
811 offset + AR5K_EEPROM_GROUP1_OFFSET); in ath5k_eeprom_read_pcal_info_5111()
815 offset += AR5K_EEPROM_GROUP2_OFFSET; in ath5k_eeprom_read_pcal_info_5111()
816 pcal = ee->ee_pwr_cal_a; in ath5k_eeprom_read_pcal_info_5111()
819 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) && in ath5k_eeprom_read_pcal_info_5111()
820 !AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5111()
823 pcal = ee->ee_pwr_cal_b; in ath5k_eeprom_read_pcal_info_5111()
824 offset += AR5K_EEPROM_GROUP3_OFFSET; in ath5k_eeprom_read_pcal_info_5111()
830 ee->ee_n_piers[mode] = 3; in ath5k_eeprom_read_pcal_info_5111()
833 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5111()
836 pcal = ee->ee_pwr_cal_g; in ath5k_eeprom_read_pcal_info_5111()
837 offset += AR5K_EEPROM_GROUP4_OFFSET; in ath5k_eeprom_read_pcal_info_5111()
843 ee->ee_n_piers[mode] = 3; in ath5k_eeprom_read_pcal_info_5111()
846 return -EINVAL; in ath5k_eeprom_read_pcal_info_5111()
849 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_5111()
853 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5111()
854 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M); in ath5k_eeprom_read_pcal_info_5111()
855 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M); in ath5k_eeprom_read_pcal_info_5111()
856 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
858 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5111()
859 cdata->pwr[0] |= ((val >> 14) & 0x3); in ath5k_eeprom_read_pcal_info_5111()
860 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
861 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
862 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
864 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5111()
865 cdata->pwr[3] |= ((val >> 12) & 0xf); in ath5k_eeprom_read_pcal_info_5111()
866 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
867 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
869 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5111()
870 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
871 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
872 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
874 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5111()
875 cdata->pwr[8] |= ((val >> 14) & 0x3); in ath5k_eeprom_read_pcal_info_5111()
876 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
877 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M); in ath5k_eeprom_read_pcal_info_5111()
879 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min, in ath5k_eeprom_read_pcal_info_5111()
880 cdata->pcdac_max, cdata->pcdac); in ath5k_eeprom_read_pcal_info_5111()
890 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
891 * for each calibrated channel on 0, -6, -12 and -18dBm but we only
895 * on hw, we read 4 points for xpd 0 (lower gain -> max power)
896 * and 3 points for xpd 3 (higher gain -> lower power) here and
908 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_convert_pcal_info_5112()
910 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_5112()
914 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_5112()
928 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { in ath5k_eeprom_convert_pcal_info_5112()
934 /* Lowest gain curve (max power) */ in ath5k_eeprom_convert_pcal_info_5112()
937 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS; in ath5k_eeprom_convert_pcal_info_5112()
940 pd->pd_step = kcalloc(pd->pd_points, in ath5k_eeprom_convert_pcal_info_5112()
943 if (!pd->pd_step) in ath5k_eeprom_convert_pcal_info_5112()
946 pd->pd_pwr = kcalloc(pd->pd_points, in ath5k_eeprom_convert_pcal_info_5112()
949 if (!pd->pd_pwr) in ath5k_eeprom_convert_pcal_info_5112()
954 pd->pd_step[0] = pcinfo->pcdac_x0[0]; in ath5k_eeprom_convert_pcal_info_5112()
955 pd->pd_pwr[0] = pcinfo->pwr_x0[0]; in ath5k_eeprom_convert_pcal_info_5112()
957 for (point = 1; point < pd->pd_points; in ath5k_eeprom_convert_pcal_info_5112()
960 pd->pd_pwr[point] = in ath5k_eeprom_convert_pcal_info_5112()
961 pcinfo->pwr_x0[point]; in ath5k_eeprom_convert_pcal_info_5112()
964 pd->pd_step[point] = in ath5k_eeprom_convert_pcal_info_5112()
965 pd->pd_step[point - 1] + in ath5k_eeprom_convert_pcal_info_5112()
966 pcinfo->pcdac_x0[point]; in ath5k_eeprom_convert_pcal_info_5112()
970 chinfo[pier].min_pwr = pd->pd_pwr[0]; in ath5k_eeprom_convert_pcal_info_5112()
972 /* Highest gain curve (min power) */ in ath5k_eeprom_convert_pcal_info_5112()
975 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS; in ath5k_eeprom_convert_pcal_info_5112()
978 pd->pd_step = kcalloc(pd->pd_points, in ath5k_eeprom_convert_pcal_info_5112()
981 if (!pd->pd_step) in ath5k_eeprom_convert_pcal_info_5112()
984 pd->pd_pwr = kcalloc(pd->pd_points, in ath5k_eeprom_convert_pcal_info_5112()
987 if (!pd->pd_pwr) in ath5k_eeprom_convert_pcal_info_5112()
992 for (point = 0; point < pd->pd_points; in ath5k_eeprom_convert_pcal_info_5112()
995 pd->pd_pwr[point] = in ath5k_eeprom_convert_pcal_info_5112()
996 pcinfo->pwr_x3[point]; in ath5k_eeprom_convert_pcal_info_5112()
999 pd->pd_step[point] = in ath5k_eeprom_convert_pcal_info_5112()
1000 pcinfo->pcdac_x3[point]; in ath5k_eeprom_convert_pcal_info_5112()
1003 /* Since we have a higher gain curve in ath5k_eeprom_convert_pcal_info_5112()
1005 chinfo[pier].min_pwr = pd->pd_pwr[0]; in ath5k_eeprom_convert_pcal_info_5112()
1014 return -ENOMEM; in ath5k_eeprom_convert_pcal_info_5112()
1021 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info_5112()
1024 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_read_pcal_info_5112()
1025 u32 offset; in ath5k_eeprom_read_pcal_info_5112() local
1034 * higher (x3) gain */ in ath5k_eeprom_read_pcal_info_5112()
1036 /* ee_x_gain[mode] is x gain mask */ in ath5k_eeprom_read_pcal_info_5112()
1037 if ((ee->ee_x_gain[mode] >> i) & 0x1) in ath5k_eeprom_read_pcal_info_5112()
1040 ee->ee_pd_gains[mode] = pd_gains; in ath5k_eeprom_read_pcal_info_5112()
1043 return -EINVAL; in ath5k_eeprom_read_pcal_info_5112()
1050 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5112()
1051 ath5k_eeprom_init_11a_pcal_freq(ah, offset); in ath5k_eeprom_read_pcal_info_5112()
1053 offset += AR5K_EEPROM_GROUP2_OFFSET; in ath5k_eeprom_read_pcal_info_5112()
1054 gen_chan_info = ee->ee_pwr_cal_a; in ath5k_eeprom_read_pcal_info_5112()
1057 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5112()
1058 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5112()
1059 offset += AR5K_EEPROM_GROUP3_OFFSET; in ath5k_eeprom_read_pcal_info_5112()
1062 gen_chan_info = ee->ee_pwr_cal_b; in ath5k_eeprom_read_pcal_info_5112()
1065 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5112()
1066 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5112()
1067 offset += AR5K_EEPROM_GROUP4_OFFSET; in ath5k_eeprom_read_pcal_info_5112()
1068 else if (AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5112()
1069 offset += AR5K_EEPROM_GROUP2_OFFSET; in ath5k_eeprom_read_pcal_info_5112()
1072 gen_chan_info = ee->ee_pwr_cal_g; in ath5k_eeprom_read_pcal_info_5112()
1075 return -EINVAL; in ath5k_eeprom_read_pcal_info_5112()
1078 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_5112()
1082 * for the lower xpd gain curve in ath5k_eeprom_read_pcal_info_5112()
1083 * (0 dBm -> higher output power) */ in ath5k_eeprom_read_pcal_info_5112()
1085 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5112()
1086 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff); in ath5k_eeprom_read_pcal_info_5112()
1087 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff); in ath5k_eeprom_read_pcal_info_5112()
1093 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5112()
1094 chan_pcal_info->pcdac_x0[1] = (val & 0x1f); in ath5k_eeprom_read_pcal_info_5112()
1095 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f); in ath5k_eeprom_read_pcal_info_5112()
1096 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f); in ath5k_eeprom_read_pcal_info_5112()
1099 * for the higher xpd gain curve in ath5k_eeprom_read_pcal_info_5112()
1100 * (18 dBm -> lower output power) */ in ath5k_eeprom_read_pcal_info_5112()
1101 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5112()
1102 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff); in ath5k_eeprom_read_pcal_info_5112()
1103 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff); in ath5k_eeprom_read_pcal_info_5112()
1105 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_5112()
1106 chan_pcal_info->pwr_x3[2] = (val & 0xff); in ath5k_eeprom_read_pcal_info_5112()
1111 chan_pcal_info->pcdac_x3[0] = 20; in ath5k_eeprom_read_pcal_info_5112()
1112 chan_pcal_info->pcdac_x3[1] = 35; in ath5k_eeprom_read_pcal_info_5112()
1113 chan_pcal_info->pcdac_x3[2] = 63; in ath5k_eeprom_read_pcal_info_5112()
1115 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) { in ath5k_eeprom_read_pcal_info_5112()
1116 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f); in ath5k_eeprom_read_pcal_info_5112()
1119 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3]; in ath5k_eeprom_read_pcal_info_5112()
1121 chan_pcal_info->pcdac_x0[0] = 1; in ath5k_eeprom_read_pcal_info_5112()
1135 * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1147 * if a mode is not supported, its section is missing -not zeroed-.
1148 * So we need to calculate the starting offset for each section by using
1159 sz = pdgains_size[ee->ee_pd_gains[mode] - 1]; in ath5k_pdgains_size_2413()
1160 sz *= ee->ee_n_piers[mode]; in ath5k_pdgains_size_2413()
1165 /* Return the starting offset for a section based on the modes supported
1170 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4); in ath5k_cal_data_offset_2413() local
1174 if (AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_cal_data_offset_2413()
1175 offset += ath5k_pdgains_size_2413(ee, in ath5k_cal_data_offset_2413()
1180 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_cal_data_offset_2413()
1181 offset += ath5k_pdgains_size_2413(ee, in ath5k_cal_data_offset_2413()
1191 return offset; in ath5k_cal_data_offset_2413()
1200 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_convert_pcal_info_2413()
1202 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_2413()
1206 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_2413()
1220 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { in ath5k_eeprom_convert_pcal_info_2413()
1227 * curve (lowest gain) */ in ath5k_eeprom_convert_pcal_info_2413()
1228 if (pdg == ee->ee_pd_gains[mode] - 1) in ath5k_eeprom_convert_pcal_info_2413()
1229 pd->pd_points = AR5K_EEPROM_N_PD_POINTS; in ath5k_eeprom_convert_pcal_info_2413()
1231 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1; in ath5k_eeprom_convert_pcal_info_2413()
1234 pd->pd_step = kcalloc(pd->pd_points, in ath5k_eeprom_convert_pcal_info_2413()
1237 if (!pd->pd_step) in ath5k_eeprom_convert_pcal_info_2413()
1240 pd->pd_pwr = kcalloc(pd->pd_points, in ath5k_eeprom_convert_pcal_info_2413()
1243 if (!pd->pd_pwr) in ath5k_eeprom_convert_pcal_info_2413()
1249 pd->pd_step[0] = pcinfo->pddac_i[pdg]; in ath5k_eeprom_convert_pcal_info_2413()
1250 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg]; in ath5k_eeprom_convert_pcal_info_2413()
1252 for (point = 1; point < pd->pd_points; point++) { in ath5k_eeprom_convert_pcal_info_2413()
1254 pd->pd_pwr[point] = pd->pd_pwr[point - 1] + in ath5k_eeprom_convert_pcal_info_2413()
1255 2 * pcinfo->pwr[pdg][point - 1]; in ath5k_eeprom_convert_pcal_info_2413()
1257 pd->pd_step[point] = pd->pd_step[point - 1] + in ath5k_eeprom_convert_pcal_info_2413()
1258 pcinfo->pddac[pdg][point - 1]; in ath5k_eeprom_convert_pcal_info_2413()
1262 /* Highest gain curve -> min power */ in ath5k_eeprom_convert_pcal_info_2413()
1264 chinfo[pier].min_pwr = pd->pd_pwr[0]; in ath5k_eeprom_convert_pcal_info_2413()
1266 /* Lowest gain curve -> max power */ in ath5k_eeprom_convert_pcal_info_2413()
1267 if (pdg == ee->ee_pd_gains[mode] - 1) in ath5k_eeprom_convert_pcal_info_2413()
1269 pd->pd_pwr[pd->pd_points - 1]; in ath5k_eeprom_convert_pcal_info_2413()
1277 return -ENOMEM; in ath5k_eeprom_convert_pcal_info_2413()
1284 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info_2413()
1287 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_read_pcal_info_2413()
1288 u32 offset; in ath5k_eeprom_read_pcal_info_2413() local
1297 * lower gain so we go backwards */ in ath5k_eeprom_read_pcal_info_2413()
1298 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) { in ath5k_eeprom_read_pcal_info_2413()
1299 /* ee_x_gain[mode] is x gain mask */ in ath5k_eeprom_read_pcal_info_2413()
1300 if ((ee->ee_x_gain[mode] >> idx) & 0x1) in ath5k_eeprom_read_pcal_info_2413()
1304 ee->ee_pd_gains[mode] = pd_gains; in ath5k_eeprom_read_pcal_info_2413()
1307 return -EINVAL; in ath5k_eeprom_read_pcal_info_2413()
1309 offset = ath5k_cal_data_offset_2413(ee, mode); in ath5k_eeprom_read_pcal_info_2413()
1312 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_2413()
1315 ath5k_eeprom_init_11a_pcal_freq(ah, offset); in ath5k_eeprom_read_pcal_info_2413()
1316 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2; in ath5k_eeprom_read_pcal_info_2413()
1317 chinfo = ee->ee_pwr_cal_a; in ath5k_eeprom_read_pcal_info_2413()
1320 if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_eeprom_read_pcal_info_2413()
1323 ath5k_eeprom_init_11bg_2413(ah, mode, offset); in ath5k_eeprom_read_pcal_info_2413()
1324 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; in ath5k_eeprom_read_pcal_info_2413()
1325 chinfo = ee->ee_pwr_cal_b; in ath5k_eeprom_read_pcal_info_2413()
1328 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_read_pcal_info_2413()
1331 ath5k_eeprom_init_11bg_2413(ah, mode, offset); in ath5k_eeprom_read_pcal_info_2413()
1332 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2; in ath5k_eeprom_read_pcal_info_2413()
1333 chinfo = ee->ee_pwr_cal_g; in ath5k_eeprom_read_pcal_info_2413()
1336 return -EINVAL; in ath5k_eeprom_read_pcal_info_2413()
1339 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_2413()
1346 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1347 pcinfo->pwr_i[0] = val & 0x1f; in ath5k_eeprom_read_pcal_info_2413()
1348 pcinfo->pddac_i[0] = (val >> 5) & 0x7f; in ath5k_eeprom_read_pcal_info_2413()
1349 pcinfo->pwr[0][0] = (val >> 12) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1351 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1352 pcinfo->pddac[0][0] = val & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1353 pcinfo->pwr[0][1] = (val >> 6) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1354 pcinfo->pddac[0][1] = (val >> 10) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1356 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1357 pcinfo->pwr[0][2] = val & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1358 pcinfo->pddac[0][2] = (val >> 4) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1360 pcinfo->pwr[0][3] = 0; in ath5k_eeprom_read_pcal_info_2413()
1361 pcinfo->pddac[0][3] = 0; in ath5k_eeprom_read_pcal_info_2413()
1365 * Pd gain 0 is not the last pd gain in ath5k_eeprom_read_pcal_info_2413()
1367 * Continue with pd gain 1. in ath5k_eeprom_read_pcal_info_2413()
1369 pcinfo->pwr_i[1] = (val >> 10) & 0x1f; in ath5k_eeprom_read_pcal_info_2413()
1371 pcinfo->pddac_i[1] = (val >> 15) & 0x1; in ath5k_eeprom_read_pcal_info_2413()
1372 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1373 pcinfo->pddac_i[1] |= (val & 0x3F) << 1; in ath5k_eeprom_read_pcal_info_2413()
1375 pcinfo->pwr[1][0] = (val >> 6) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1376 pcinfo->pddac[1][0] = (val >> 10) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1378 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1379 pcinfo->pwr[1][1] = val & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1380 pcinfo->pddac[1][1] = (val >> 4) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1381 pcinfo->pwr[1][2] = (val >> 10) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1383 pcinfo->pddac[1][2] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1384 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1385 pcinfo->pddac[1][2] |= (val & 0xF) << 2; in ath5k_eeprom_read_pcal_info_2413()
1387 pcinfo->pwr[1][3] = 0; in ath5k_eeprom_read_pcal_info_2413()
1388 pcinfo->pddac[1][3] = 0; in ath5k_eeprom_read_pcal_info_2413()
1391 * Pd gain 0 is the last one so in ath5k_eeprom_read_pcal_info_2413()
1394 pcinfo->pwr[0][3] = (val >> 10) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1396 pcinfo->pddac[0][3] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1397 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1398 pcinfo->pddac[0][3] |= (val & 0xF) << 2; in ath5k_eeprom_read_pcal_info_2413()
1406 pcinfo->pwr_i[2] = (val >> 4) & 0x1f; in ath5k_eeprom_read_pcal_info_2413()
1407 pcinfo->pddac_i[2] = (val >> 9) & 0x7f; in ath5k_eeprom_read_pcal_info_2413()
1409 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1410 pcinfo->pwr[2][0] = (val >> 0) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1411 pcinfo->pddac[2][0] = (val >> 4) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1412 pcinfo->pwr[2][1] = (val >> 10) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1414 pcinfo->pddac[2][1] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1415 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1416 pcinfo->pddac[2][1] |= (val & 0xF) << 2; in ath5k_eeprom_read_pcal_info_2413()
1418 pcinfo->pwr[2][2] = (val >> 4) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1419 pcinfo->pddac[2][2] = (val >> 8) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1421 pcinfo->pwr[2][3] = 0; in ath5k_eeprom_read_pcal_info_2413()
1422 pcinfo->pddac[2][3] = 0; in ath5k_eeprom_read_pcal_info_2413()
1424 pcinfo->pwr[1][3] = (val >> 4) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1425 pcinfo->pddac[1][3] = (val >> 8) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1429 pcinfo->pwr_i[3] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1430 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1431 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2; in ath5k_eeprom_read_pcal_info_2413()
1433 pcinfo->pddac_i[3] = (val >> 3) & 0x7f; in ath5k_eeprom_read_pcal_info_2413()
1434 pcinfo->pwr[3][0] = (val >> 10) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1435 pcinfo->pddac[3][0] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1437 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1438 pcinfo->pddac[3][0] |= (val & 0xF) << 2; in ath5k_eeprom_read_pcal_info_2413()
1439 pcinfo->pwr[3][1] = (val >> 4) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1440 pcinfo->pddac[3][1] = (val >> 8) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1442 pcinfo->pwr[3][2] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1443 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1444 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2; in ath5k_eeprom_read_pcal_info_2413()
1446 pcinfo->pddac[3][2] = (val >> 2) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1447 pcinfo->pwr[3][3] = (val >> 8) & 0xf; in ath5k_eeprom_read_pcal_info_2413()
1449 pcinfo->pddac[3][3] = (val >> 12) & 0xF; in ath5k_eeprom_read_pcal_info_2413()
1450 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1451 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4; in ath5k_eeprom_read_pcal_info_2413()
1453 pcinfo->pwr[2][3] = (val >> 14) & 0x3; in ath5k_eeprom_read_pcal_info_2413()
1454 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_pcal_info_2413()
1455 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2; in ath5k_eeprom_read_pcal_info_2413()
1457 pcinfo->pddac[2][3] = (val >> 2) & 0x3f; in ath5k_eeprom_read_pcal_info_2413()
1475 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_target_rate_pwr_info()
1478 u32 offset; in ath5k_eeprom_read_target_rate_pwr_info() local
1482 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1); in ath5k_eeprom_read_target_rate_pwr_info()
1483 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode]; in ath5k_eeprom_read_target_rate_pwr_info()
1486 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version); in ath5k_eeprom_read_target_rate_pwr_info()
1487 rate_pcal_info = ee->ee_rate_tpwr_a; in ath5k_eeprom_read_target_rate_pwr_info()
1488 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_RATE_CHAN; in ath5k_eeprom_read_target_rate_pwr_info()
1491 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version); in ath5k_eeprom_read_target_rate_pwr_info()
1492 rate_pcal_info = ee->ee_rate_tpwr_b; in ath5k_eeprom_read_target_rate_pwr_info()
1493 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */ in ath5k_eeprom_read_target_rate_pwr_info()
1496 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version); in ath5k_eeprom_read_target_rate_pwr_info()
1497 rate_pcal_info = ee->ee_rate_tpwr_g; in ath5k_eeprom_read_target_rate_pwr_info()
1498 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN; in ath5k_eeprom_read_target_rate_pwr_info()
1501 return -EINVAL; in ath5k_eeprom_read_target_rate_pwr_info()
1505 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) { in ath5k_eeprom_read_target_rate_pwr_info()
1507 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_target_rate_pwr_info()
1514 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_target_rate_pwr_info()
1528 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_target_rate_pwr_info()
1535 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_target_rate_pwr_info()
1559 * offsets we pass on to phy chip (baseband -> before amplifier) so that
1563 * EEPROM provides us with the offsets for some pre-calibrated channels
1570 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info()
1575 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) && in ath5k_eeprom_read_pcal_info()
1576 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1)) in ath5k_eeprom_read_pcal_info()
1578 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) && in ath5k_eeprom_read_pcal_info()
1579 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2)) in ath5k_eeprom_read_pcal_info()
1603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_ctl_info()
1608 u32 offset; in ath5k_eeprom_read_ctl_info() local
1612 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1613 offset = AR5K_EEPROM_CTL(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1614 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1615 for (i = 0; i < ee->ee_ctls; i += 2) { in ath5k_eeprom_read_ctl_info()
1616 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1617 ee->ee_ctl[i] = (val >> 8) & 0xff; in ath5k_eeprom_read_ctl_info()
1618 ee->ee_ctl[i + 1] = val & 0xff; in ath5k_eeprom_read_ctl_info()
1621 offset = AR5K_EEPROM_GROUP8_OFFSET; in ath5k_eeprom_read_ctl_info()
1622 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0) in ath5k_eeprom_read_ctl_info()
1623 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) - in ath5k_eeprom_read_ctl_info()
1626 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1628 rep = ee->ee_ctl_pwr; in ath5k_eeprom_read_ctl_info()
1629 for (i = 0; i < ee->ee_ctls; i++) { in ath5k_eeprom_read_ctl_info()
1630 switch (ee->ee_ctl[i] & AR5K_CTL_MODE_M) { in ath5k_eeprom_read_ctl_info()
1639 if (ee->ee_ctl[i] == 0) { in ath5k_eeprom_read_ctl_info()
1640 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) in ath5k_eeprom_read_ctl_info()
1641 offset += 8; in ath5k_eeprom_read_ctl_info()
1643 offset += 7; in ath5k_eeprom_read_ctl_info()
1647 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { in ath5k_eeprom_read_ctl_info()
1649 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1654 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1661 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1666 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1671 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1676 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1683 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1688 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1693 AR5K_EEPROM_READ(offset++, val); in ath5k_eeprom_read_ctl_info()
1710 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_spur_chans()
1711 u32 offset; in ath5k_eeprom_read_spur_chans() local
1715 offset = AR5K_EEPROM_CTL(ee->ee_version) + in ath5k_eeprom_read_spur_chans()
1716 AR5K_EEPROM_N_CTLS(ee->ee_version); in ath5k_eeprom_read_spur_chans()
1718 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) { in ath5k_eeprom_read_spur_chans()
1720 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR; in ath5k_eeprom_read_spur_chans()
1722 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1; in ath5k_eeprom_read_spur_chans()
1723 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2; in ath5k_eeprom_read_spur_chans()
1724 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR; in ath5k_eeprom_read_spur_chans()
1725 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) { in ath5k_eeprom_read_spur_chans()
1727 AR5K_EEPROM_READ(offset, val); in ath5k_eeprom_read_spur_chans()
1728 ee->ee_spur_chans[i][0] = val; in ath5k_eeprom_read_spur_chans()
1729 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS, in ath5k_eeprom_read_spur_chans()
1731 ee->ee_spur_chans[i][1] = val; in ath5k_eeprom_read_spur_chans()
1732 offset++; in ath5k_eeprom_read_spur_chans()
1788 switch (channel->hw_value) { in ath5k_eeprom_mode_from_channel()