2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
27  * handle queue setup for 5210 chipset (rest are handled on qcu.c).
44  * ath5k_hw_start_rx_dma() - Start DMA receive
55  * ath5k_hw_stop_rx_dma() - Stop DMA receive
70 			i--)  in ath5k_hw_stop_rx_dma()
75 				"failed to stop RX DMA !\n");  in ath5k_hw_stop_rx_dma()
77 	return i ? 0 : -EBUSY;  in ath5k_hw_stop_rx_dma()
81  * ath5k_hw_get_rxdp() - Get RX Descriptor's address
91  * ath5k_hw_set_rxdp() - Set RX Descriptor's address
93  * @phys_addr: RX descriptor address
95  * Returns -EIO if rx is active
102 				"tried to set RXDP while rx was active !\n");  in ath5k_hw_set_rxdp()
103 		return -EIO;  in ath5k_hw_set_rxdp()
116  * ath5k_hw_start_tx_dma() - Start DMA transmit for a specific queue
118  * @queue: The hw queue number
120  * Start DMA transmit for a specific queue and since 5210 doesn't have
121  * QCU/DCU, set up queue parameters for 5210 here based on queue type (one
122  * queue for normal data and one queue for beacons). For queue setup
123  * on newer chips check out qcu.c. Returns -EINVAL if queue number is out
124  * of range or if queue is already disabled.
127  * queue (see below).
130 ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_start_tx_dma()  argument
134 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_start_tx_dma()
136 	/* Return if queue is declared inactive */  in ath5k_hw_start_tx_dma()
137 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_start_tx_dma()
138 		return -EINVAL;  in ath5k_hw_start_tx_dma()
140 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_start_tx_dma()
144 		 * Set the queue by type on 5210  in ath5k_hw_start_tx_dma()
146 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_start_tx_dma()
161 			return -EINVAL;  in ath5k_hw_start_tx_dma()
163 		/* Start queue */  in ath5k_hw_start_tx_dma()
167 		/* Return if queue is disabled */  in ath5k_hw_start_tx_dma()
168 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))  in ath5k_hw_start_tx_dma()
169 			return -EIO;  in ath5k_hw_start_tx_dma()
171 		/* Start queue */  in ath5k_hw_start_tx_dma()
172 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);  in ath5k_hw_start_tx_dma()
179  * ath5k_hw_stop_tx_dma() - Stop DMA transmit on a specific queue
181  * @queue: The hw queue number
183  * Stop DMA transmit on a specific hw queue and drain queue so we don't
184  * have any pending frames. Returns -EBUSY if we still have pending frames,
185  * -EINVAL if queue number is out of range or inactive.
188 ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_stop_tx_dma()  argument
193 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_stop_tx_dma()
195 	/* Return if queue is declared inactive */  in ath5k_hw_stop_tx_dma()
196 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_stop_tx_dma()
197 		return -EINVAL;  in ath5k_hw_stop_tx_dma()
199 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_stop_tx_dma()
203 		 * Set by queue type  in ath5k_hw_stop_tx_dma()
205 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_stop_tx_dma()
216 			return -EINVAL;  in ath5k_hw_stop_tx_dma()
219 		/* Stop queue */  in ath5k_hw_stop_tx_dma()
228 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_stop_tx_dma()
232 		 * Schedule TX disable and wait until queue is empty  in ath5k_hw_stop_tx_dma()
234 		AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);  in ath5k_hw_stop_tx_dma()
236 		/* Wait for queue to stop */  in ath5k_hw_stop_tx_dma()
238 		(AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue) != 0);  in ath5k_hw_stop_tx_dma()
239 		i--)  in ath5k_hw_stop_tx_dma()
242 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))  in ath5k_hw_stop_tx_dma()
244 				"queue %i didn't stop !\n", queue);  in ath5k_hw_stop_tx_dma()
250 				AR5K_QUEUE_STATUS(queue)) &  in ath5k_hw_stop_tx_dma()
253 		} while (--i && pending);  in ath5k_hw_stop_tx_dma()
257 		if (ah->ah_mac_version >= (AR5K_SREV_AR2414 >> 4) &&  in ath5k_hw_stop_tx_dma()
282 			/* Re-check for pending frames */  in ath5k_hw_stop_tx_dma()
286 					AR5K_QUEUE_STATUS(queue)) &  in ath5k_hw_stop_tx_dma()
289 			} while (--i && pending);  in ath5k_hw_stop_tx_dma()
297 					queue);  in ath5k_hw_stop_tx_dma()
303 		AR5K_REG_DISABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_stop_tx_dma()
311 					queue, pending);  in ath5k_hw_stop_tx_dma()
312 			return -EBUSY;  in ath5k_hw_stop_tx_dma()
321  * ath5k_hw_stop_beacon_queue() - Stop beacon queue
323  * @queue: The queue number
325  * Returns -EIO if queue didn't stop
328 ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_stop_beacon_queue()  argument
331 	ret = ath5k_hw_stop_tx_dma(ah, queue);  in ath5k_hw_stop_beacon_queue()
334 				"beacon queue didn't stop !\n");  in ath5k_hw_stop_beacon_queue()
335 		return -EIO;  in ath5k_hw_stop_beacon_queue()
341  * ath5k_hw_get_txdp() - Get TX Descriptor's address for a specific queue
343  * @queue: The hw queue number
345  * Get TX descriptor's address for a specific queue. For 5210 we ignore
346  * the queue number and use tx queue type since we only have 2 queues.
347  * We use TXDP0 for normal data queue and TXDP1 for beacon queue.
353 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_get_txdp()  argument
357 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_get_txdp()
360 	 * Get the transmit queue descriptor pointer from the selected queue  in ath5k_hw_get_txdp()
363 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_get_txdp()
364 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_get_txdp()
376 		tx_reg = AR5K_QUEUE_TXDP(queue);  in ath5k_hw_get_txdp()
383  * ath5k_hw_set_txdp() - Set TX Descriptor's address for a specific queue
385  * @queue: The hw queue number
388  * Set TX descriptor's address for a specific queue. For 5210 we ignore
389  * the queue number and we use tx queue type since we only have 2 queues
390  * so as above we use TXDP0 for normal data queue and TXDP1 for beacon queue.
392  * Returns -EINVAL if queue type is invalid for 5210 and -EIO if queue is still
396 ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)  in ath5k_hw_set_txdp()  argument
400 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_set_txdp()
403 	 * Set the transmit queue descriptor pointer register by type  in ath5k_hw_set_txdp()
406 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_set_txdp()
407 		switch (ah->ah_txq[queue].tqi_type) {  in ath5k_hw_set_txdp()
416 			return -EINVAL;  in ath5k_hw_set_txdp()
420 		 * Set the transmit queue descriptor pointer for  in ath5k_hw_set_txdp()
421 		 * the selected queue on QCU for 5211+  in ath5k_hw_set_txdp()
422 		 * (this won't work if the queue is still active)  in ath5k_hw_set_txdp()
424 		if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))  in ath5k_hw_set_txdp()
425 			return -EIO;  in ath5k_hw_set_txdp()
427 		tx_reg = AR5K_QUEUE_TXDP(queue);  in ath5k_hw_set_txdp()
437  * ath5k_hw_update_tx_triglevel() - Update tx trigger level
447  * flag. Returns -EIO if we have reached maximum/minimum.
456 	int ret = -EIO;  in ath5k_hw_update_tx_triglevel()
461 	imr = ath5k_hw_set_imr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);  in ath5k_hw_update_tx_triglevel()
467 		if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)  in ath5k_hw_update_tx_triglevel()
471 			((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);  in ath5k_hw_update_tx_triglevel()
476 	if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_update_tx_triglevel()
499  * ath5k_hw_is_intr_pending() - Check if we have pending interrupts
512  * ath5k_hw_get_isr() - Get interrupt status
520  * being mapped on some standard non hw-specific positions
523  * NOTE: We do write-to-clear, so the active PISR/SISR bits at the time this
537 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_get_isr()
542 			return -ENODEV;  in ath5k_hw_get_isr()
546 		 * Filter out the non-common bits from the interrupt  in ath5k_hw_get_isr()
549 		*interrupt_mask = (isr & AR5K_INT_COMMON) & ah->ah_imr;  in ath5k_hw_get_isr()
559 		 * true we should disable them before assoc and re-enable them  in ath5k_hw_get_isr()
578 			return -ENODEV;  in ath5k_hw_get_isr()
591 		 * TXOK and TXDESC  -> Logical OR of TXOK and TXDESC  in ath5k_hw_get_isr()
592 		 *			per-queue bits on SISR0  in ath5k_hw_get_isr()
594 		 * TXERR and TXEOL -> Logical OR of TXERR and TXEOL  in ath5k_hw_get_isr()
595 		 *			per-queue bits on SISR1  in ath5k_hw_get_isr()
597 		 * TXURN -> Logical OR of TXURN per-queue bits on SISR2  in ath5k_hw_get_isr()
599 		 * HIUERR -> Logical OR of MCABT, SSERR and DPER bits on SISR2  in ath5k_hw_get_isr()
601 		 * BCNMISC -> Logical OR of TIM, CAB_END, DTIM_SYNC  in ath5k_hw_get_isr()
605 		 * QCBRORN and QCBRURN -> Logical OR of QCBRORN and  in ath5k_hw_get_isr()
606 		 *			QCBRURN per-queue bits on SISR3  in ath5k_hw_get_isr()
607 		 * QTRIG -> Logical OR of QTRIG per-queue bits on SISR4  in ath5k_hw_get_isr()
612 		 * interrupt got fired for another queue while we were reading  in ath5k_hw_get_isr()
648 		 * Filter out the non-common bits from the interrupt  in ath5k_hw_get_isr()
651 		*interrupt_mask = (pisr & AR5K_INT_COMMON) & ah->ah_imr;  in ath5k_hw_get_isr()
653 		ah->ah_txq_isr_txok_all = 0;  in ath5k_hw_get_isr()
657 		 * so we track them all together per queue */  in ath5k_hw_get_isr()
659 			ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,  in ath5k_hw_get_isr()
663 			ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr0,  in ath5k_hw_get_isr()
667 			ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,  in ath5k_hw_get_isr()
671 			ah->ah_txq_isr_txok_all |= AR5K_REG_MS(sisr1,  in ath5k_hw_get_isr()
705 		/* A queue got CBR overrun */  in ath5k_hw_get_isr()
709 		/* A queue got CBR underrun */  in ath5k_hw_get_isr()
713 		/* A queue got triggered */  in ath5k_hw_get_isr()
725 		ATH5K_PRINTF("ISR: 0x%08x IMR: 0x%08x\n", data, ah->ah_imr);  in ath5k_hw_get_isr()
731  * ath5k_hw_set_imr() - Set interrupt mask
736  * ath5k_int bits to hw-specific bits to remove abstraction and writing
744 	old_mask = ah->ah_imr;  in ath5k_hw_set_imr()
748 	 * (they will be re-enabled afterwards if AR5K_INT GLOBAL  in ath5k_hw_set_imr()
757 	 * Add additional, chipset-dependent interrupt mask flags  in ath5k_hw_set_imr()
762 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_set_imr()
763 		/* Preserve per queue TXURN interrupt mask */  in ath5k_hw_set_imr()
793 		/* Note: Per queue interrupt masks  in ath5k_hw_set_imr()
814 	ah->ah_imr = new_mask;  in ath5k_hw_set_imr()
816 	/* ..re-enable interrupts if AR5K_INT_GLOBAL is set */  in ath5k_hw_set_imr()
831  * ath5k_hw_dma_init() - Initialize DMA unit
834  * Set DMA size and pre-enable interrupts
835  * (driver handles tx/rx buffer setup and
844 	 * Set Rx/Tx DMA Configuration  in ath5k_hw_dma_init()
847 	 * a DMA size of 512 causes rx overruns and tx errors  in ath5k_hw_dma_init()
848 	 * on pci-e cards (tested on 5424 but since rx overruns  in ath5k_hw_dma_init()
850 	 * for all PCI-E cards to be safe).  in ath5k_hw_dma_init()
854 	 * guess we can tweak it and see how it goes ;-)  in ath5k_hw_dma_init()
856 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_dma_init()
863 	/* Pre-enable interrupts on 5211/5212*/  in ath5k_hw_dma_init()
864 	if (ah->ah_version != AR5K_AR5210)  in ath5k_hw_dma_init()
865 		ath5k_hw_set_imr(ah, ah->ah_imr);  in ath5k_hw_dma_init()
870  * ath5k_hw_dma_stop() - stop DMA unit
873  * Stop tx/rx DMA and interrupts. Returns
874  * -EBUSY if tx or rx dma failed to stop.
889 	/* Stop rx dma */  in ath5k_hw_dma_stop()
896 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_dma_stop()
907 		/* -EINVAL -> queue inactive */  in ath5k_hw_dma_stop()
908 		if (err && err != -EINVAL)  in ath5k_hw_dma_stop()