Lines Matching +full:fw +full:- +full:cfg +full:- +full:mmio
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <linux/dma-mapping.h>
254 return HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_id_offset()
259 return HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_msi1_base_lsb_offset()
264 return HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_msi1_base_msb_offset()
269 return HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_msi1_data_offset()
274 return HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_base_msb_offset()
279 return HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_producer_int_setup_offset()
284 return HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_hp_addr_lsb_offset()
289 return HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_hp_addr_msb_offset()
294 return HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_reo1_ring_misc_offset()
299 return !!le16_get_bits(desc->u.qcn9274.msdu_end.info5, in ath12k_hw_qcn9274_rx_desc_get_first_msdu()
305 return !!le16_get_bits(desc->u.qcn9274.msdu_end.info5, in ath12k_hw_qcn9274_rx_desc_get_last_msdu()
311 return le16_get_bits(desc->u.qcn9274.msdu_end.info5, in ath12k_hw_qcn9274_rx_desc_get_l3_pad_bytes()
317 return !!le32_get_bits(desc->u.qcn9274.mpdu_start.info4, in ath12k_hw_qcn9274_rx_desc_encrypt_valid()
323 return le32_get_bits(desc->u.qcn9274.mpdu_start.info2, in ath12k_hw_qcn9274_rx_desc_get_encrypt_type()
329 return le32_get_bits(desc->u.qcn9274.msdu_end.info11, in ath12k_hw_qcn9274_rx_desc_get_decap_type()
335 return le32_get_bits(desc->u.qcn9274.msdu_end.info11, in ath12k_hw_qcn9274_rx_desc_get_mesh_ctl()
341 return !!le32_get_bits(desc->u.qcn9274.mpdu_start.info4, in ath12k_hw_qcn9274_rx_desc_get_mpdu_seq_ctl_vld()
347 return !!le32_get_bits(desc->u.qcn9274.mpdu_start.info4, in ath12k_hw_qcn9274_rx_desc_get_mpdu_fc_valid()
353 return le32_get_bits(desc->u.qcn9274.mpdu_start.info4, in ath12k_hw_qcn9274_rx_desc_get_mpdu_start_seq_no()
359 return le32_get_bits(desc->u.qcn9274.msdu_end.info10, in ath12k_hw_qcn9274_rx_desc_get_msdu_len()
365 return le32_get_bits(desc->u.qcn9274.msdu_end.info12, in ath12k_hw_qcn9274_rx_desc_get_msdu_sgi()
371 return le32_get_bits(desc->u.qcn9274.msdu_end.info12, in ath12k_hw_qcn9274_rx_desc_get_msdu_rate_mcs()
377 return le32_get_bits(desc->u.qcn9274.msdu_end.info12, in ath12k_hw_qcn9274_rx_desc_get_msdu_rx_bw()
383 return __le32_to_cpu(desc->u.qcn9274.msdu_end.phy_meta_data); in ath12k_hw_qcn9274_rx_desc_get_msdu_freq()
388 return le32_get_bits(desc->u.qcn9274.msdu_end.info12, in ath12k_hw_qcn9274_rx_desc_get_msdu_pkt_type()
394 return le32_get_bits(desc->u.qcn9274.msdu_end.info12, in ath12k_hw_qcn9274_rx_desc_get_msdu_nss()
400 return le16_get_bits(desc->u.qcn9274.msdu_end.info5, in ath12k_hw_qcn9274_rx_desc_get_mpdu_tid()
406 return __le16_to_cpu(desc->u.qcn9274.mpdu_start.sw_peer_id); in ath12k_hw_qcn9274_rx_desc_get_mpdu_peer_id()
412 memcpy(&fdesc->u.qcn9274.msdu_end, &ldesc->u.qcn9274.msdu_end, in ath12k_hw_qcn9274_rx_desc_copy_end_tlv()
418 return __le16_to_cpu(desc->u.qcn9274.mpdu_start.phy_ppdu_id); in ath12k_hw_qcn9274_rx_desc_get_mpdu_ppdu_id()
423 u32 info = __le32_to_cpu(desc->u.qcn9274.msdu_end.info10); in ath12k_hw_qcn9274_rx_desc_set_msdu_len()
428 desc->u.qcn9274.msdu_end.info10 = __cpu_to_le32(info); in ath12k_hw_qcn9274_rx_desc_set_msdu_len()
433 return &desc->u.qcn9274.msdu_payload[0]; in ath12k_hw_qcn9274_rx_desc_get_msdu_payload()
448 return __le32_to_cpu(desc->u.qcn9274.mpdu_start.info4) & in ath12k_hw_qcn9274_rx_desc_mac_addr2_valid()
454 return desc->u.qcn9274.mpdu_start.addr2; in ath12k_hw_qcn9274_rx_desc_mpdu_start_addr2()
459 return __le16_to_cpu(desc->u.qcn9274.msdu_end.info5) & in ath12k_hw_qcn9274_rx_desc_is_da_mcbc()
466 hdr->frame_control = desc->u.qcn9274.mpdu_start.frame_ctrl; in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
467 hdr->duration_id = desc->u.qcn9274.mpdu_start.duration; in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
468 ether_addr_copy(hdr->addr1, desc->u.qcn9274.mpdu_start.addr1); in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
469 ether_addr_copy(hdr->addr2, desc->u.qcn9274.mpdu_start.addr2); in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
470 ether_addr_copy(hdr->addr3, desc->u.qcn9274.mpdu_start.addr3); in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
471 if (__le32_to_cpu(desc->u.qcn9274.mpdu_start.info4) & in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
473 ether_addr_copy(hdr->addr4, desc->u.qcn9274.mpdu_start.addr4); in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
475 hdr->seq_ctrl = desc->u.qcn9274.mpdu_start.seq_ctrl; in ath12k_hw_qcn9274_rx_desc_get_dot11_hdr()
490 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274.mpdu_start.pn[0]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
493 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274.mpdu_start.pn[0]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
500 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274.mpdu_start.pn[0]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
502 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274.mpdu_start.pn[0]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
512 key_id = le32_get_bits(desc->u.qcn9274.mpdu_start.info5, in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
515 crypto_hdr[4] = HAL_RX_MPDU_INFO_PN_GET_BYTE3(desc->u.qcn9274.mpdu_start.pn[0]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
516 crypto_hdr[5] = HAL_RX_MPDU_INFO_PN_GET_BYTE4(desc->u.qcn9274.mpdu_start.pn[0]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
517 crypto_hdr[6] = HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274.mpdu_start.pn[1]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
518 crypto_hdr[7] = HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274.mpdu_start.pn[1]); in ath12k_hw_qcn9274_rx_desc_get_crypto_hdr()
523 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_create_config_qcn9274()
526 hal->srng_config = kmemdup(hw_srng_config_template, in ath12k_hal_srng_create_config_qcn9274()
529 if (!hal->srng_config) in ath12k_hal_srng_create_config_qcn9274()
530 return -ENOMEM; in ath12k_hal_srng_create_config_qcn9274()
532 s = &hal->srng_config[HAL_REO_DST]; in ath12k_hal_srng_create_config_qcn9274()
533 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
534 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
535 s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
536 s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
538 s = &hal->srng_config[HAL_REO_EXCEPTION]; in ath12k_hal_srng_create_config_qcn9274()
539 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
540 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
542 s = &hal->srng_config[HAL_REO_REINJECT]; in ath12k_hal_srng_create_config_qcn9274()
543 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
544 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
545 s->reg_size[0] = HAL_SW2REO1_RING_BASE_LSB(ab) - HAL_SW2REO_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
546 s->reg_size[1] = HAL_SW2REO1_RING_HP - HAL_SW2REO_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
548 s = &hal->srng_config[HAL_REO_CMD]; in ath12k_hal_srng_create_config_qcn9274()
549 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
550 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; in ath12k_hal_srng_create_config_qcn9274()
552 s = &hal->srng_config[HAL_REO_STATUS]; in ath12k_hal_srng_create_config_qcn9274()
553 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
554 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; in ath12k_hal_srng_create_config_qcn9274()
556 s = &hal->srng_config[HAL_TCL_DATA]; in ath12k_hal_srng_create_config_qcn9274()
557 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
558 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
559 s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
560 s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
562 s = &hal->srng_config[HAL_TCL_CMD]; in ath12k_hal_srng_create_config_qcn9274()
563 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
564 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
566 s = &hal->srng_config[HAL_TCL_STATUS]; in ath12k_hal_srng_create_config_qcn9274()
567 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
568 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
570 s = &hal->srng_config[HAL_CE_SRC]; in ath12k_hal_srng_create_config_qcn9274()
571 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
572 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
573 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - in ath12k_hal_srng_create_config_qcn9274()
575 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - in ath12k_hal_srng_create_config_qcn9274()
578 s = &hal->srng_config[HAL_CE_DST]; in ath12k_hal_srng_create_config_qcn9274()
579 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
580 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
581 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_qcn9274()
583 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_qcn9274()
586 s = &hal->srng_config[HAL_CE_DST_STATUS]; in ath12k_hal_srng_create_config_qcn9274()
587 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + in ath12k_hal_srng_create_config_qcn9274()
589 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
590 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_qcn9274()
592 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_qcn9274()
595 s = &hal->srng_config[HAL_WBM_IDLE_LINK]; in ath12k_hal_srng_create_config_qcn9274()
596 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
597 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
599 s = &hal->srng_config[HAL_SW2WBM_RELEASE]; in ath12k_hal_srng_create_config_qcn9274()
600 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + in ath12k_hal_srng_create_config_qcn9274()
602 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
603 s->reg_size[0] = HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) - in ath12k_hal_srng_create_config_qcn9274()
605 s->reg_size[1] = HAL_WBM_SW1_RELEASE_RING_HP - HAL_WBM_SW_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
607 s = &hal->srng_config[HAL_WBM2SW_RELEASE]; in ath12k_hal_srng_create_config_qcn9274()
608 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_qcn9274()
609 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
610 s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) - in ath12k_hal_srng_create_config_qcn9274()
612 s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
619 s = &hal->srng_config[HAL_PPE2TCL]; in ath12k_hal_srng_create_config_qcn9274()
620 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB; in ath12k_hal_srng_create_config_qcn9274()
621 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
623 s = &hal->srng_config[HAL_PPE_RELEASE]; in ath12k_hal_srng_create_config_qcn9274()
624 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + in ath12k_hal_srng_create_config_qcn9274()
626 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP; in ath12k_hal_srng_create_config_qcn9274()
648 return !!le32_get_bits(desc->u.qcn9274.msdu_end.info14, in ath12k_hw_qcn9274_dp_rx_h_msdu_done()
654 return !!le32_get_bits(desc->u.qcn9274.msdu_end.info13, in ath12k_hw_qcn9274_dp_rx_h_l4_cksum_fail()
660 return !!le32_get_bits(desc->u.qcn9274.msdu_end.info13, in ath12k_hw_qcn9274_dp_rx_h_ip_cksum_fail()
666 return (le32_get_bits(desc->u.qcn9274.msdu_end.info14, in ath12k_hw_qcn9274_dp_rx_h_is_decrypted()
673 u32 info = __le32_to_cpu(desc->u.qcn9274.msdu_end.info13); in ath12k_hw_qcn9274_dp_rx_h_mpdu_err()
752 return !!le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, in ath12k_hw_qcn9274_compact_rx_desc_get_first_msdu()
758 return !!le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, in ath12k_hw_qcn9274_compact_rx_desc_get_last_msdu()
764 return le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, in ath12k_hw_qcn9274_compact_rx_desc_get_l3_pad_bytes()
770 return !!le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, in ath12k_hw_qcn9274_compact_rx_desc_encrypt_valid()
776 return le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info2, in ath12k_hw_qcn9274_compact_rx_desc_get_encrypt_type()
782 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info11, in ath12k_hw_qcn9274_compact_rx_desc_get_decap_type()
788 return le32_get_bits(desc->u.qcn9274.msdu_end.info11, in ath12k_hw_qcn9274_compact_rx_desc_get_mesh_ctl()
795 return !!le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, in ath12k_hw_qcn9274_compact_rx_desc_get_mpdu_seq_ctl_vld()
801 return !!le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, in ath12k_hw_qcn9274_compact_rx_desc_get_mpdu_fc_valid()
808 return le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info4, in ath12k_hw_qcn9274_compact_rx_desc_get_mpdu_start_seq_no()
814 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info10, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_len()
820 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_sgi()
826 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_rate_mcs()
832 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_rx_bw()
838 return __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.phy_meta_data); in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_freq()
843 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_pkt_type()
849 return le32_get_bits(desc->u.qcn9274_compact.msdu_end.info12, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_nss()
855 return le16_get_bits(desc->u.qcn9274_compact.msdu_end.info5, in ath12k_hw_qcn9274_compact_rx_desc_get_mpdu_tid()
861 return __le16_to_cpu(desc->u.qcn9274_compact.mpdu_start.sw_peer_id); in ath12k_hw_qcn9274_compact_rx_desc_get_mpdu_peer_id()
867 fdesc->u.qcn9274_compact.msdu_end = ldesc->u.qcn9274_compact.msdu_end; in ath12k_hw_qcn9274_compact_rx_desc_copy_end_tlv()
872 return __le16_to_cpu(desc->u.qcn9274_compact.mpdu_start.phy_ppdu_id); in ath12k_hw_qcn9274_compact_rx_desc_get_mpdu_ppdu_id()
878 u32 info = __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.info10); in ath12k_hw_qcn9274_compact_rx_desc_set_msdu_len()
881 desc->u.qcn9274_compact.msdu_end.info10 = __cpu_to_le32(info); in ath12k_hw_qcn9274_compact_rx_desc_set_msdu_len()
886 return &desc->u.qcn9274_compact.msdu_payload[0]; in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_payload()
901 return __le32_to_cpu(desc->u.qcn9274_compact.mpdu_start.info4) & in ath12k_hw_qcn9274_compact_rx_desc_mac_addr2_valid()
907 return desc->u.qcn9274_compact.mpdu_start.addr2; in ath12k_hw_qcn9274_compact_rx_desc_mpdu_start_addr2()
912 return __le16_to_cpu(desc->u.qcn9274_compact.msdu_end.info5) & in ath12k_hw_qcn9274_compact_rx_desc_is_da_mcbc()
919 hdr->frame_control = desc->u.qcn9274_compact.mpdu_start.frame_ctrl; in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
920 hdr->duration_id = desc->u.qcn9274_compact.mpdu_start.duration; in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
921 ether_addr_copy(hdr->addr1, desc->u.qcn9274_compact.mpdu_start.addr1); in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
922 ether_addr_copy(hdr->addr2, desc->u.qcn9274_compact.mpdu_start.addr2); in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
923 ether_addr_copy(hdr->addr3, desc->u.qcn9274_compact.mpdu_start.addr3); in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
924 if (__le32_to_cpu(desc->u.qcn9274_compact.mpdu_start.info4) & in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
926 ether_addr_copy(hdr->addr4, desc->u.qcn9274_compact.mpdu_start.addr4); in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
928 hdr->seq_ctrl = desc->u.qcn9274_compact.mpdu_start.seq_ctrl; in ath12k_hw_qcn9274_compact_rx_desc_get_dot11_hdr()
944 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274_compact.mpdu_start.pn[0]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
947 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274_compact.mpdu_start.pn[0]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
954 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274_compact.mpdu_start.pn[0]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
956 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274_compact.mpdu_start.pn[0]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
966 key_id = le32_get_bits(desc->u.qcn9274_compact.mpdu_start.info5, in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
970 HAL_RX_MPDU_INFO_PN_GET_BYTE3(desc->u.qcn9274_compact.mpdu_start.pn[0]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
972 HAL_RX_MPDU_INFO_PN_GET_BYTE4(desc->u.qcn9274_compact.mpdu_start.pn[0]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
974 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.qcn9274_compact.mpdu_start.pn[1]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
976 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274_compact.mpdu_start.pn[1]); in ath12k_hw_qcn9274_compact_rx_desc_get_crypto_hdr()
981 return !!le32_get_bits(desc->u.qcn9274_compact.msdu_end.info14, in ath12k_hw_qcn9274_compact_dp_rx_h_msdu_done()
987 return !!le32_get_bits(desc->u.qcn9274_compact.msdu_end.info13, in ath12k_hw_qcn9274_compact_dp_rx_h_l4_cksum_fail()
993 return !!le32_get_bits(desc->u.qcn9274_compact.msdu_end.info13, in ath12k_hw_qcn9274_compact_dp_rx_h_ip_cksum_fail()
999 return (le32_get_bits(desc->u.qcn9274_compact.msdu_end.info14, in ath12k_hw_qcn9274_compact_dp_rx_h_is_decrypted()
1006 u32 info = __le32_to_cpu(desc->u.qcn9274_compact.msdu_end.info13); in ath12k_hw_qcn9274_compact_dp_rx_h_mpdu_err()
1040 return le64_get_bits(desc->u.qcn9274_compact.msdu_end.msdu_end_tag, in ath12k_hw_qcn9274_compact_rx_desc_get_msdu_src_link()
1099 return !!le16_get_bits(desc->u.wcn7850.msdu_end.info5, in ath12k_hw_wcn7850_rx_desc_get_first_msdu()
1105 return !!le16_get_bits(desc->u.wcn7850.msdu_end.info5, in ath12k_hw_wcn7850_rx_desc_get_last_msdu()
1111 return le16_get_bits(desc->u.wcn7850.msdu_end.info5, in ath12k_hw_wcn7850_rx_desc_get_l3_pad_bytes()
1117 return !!le32_get_bits(desc->u.wcn7850.mpdu_start.info4, in ath12k_hw_wcn7850_rx_desc_encrypt_valid()
1123 return le32_get_bits(desc->u.wcn7850.mpdu_start.info2, in ath12k_hw_wcn7850_rx_desc_get_encrypt_type()
1129 return le32_get_bits(desc->u.wcn7850.msdu_end.info11, in ath12k_hw_wcn7850_rx_desc_get_decap_type()
1135 return le32_get_bits(desc->u.wcn7850.msdu_end.info11, in ath12k_hw_wcn7850_rx_desc_get_mesh_ctl()
1141 return !!le32_get_bits(desc->u.wcn7850.mpdu_start.info4, in ath12k_hw_wcn7850_rx_desc_get_mpdu_seq_ctl_vld()
1147 return !!le32_get_bits(desc->u.wcn7850.mpdu_start.info4, in ath12k_hw_wcn7850_rx_desc_get_mpdu_fc_valid()
1153 return le32_get_bits(desc->u.wcn7850.mpdu_start.info4, in ath12k_hw_wcn7850_rx_desc_get_mpdu_start_seq_no()
1159 return le32_get_bits(desc->u.wcn7850.msdu_end.info10, in ath12k_hw_wcn7850_rx_desc_get_msdu_len()
1165 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, in ath12k_hw_wcn7850_rx_desc_get_msdu_sgi()
1171 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, in ath12k_hw_wcn7850_rx_desc_get_msdu_rate_mcs()
1177 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, in ath12k_hw_wcn7850_rx_desc_get_msdu_rx_bw()
1183 return __le32_to_cpu(desc->u.wcn7850.msdu_end.phy_meta_data); in ath12k_hw_wcn7850_rx_desc_get_msdu_freq()
1188 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, in ath12k_hw_wcn7850_rx_desc_get_msdu_pkt_type()
1194 return le32_get_bits(desc->u.wcn7850.msdu_end.info12, in ath12k_hw_wcn7850_rx_desc_get_msdu_nss()
1200 return le32_get_bits(desc->u.wcn7850.mpdu_start.info2, in ath12k_hw_wcn7850_rx_desc_get_mpdu_tid()
1206 return __le16_to_cpu(desc->u.wcn7850.mpdu_start.sw_peer_id); in ath12k_hw_wcn7850_rx_desc_get_mpdu_peer_id()
1212 memcpy(&fdesc->u.wcn7850.msdu_end, &ldesc->u.wcn7850.msdu_end, in ath12k_hw_wcn7850_rx_desc_copy_end_tlv()
1218 return le64_get_bits(desc->u.wcn7850.mpdu_start_tag, in ath12k_hw_wcn7850_rx_desc_get_mpdu_start_tag()
1224 return __le16_to_cpu(desc->u.wcn7850.mpdu_start.phy_ppdu_id); in ath12k_hw_wcn7850_rx_desc_get_mpdu_ppdu_id()
1229 u32 info = __le32_to_cpu(desc->u.wcn7850.msdu_end.info10); in ath12k_hw_wcn7850_rx_desc_set_msdu_len()
1234 desc->u.wcn7850.msdu_end.info10 = __cpu_to_le32(info); in ath12k_hw_wcn7850_rx_desc_set_msdu_len()
1239 return &desc->u.wcn7850.msdu_payload[0]; in ath12k_hw_wcn7850_rx_desc_get_msdu_payload()
1254 return __le32_to_cpu(desc->u.wcn7850.mpdu_start.info4) & in ath12k_hw_wcn7850_rx_desc_mac_addr2_valid()
1260 return desc->u.wcn7850.mpdu_start.addr2; in ath12k_hw_wcn7850_rx_desc_mpdu_start_addr2()
1265 return __le32_to_cpu(desc->u.wcn7850.msdu_end.info13) & in ath12k_hw_wcn7850_rx_desc_is_da_mcbc()
1272 hdr->frame_control = desc->u.wcn7850.mpdu_start.frame_ctrl; in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1273 hdr->duration_id = desc->u.wcn7850.mpdu_start.duration; in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1274 ether_addr_copy(hdr->addr1, desc->u.wcn7850.mpdu_start.addr1); in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1275 ether_addr_copy(hdr->addr2, desc->u.wcn7850.mpdu_start.addr2); in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1276 ether_addr_copy(hdr->addr3, desc->u.wcn7850.mpdu_start.addr3); in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1277 if (__le32_to_cpu(desc->u.wcn7850.mpdu_start.info4) & in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1279 ether_addr_copy(hdr->addr4, desc->u.wcn7850.mpdu_start.addr4); in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1281 hdr->seq_ctrl = desc->u.wcn7850.mpdu_start.seq_ctrl; in ath12k_hw_wcn7850_rx_desc_get_dot11_hdr()
1296 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[0]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1299 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.wcn7850.mpdu_start.pn[0]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1306 HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.wcn7850.mpdu_start.pn[0]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1308 HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[0]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1318 key_id = u32_get_bits(__le32_to_cpu(desc->u.wcn7850.mpdu_start.info5), in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1321 crypto_hdr[4] = HAL_RX_MPDU_INFO_PN_GET_BYTE3(desc->u.wcn7850.mpdu_start.pn[0]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1322 crypto_hdr[5] = HAL_RX_MPDU_INFO_PN_GET_BYTE4(desc->u.wcn7850.mpdu_start.pn[0]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1323 crypto_hdr[6] = HAL_RX_MPDU_INFO_PN_GET_BYTE1(desc->u.wcn7850.mpdu_start.pn[1]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1324 crypto_hdr[7] = HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[1]); in ath12k_hw_wcn7850_rx_desc_get_crypto_hdr()
1329 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_create_config_wcn7850()
1332 hal->srng_config = kmemdup(hw_srng_config_template, in ath12k_hal_srng_create_config_wcn7850()
1335 if (!hal->srng_config) in ath12k_hal_srng_create_config_wcn7850()
1336 return -ENOMEM; in ath12k_hal_srng_create_config_wcn7850()
1338 s = &hal->srng_config[HAL_REO_DST]; in ath12k_hal_srng_create_config_wcn7850()
1339 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1340 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1341 s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1342 s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1344 s = &hal->srng_config[HAL_REO_EXCEPTION]; in ath12k_hal_srng_create_config_wcn7850()
1345 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1346 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_SW0_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1348 s = &hal->srng_config[HAL_REO_REINJECT]; in ath12k_hal_srng_create_config_wcn7850()
1349 s->max_rings = 1; in ath12k_hal_srng_create_config_wcn7850()
1350 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1351 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1353 s = &hal->srng_config[HAL_REO_CMD]; in ath12k_hal_srng_create_config_wcn7850()
1354 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1355 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; in ath12k_hal_srng_create_config_wcn7850()
1357 s = &hal->srng_config[HAL_REO_STATUS]; in ath12k_hal_srng_create_config_wcn7850()
1358 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1359 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; in ath12k_hal_srng_create_config_wcn7850()
1361 s = &hal->srng_config[HAL_TCL_DATA]; in ath12k_hal_srng_create_config_wcn7850()
1362 s->max_rings = 5; in ath12k_hal_srng_create_config_wcn7850()
1363 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1364 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1365 s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1366 s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1368 s = &hal->srng_config[HAL_TCL_CMD]; in ath12k_hal_srng_create_config_wcn7850()
1369 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1370 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1372 s = &hal->srng_config[HAL_TCL_STATUS]; in ath12k_hal_srng_create_config_wcn7850()
1373 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1374 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1376 s = &hal->srng_config[HAL_CE_SRC]; in ath12k_hal_srng_create_config_wcn7850()
1377 s->max_rings = 12; in ath12k_hal_srng_create_config_wcn7850()
1378 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()
1379 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1380 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - in ath12k_hal_srng_create_config_wcn7850()
1382 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - in ath12k_hal_srng_create_config_wcn7850()
1385 s = &hal->srng_config[HAL_CE_DST]; in ath12k_hal_srng_create_config_wcn7850()
1386 s->max_rings = 12; in ath12k_hal_srng_create_config_wcn7850()
1387 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB; in ath12k_hal_srng_create_config_wcn7850()
1388 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1389 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_wcn7850()
1391 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_wcn7850()
1394 s = &hal->srng_config[HAL_CE_DST_STATUS]; in ath12k_hal_srng_create_config_wcn7850()
1395 s->max_rings = 12; in ath12k_hal_srng_create_config_wcn7850()
1396 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + in ath12k_hal_srng_create_config_wcn7850()
1398 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1399 s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_wcn7850()
1401 s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - in ath12k_hal_srng_create_config_wcn7850()
1404 s = &hal->srng_config[HAL_WBM_IDLE_LINK]; in ath12k_hal_srng_create_config_wcn7850()
1405 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1406 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1408 s = &hal->srng_config[HAL_SW2WBM_RELEASE]; in ath12k_hal_srng_create_config_wcn7850()
1409 s->max_rings = 1; in ath12k_hal_srng_create_config_wcn7850()
1410 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + in ath12k_hal_srng_create_config_wcn7850()
1412 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_SW_RELEASE_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1414 s = &hal->srng_config[HAL_WBM2SW_RELEASE]; in ath12k_hal_srng_create_config_wcn7850()
1415 s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB(ab); in ath12k_hal_srng_create_config_wcn7850()
1416 s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1417 s->reg_size[0] = HAL_WBM1_RELEASE_RING_BASE_LSB(ab) - in ath12k_hal_srng_create_config_wcn7850()
1419 s->reg_size[1] = HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; in ath12k_hal_srng_create_config_wcn7850()
1421 s = &hal->srng_config[HAL_RXDMA_BUF]; in ath12k_hal_srng_create_config_wcn7850()
1422 s->max_rings = 2; in ath12k_hal_srng_create_config_wcn7850()
1423 s->mac_type = ATH12K_HAL_SRNG_PMAC; in ath12k_hal_srng_create_config_wcn7850()
1425 s = &hal->srng_config[HAL_RXDMA_DST]; in ath12k_hal_srng_create_config_wcn7850()
1426 s->max_rings = 1; in ath12k_hal_srng_create_config_wcn7850()
1427 s->entry_size = sizeof(struct hal_reo_entrance_ring) >> 2; in ath12k_hal_srng_create_config_wcn7850()
1430 s = &hal->srng_config[HAL_RXDMA_DIR_BUF]; in ath12k_hal_srng_create_config_wcn7850()
1431 s->max_rings = 0; in ath12k_hal_srng_create_config_wcn7850()
1433 s = &hal->srng_config[HAL_PPE2TCL]; in ath12k_hal_srng_create_config_wcn7850()
1434 s->max_rings = 0; in ath12k_hal_srng_create_config_wcn7850()
1436 s = &hal->srng_config[HAL_PPE_RELEASE]; in ath12k_hal_srng_create_config_wcn7850()
1437 s->max_rings = 0; in ath12k_hal_srng_create_config_wcn7850()
1439 s = &hal->srng_config[HAL_TX_MONITOR_BUF]; in ath12k_hal_srng_create_config_wcn7850()
1440 s->max_rings = 0; in ath12k_hal_srng_create_config_wcn7850()
1442 s = &hal->srng_config[HAL_TX_MONITOR_DST]; in ath12k_hal_srng_create_config_wcn7850()
1443 s->max_rings = 0; in ath12k_hal_srng_create_config_wcn7850()
1445 s = &hal->srng_config[HAL_PPE2TCL]; in ath12k_hal_srng_create_config_wcn7850()
1446 s->max_rings = 0; in ath12k_hal_srng_create_config_wcn7850()
1453 return !!le32_get_bits(desc->u.wcn7850.msdu_end.info14, in ath12k_hw_wcn7850_dp_rx_h_msdu_done()
1459 return !!le32_get_bits(desc->u.wcn7850.msdu_end.info13, in ath12k_hw_wcn7850_dp_rx_h_l4_cksum_fail()
1465 return !!le32_get_bits(desc->u.wcn7850.msdu_end.info13, in ath12k_hw_wcn7850_dp_rx_h_ip_cksum_fail()
1471 return (le32_get_bits(desc->u.wcn7850.msdu_end.info14, in ath12k_hw_wcn7850_dp_rx_h_is_decrypted()
1478 u32 info = __le32_to_cpu(desc->u.wcn7850.msdu_end.info13); in ath12k_hw_wcn7850_dp_rx_h_mpdu_err()
1566 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_alloc_cont_rdp()
1570 hal->rdp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->rdp.paddr, in ath12k_hal_alloc_cont_rdp()
1572 if (!hal->rdp.vaddr) in ath12k_hal_alloc_cont_rdp()
1573 return -ENOMEM; in ath12k_hal_alloc_cont_rdp()
1580 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_free_cont_rdp()
1583 if (!hal->rdp.vaddr) in ath12k_hal_free_cont_rdp()
1587 dma_free_coherent(ab->dev, size, in ath12k_hal_free_cont_rdp()
1588 hal->rdp.vaddr, hal->rdp.paddr); in ath12k_hal_free_cont_rdp()
1589 hal->rdp.vaddr = NULL; in ath12k_hal_free_cont_rdp()
1594 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_alloc_cont_wrp()
1598 hal->wrp.vaddr = dma_alloc_coherent(ab->dev, size, &hal->wrp.paddr, in ath12k_hal_alloc_cont_wrp()
1600 if (!hal->wrp.vaddr) in ath12k_hal_alloc_cont_wrp()
1601 return -ENOMEM; in ath12k_hal_alloc_cont_wrp()
1608 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_free_cont_wrp()
1611 if (!hal->wrp.vaddr) in ath12k_hal_free_cont_wrp()
1615 dma_free_coherent(ab->dev, size, in ath12k_hal_free_cont_wrp()
1616 hal->wrp.vaddr, hal->wrp.paddr); in ath12k_hal_free_cont_wrp()
1617 hal->wrp.vaddr = NULL; in ath12k_hal_free_cont_wrp()
1623 struct hal_srng_config *srng_config = &ab->hal.srng_config[HAL_CE_DST]; in ath12k_hal_ce_dst_setup()
1628 srng_config->reg_start[HAL_SRNG_REG_GRP_R0] + in ath12k_hal_ce_dst_setup()
1629 ring_num * srng_config->reg_size[HAL_SRNG_REG_GRP_R0]; in ath12k_hal_ce_dst_setup()
1633 val |= u32_encode_bits(srng->u.dst_ring.max_buffer_length, in ath12k_hal_ce_dst_setup()
1641 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_dst_hw_init()
1646 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath12k_hal_srng_dst_hw_init()
1648 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { in ath12k_hal_srng_dst_hw_init()
1651 srng->msi_addr); in ath12k_hal_srng_dst_hw_init()
1653 val = u32_encode_bits(((u64)srng->msi_addr >> HAL_ADDR_MSB_REG_SHIFT), in ath12k_hal_srng_dst_hw_init()
1661 srng->msi_data); in ath12k_hal_srng_dst_hw_init()
1664 ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr); in ath12k_hal_srng_dst_hw_init()
1666 val = u32_encode_bits(((u64)srng->ring_base_paddr >> HAL_ADDR_MSB_REG_SHIFT), in ath12k_hal_srng_dst_hw_init()
1668 u32_encode_bits((srng->entry_size * srng->num_entries), in ath12k_hal_srng_dst_hw_init()
1672 val = u32_encode_bits(srng->ring_id, HAL_REO1_RING_ID_RING_ID) | in ath12k_hal_srng_dst_hw_init()
1673 u32_encode_bits(srng->entry_size, HAL_REO1_RING_ID_ENTRY_SIZE); in ath12k_hal_srng_dst_hw_init()
1677 val = u32_encode_bits((srng->intr_timer_thres_us >> 3), in ath12k_hal_srng_dst_hw_init()
1680 val |= u32_encode_bits((srng->intr_batch_cntr_thres_entries * srng->entry_size), in ath12k_hal_srng_dst_hw_init()
1687 hp_addr = hal->rdp.paddr + in ath12k_hal_srng_dst_hw_init()
1688 ((unsigned long)srng->u.dst_ring.hp_addr - in ath12k_hal_srng_dst_hw_init()
1689 (unsigned long)hal->rdp.vaddr); in ath12k_hal_srng_dst_hw_init()
1696 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; in ath12k_hal_srng_dst_hw_init()
1699 *srng->u.dst_ring.hp_addr = 0; in ath12k_hal_srng_dst_hw_init()
1701 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath12k_hal_srng_dst_hw_init()
1703 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) in ath12k_hal_srng_dst_hw_init()
1705 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) in ath12k_hal_srng_dst_hw_init()
1707 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) in ath12k_hal_srng_dst_hw_init()
1717 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_src_hw_init()
1722 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath12k_hal_srng_src_hw_init()
1724 if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { in ath12k_hal_srng_src_hw_init()
1727 srng->msi_addr); in ath12k_hal_srng_src_hw_init()
1729 val = u32_encode_bits(((u64)srng->msi_addr >> HAL_ADDR_MSB_REG_SHIFT), in ath12k_hal_srng_src_hw_init()
1738 srng->msi_data); in ath12k_hal_srng_src_hw_init()
1741 ath12k_hif_write32(ab, reg_base, srng->ring_base_paddr); in ath12k_hal_srng_src_hw_init()
1743 val = u32_encode_bits(((u64)srng->ring_base_paddr >> HAL_ADDR_MSB_REG_SHIFT), in ath12k_hal_srng_src_hw_init()
1745 u32_encode_bits((srng->entry_size * srng->num_entries), in ath12k_hal_srng_src_hw_init()
1749 val = u32_encode_bits(srng->entry_size, HAL_REO1_RING_ID_ENTRY_SIZE); in ath12k_hal_srng_src_hw_init()
1752 val = u32_encode_bits(srng->intr_timer_thres_us, in ath12k_hal_srng_src_hw_init()
1755 val |= u32_encode_bits((srng->intr_batch_cntr_thres_entries * srng->entry_size), in ath12k_hal_srng_src_hw_init()
1763 if (srng->flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { in ath12k_hal_srng_src_hw_init()
1764 val |= u32_encode_bits(srng->u.src_ring.low_threshold, in ath12k_hal_srng_src_hw_init()
1771 if (srng->ring_id != HAL_SRNG_RING_ID_WBM_IDLE_LINK) { in ath12k_hal_srng_src_hw_init()
1772 tp_addr = hal->rdp.paddr + in ath12k_hal_srng_src_hw_init()
1773 ((unsigned long)srng->u.src_ring.tp_addr - in ath12k_hal_srng_src_hw_init()
1774 (unsigned long)hal->rdp.vaddr); in ath12k_hal_srng_src_hw_init()
1784 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; in ath12k_hal_srng_src_hw_init()
1787 *srng->u.src_ring.tp_addr = 0; in ath12k_hal_srng_src_hw_init()
1789 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; in ath12k_hal_srng_src_hw_init()
1791 if (srng->flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP) in ath12k_hal_srng_src_hw_init()
1793 if (srng->flags & HAL_SRNG_FLAGS_RING_PTR_SWAP) in ath12k_hal_srng_src_hw_init()
1795 if (srng->flags & HAL_SRNG_FLAGS_MSI_SWAP) in ath12k_hal_srng_src_hw_init()
1803 if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) in ath12k_hal_srng_src_hw_init()
1812 if (srng->ring_dir == HAL_SRNG_DIR_SRC) in ath12k_hal_srng_hw_init()
1822 struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; in ath12k_hal_srng_get_ring_id()
1825 if (ring_num >= srng_config->max_rings) { in ath12k_hal_srng_get_ring_id()
1827 return -EINVAL; in ath12k_hal_srng_get_ring_id()
1830 ring_id = srng_config->start_ring_id + ring_num; in ath12k_hal_srng_get_ring_id()
1831 if (srng_config->mac_type == ATH12K_HAL_SRNG_PMAC) in ath12k_hal_srng_get_ring_id()
1835 return -EINVAL; in ath12k_hal_srng_get_ring_id()
1845 return -EINVAL; in ath12k_hal_srng_get_entrysize()
1847 srng_config = &ab->hal.srng_config[ring_type]; in ath12k_hal_srng_get_entrysize()
1849 return (srng_config->entry_size << 2); in ath12k_hal_srng_get_entrysize()
1857 return -EINVAL; in ath12k_hal_srng_get_max_entries()
1859 srng_config = &ab->hal.srng_config[ring_type]; in ath12k_hal_srng_get_max_entries()
1861 return (srng_config->max_size / srng_config->entry_size); in ath12k_hal_srng_get_max_entries()
1867 params->ring_base_paddr = srng->ring_base_paddr; in ath12k_hal_srng_get_params()
1868 params->ring_base_vaddr = srng->ring_base_vaddr; in ath12k_hal_srng_get_params()
1869 params->num_entries = srng->num_entries; in ath12k_hal_srng_get_params()
1870 params->intr_timer_thres_us = srng->intr_timer_thres_us; in ath12k_hal_srng_get_params()
1871 params->intr_batch_cntr_thres_entries = in ath12k_hal_srng_get_params()
1872 srng->intr_batch_cntr_thres_entries; in ath12k_hal_srng_get_params()
1873 params->low_threshold = srng->u.src_ring.low_threshold; in ath12k_hal_srng_get_params()
1874 params->msi_addr = srng->msi_addr; in ath12k_hal_srng_get_params()
1875 params->msi2_addr = srng->msi2_addr; in ath12k_hal_srng_get_params()
1876 params->msi_data = srng->msi_data; in ath12k_hal_srng_get_params()
1877 params->msi2_data = srng->msi2_data; in ath12k_hal_srng_get_params()
1878 params->flags = srng->flags; in ath12k_hal_srng_get_params()
1884 if (!(srng->flags & HAL_SRNG_FLAGS_LMAC_RING)) in ath12k_hal_srng_get_hp_addr()
1887 if (srng->ring_dir == HAL_SRNG_DIR_SRC) in ath12k_hal_srng_get_hp_addr()
1888 return ab->hal.wrp.paddr + in ath12k_hal_srng_get_hp_addr()
1889 ((unsigned long)srng->u.src_ring.hp_addr - in ath12k_hal_srng_get_hp_addr()
1890 (unsigned long)ab->hal.wrp.vaddr); in ath12k_hal_srng_get_hp_addr()
1892 return ab->hal.rdp.paddr + in ath12k_hal_srng_get_hp_addr()
1893 ((unsigned long)srng->u.dst_ring.hp_addr - in ath12k_hal_srng_get_hp_addr()
1894 (unsigned long)ab->hal.rdp.vaddr); in ath12k_hal_srng_get_hp_addr()
1900 if (!(srng->flags & HAL_SRNG_FLAGS_LMAC_RING)) in ath12k_hal_srng_get_tp_addr()
1903 if (srng->ring_dir == HAL_SRNG_DIR_SRC) in ath12k_hal_srng_get_tp_addr()
1904 return ab->hal.rdp.paddr + in ath12k_hal_srng_get_tp_addr()
1905 ((unsigned long)srng->u.src_ring.tp_addr - in ath12k_hal_srng_get_tp_addr()
1906 (unsigned long)ab->hal.rdp.vaddr); in ath12k_hal_srng_get_tp_addr()
1908 return ab->hal.wrp.paddr + in ath12k_hal_srng_get_tp_addr()
1909 ((unsigned long)srng->u.dst_ring.tp_addr - in ath12k_hal_srng_get_tp_addr()
1910 (unsigned long)ab->hal.wrp.vaddr); in ath12k_hal_srng_get_tp_addr()
1930 desc->buffer_addr_low = cpu_to_le32(paddr & HAL_ADDR_LSB_REG_MASK); in ath12k_hal_ce_src_set_desc()
1931 desc->buffer_addr_info = in ath12k_hal_ce_src_set_desc()
1938 desc->meta_info = le32_encode_bits(id, HAL_CE_SRC_DESC_META_INFO_DATA); in ath12k_hal_ce_src_set_desc()
1943 desc->buffer_addr_low = cpu_to_le32(paddr & HAL_ADDR_LSB_REG_MASK); in ath12k_hal_ce_dst_set_desc()
1944 desc->buffer_addr_info = in ath12k_hal_ce_dst_set_desc()
1953 len = le32_get_bits(desc->flags, HAL_CE_DST_STATUS_DESC_FLAGS_LEN); in ath12k_hal_ce_dst_status_get_length()
1954 desc->flags &= ~cpu_to_le32(HAL_CE_DST_STATUS_DESC_FLAGS_LEN); in ath12k_hal_ce_dst_status_get_length()
1963 desc->buf_addr_info.info0 = le32_encode_bits((paddr & HAL_ADDR_LSB_REG_MASK), in ath12k_hal_set_link_desc_addr()
1965 desc->buf_addr_info.info1 = in ath12k_hal_set_link_desc_addr()
1974 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_dst_peek()
1976 if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp) in ath12k_hal_srng_dst_peek()
1977 return (srng->ring_base_vaddr + srng->u.dst_ring.tp); in ath12k_hal_srng_dst_peek()
1987 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_dst_get_next_entry()
1989 if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp) in ath12k_hal_srng_dst_get_next_entry()
1992 desc = srng->ring_base_vaddr + srng->u.dst_ring.tp; in ath12k_hal_srng_dst_get_next_entry()
1994 srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size) % in ath12k_hal_srng_dst_get_next_entry()
1995 srng->ring_size; in ath12k_hal_srng_dst_get_next_entry()
2005 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_dst_num_free()
2007 tp = srng->u.dst_ring.tp; in ath12k_hal_srng_dst_num_free()
2010 hp = *srng->u.dst_ring.hp_addr; in ath12k_hal_srng_dst_num_free()
2011 srng->u.dst_ring.cached_hp = hp; in ath12k_hal_srng_dst_num_free()
2013 hp = srng->u.dst_ring.cached_hp; in ath12k_hal_srng_dst_num_free()
2017 return (hp - tp) / srng->entry_size; in ath12k_hal_srng_dst_num_free()
2019 return (srng->ring_size - tp + hp) / srng->entry_size; in ath12k_hal_srng_dst_num_free()
2028 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_src_num_free()
2030 hp = srng->u.src_ring.hp; in ath12k_hal_srng_src_num_free()
2033 tp = *srng->u.src_ring.tp_addr; in ath12k_hal_srng_src_num_free()
2034 srng->u.src_ring.cached_tp = tp; in ath12k_hal_srng_src_num_free()
2036 tp = srng->u.src_ring.cached_tp; in ath12k_hal_srng_src_num_free()
2040 return ((tp - hp) / srng->entry_size) - 1; in ath12k_hal_srng_src_num_free()
2042 return ((srng->ring_size - hp + tp) / srng->entry_size) - 1; in ath12k_hal_srng_src_num_free()
2051 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_src_next_peek()
2053 next_hp = (srng->u.src_ring.hp + srng->entry_size) % srng->ring_size; in ath12k_hal_srng_src_next_peek()
2055 if (next_hp == srng->u.src_ring.cached_tp) in ath12k_hal_srng_src_next_peek()
2058 desc = srng->ring_base_vaddr + next_hp; in ath12k_hal_srng_src_next_peek()
2069 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_src_get_next_entry()
2077 next_hp = (srng->u.src_ring.hp + srng->entry_size) % srng->ring_size; in ath12k_hal_srng_src_get_next_entry()
2079 if (next_hp == srng->u.src_ring.cached_tp) in ath12k_hal_srng_src_get_next_entry()
2082 desc = srng->ring_base_vaddr + srng->u.src_ring.hp; in ath12k_hal_srng_src_get_next_entry()
2083 srng->u.src_ring.hp = next_hp; in ath12k_hal_srng_src_get_next_entry()
2091 srng->u.src_ring.reap_hp = next_hp; in ath12k_hal_srng_src_get_next_entry()
2098 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_src_peek()
2100 if (((srng->u.src_ring.hp + srng->entry_size) % srng->ring_size) == in ath12k_hal_srng_src_peek()
2101 srng->u.src_ring.cached_tp) in ath12k_hal_srng_src_peek()
2104 return srng->ring_base_vaddr + srng->u.src_ring.hp; in ath12k_hal_srng_src_peek()
2113 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_src_reap_next()
2115 next_reap_hp = (srng->u.src_ring.reap_hp + srng->entry_size) % in ath12k_hal_srng_src_reap_next()
2116 srng->ring_size; in ath12k_hal_srng_src_reap_next()
2118 if (next_reap_hp == srng->u.src_ring.cached_tp) in ath12k_hal_srng_src_reap_next()
2121 desc = srng->ring_base_vaddr + next_reap_hp; in ath12k_hal_srng_src_reap_next()
2122 srng->u.src_ring.reap_hp = next_reap_hp; in ath12k_hal_srng_src_reap_next()
2132 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_src_get_next_reaped()
2134 if (srng->u.src_ring.hp == srng->u.src_ring.reap_hp) in ath12k_hal_srng_src_get_next_reaped()
2137 desc = srng->ring_base_vaddr + srng->u.src_ring.hp; in ath12k_hal_srng_src_get_next_reaped()
2138 srng->u.src_ring.hp = (srng->u.src_ring.hp + srng->entry_size) % in ath12k_hal_srng_src_get_next_reaped()
2139 srng->ring_size; in ath12k_hal_srng_src_get_next_reaped()
2148 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_access_begin()
2150 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { in ath12k_hal_srng_access_begin()
2151 srng->u.src_ring.cached_tp = in ath12k_hal_srng_access_begin()
2152 *(volatile u32 *)srng->u.src_ring.tp_addr; in ath12k_hal_srng_access_begin()
2154 hp = READ_ONCE(*srng->u.dst_ring.hp_addr); in ath12k_hal_srng_access_begin()
2156 if (hp != srng->u.dst_ring.cached_hp) { in ath12k_hal_srng_access_begin()
2157 srng->u.dst_ring.cached_hp = hp; in ath12k_hal_srng_access_begin()
2171 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_access_end()
2173 if (srng->flags & HAL_SRNG_FLAGS_LMAC_RING) { in ath12k_hal_srng_access_end()
2174 /* For LMAC rings, ring pointer updates are done through FW and in ath12k_hal_srng_access_end()
2175 * hence written to a shared memory location that is read by FW in ath12k_hal_srng_access_end()
2177 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { in ath12k_hal_srng_access_end()
2178 srng->u.src_ring.last_tp = in ath12k_hal_srng_access_end()
2179 *(volatile u32 *)srng->u.src_ring.tp_addr; in ath12k_hal_srng_access_end()
2184 WRITE_ONCE(*srng->u.src_ring.hp_addr, srng->u.src_ring.hp); in ath12k_hal_srng_access_end()
2186 srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; in ath12k_hal_srng_access_end()
2191 WRITE_ONCE(*srng->u.dst_ring.tp_addr, srng->u.dst_ring.tp); in ath12k_hal_srng_access_end()
2194 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { in ath12k_hal_srng_access_end()
2195 srng->u.src_ring.last_tp = in ath12k_hal_srng_access_end()
2196 *(volatile u32 *)srng->u.src_ring.tp_addr; in ath12k_hal_srng_access_end()
2197 /* Assume implementation use an MMIO write accessor in ath12k_hal_srng_access_end()
2202 (unsigned long)srng->u.src_ring.hp_addr - in ath12k_hal_srng_access_end()
2203 (unsigned long)ab->mem, in ath12k_hal_srng_access_end()
2204 srng->u.src_ring.hp); in ath12k_hal_srng_access_end()
2206 srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; in ath12k_hal_srng_access_end()
2212 (unsigned long)srng->u.dst_ring.tp_addr - in ath12k_hal_srng_access_end()
2213 (unsigned long)ab->mem, in ath12k_hal_srng_access_end()
2214 srng->u.dst_ring.tp); in ath12k_hal_srng_access_end()
2218 srng->timestamp = jiffies; in ath12k_hal_srng_access_end()
2234 link_addr->info0 = cpu_to_le32(sbuf[i].paddr & HAL_ADDR_LSB_REG_MASK); in ath12k_hal_setup_link_idle_list()
2236 link_addr->info1 = in ath12k_hal_setup_link_idle_list()
2277 val = u32_encode_bits(sbuf[nsbufs - 1].paddr, BUFFER_ADDR_INFO0_ADDR); in ath12k_hal_setup_link_idle_list()
2283 val = u32_encode_bits(((u64)sbuf[nsbufs - 1].paddr >> HAL_ADDR_MSB_REG_SHIFT), in ath12k_hal_setup_link_idle_list()
2331 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_setup()
2332 struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; in ath12k_hal_srng_setup()
2343 srng = &hal->srng_list[ring_id]; in ath12k_hal_srng_setup()
2345 srng->ring_id = ring_id; in ath12k_hal_srng_setup()
2346 srng->ring_dir = srng_config->ring_dir; in ath12k_hal_srng_setup()
2347 srng->ring_base_paddr = params->ring_base_paddr; in ath12k_hal_srng_setup()
2348 srng->ring_base_vaddr = params->ring_base_vaddr; in ath12k_hal_srng_setup()
2349 srng->entry_size = srng_config->entry_size; in ath12k_hal_srng_setup()
2350 srng->num_entries = params->num_entries; in ath12k_hal_srng_setup()
2351 srng->ring_size = srng->entry_size * srng->num_entries; in ath12k_hal_srng_setup()
2352 srng->intr_batch_cntr_thres_entries = in ath12k_hal_srng_setup()
2353 params->intr_batch_cntr_thres_entries; in ath12k_hal_srng_setup()
2354 srng->intr_timer_thres_us = params->intr_timer_thres_us; in ath12k_hal_srng_setup()
2355 srng->flags = params->flags; in ath12k_hal_srng_setup()
2356 srng->msi_addr = params->msi_addr; in ath12k_hal_srng_setup()
2357 srng->msi2_addr = params->msi2_addr; in ath12k_hal_srng_setup()
2358 srng->msi_data = params->msi_data; in ath12k_hal_srng_setup()
2359 srng->msi2_data = params->msi2_data; in ath12k_hal_srng_setup()
2360 srng->initialized = 1; in ath12k_hal_srng_setup()
2361 spin_lock_init(&srng->lock); in ath12k_hal_srng_setup()
2362 lockdep_set_class(&srng->lock, &srng->lock_key); in ath12k_hal_srng_setup()
2365 srng->hwreg_base[i] = srng_config->reg_start[i] + in ath12k_hal_srng_setup()
2366 (ring_num * srng_config->reg_size[i]); in ath12k_hal_srng_setup()
2369 memset(srng->ring_base_vaddr, 0, in ath12k_hal_srng_setup()
2370 (srng->entry_size * srng->num_entries) << 2); in ath12k_hal_srng_setup()
2372 reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; in ath12k_hal_srng_setup()
2374 if (srng->ring_dir == HAL_SRNG_DIR_SRC) { in ath12k_hal_srng_setup()
2375 srng->u.src_ring.hp = 0; in ath12k_hal_srng_setup()
2376 srng->u.src_ring.cached_tp = 0; in ath12k_hal_srng_setup()
2377 srng->u.src_ring.reap_hp = srng->ring_size - srng->entry_size; in ath12k_hal_srng_setup()
2378 srng->u.src_ring.tp_addr = (void *)(hal->rdp.vaddr + ring_id); in ath12k_hal_srng_setup()
2379 srng->u.src_ring.low_threshold = params->low_threshold * in ath12k_hal_srng_setup()
2380 srng->entry_size; in ath12k_hal_srng_setup()
2381 if (srng_config->mac_type == ATH12K_HAL_SRNG_UMAC) { in ath12k_hal_srng_setup()
2382 if (!ab->hw_params->supports_shadow_regs) in ath12k_hal_srng_setup()
2383 srng->u.src_ring.hp_addr = in ath12k_hal_srng_setup()
2384 (u32 *)((unsigned long)ab->mem + reg_base); in ath12k_hal_srng_setup()
2390 (unsigned long)srng->u.src_ring.hp_addr - in ath12k_hal_srng_setup()
2391 (unsigned long)ab->mem); in ath12k_hal_srng_setup()
2393 idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START; in ath12k_hal_srng_setup()
2394 srng->u.src_ring.hp_addr = (void *)(hal->wrp.vaddr + in ath12k_hal_srng_setup()
2396 srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; in ath12k_hal_srng_setup()
2407 srng->u.dst_ring.loop_cnt = 1; in ath12k_hal_srng_setup()
2408 srng->u.dst_ring.tp = 0; in ath12k_hal_srng_setup()
2409 srng->u.dst_ring.cached_hp = 0; in ath12k_hal_srng_setup()
2410 srng->u.dst_ring.hp_addr = (void *)(hal->rdp.vaddr + ring_id); in ath12k_hal_srng_setup()
2411 if (srng_config->mac_type == ATH12K_HAL_SRNG_UMAC) { in ath12k_hal_srng_setup()
2412 if (!ab->hw_params->supports_shadow_regs) in ath12k_hal_srng_setup()
2413 srng->u.dst_ring.tp_addr = in ath12k_hal_srng_setup()
2414 (u32 *)((unsigned long)ab->mem + reg_base + in ath12k_hal_srng_setup()
2415 (HAL_REO1_RING_TP - HAL_REO1_RING_HP)); in ath12k_hal_srng_setup()
2420 reg_base + HAL_REO1_RING_TP - HAL_REO1_RING_HP, in ath12k_hal_srng_setup()
2421 (unsigned long)srng->u.dst_ring.tp_addr - in ath12k_hal_srng_setup()
2422 (unsigned long)ab->mem); in ath12k_hal_srng_setup()
2425 * through FW by writing to a shared memory location in ath12k_hal_srng_setup()
2427 idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START; in ath12k_hal_srng_setup()
2428 srng->u.dst_ring.tp_addr = (void *)(hal->wrp.vaddr + in ath12k_hal_srng_setup()
2430 srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; in ath12k_hal_srng_setup()
2434 if (srng_config->mac_type != ATH12K_HAL_SRNG_UMAC) in ath12k_hal_srng_setup()
2440 srng->u.dst_ring.max_buffer_length = params->max_buffer_len; in ath12k_hal_srng_setup()
2453 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_update_hp_tp_addr()
2455 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; in ath12k_hal_srng_update_hp_tp_addr()
2461 srng = &hal->srng_list[ring_id]; in ath12k_hal_srng_update_hp_tp_addr()
2463 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) in ath12k_hal_srng_update_hp_tp_addr()
2464 srng->u.dst_ring.tp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + in ath12k_hal_srng_update_hp_tp_addr()
2465 (unsigned long)ab->mem); in ath12k_hal_srng_update_hp_tp_addr()
2467 srng->u.src_ring.hp_addr = (u32 *)(HAL_SHADOW_REG(shadow_cfg_idx) + in ath12k_hal_srng_update_hp_tp_addr()
2468 (unsigned long)ab->mem); in ath12k_hal_srng_update_hp_tp_addr()
2475 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_update_shadow_config()
2476 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; in ath12k_hal_srng_update_shadow_config()
2477 int shadow_cfg_idx = hal->num_shadow_reg_configured; in ath12k_hal_srng_update_shadow_config()
2481 return -EINVAL; in ath12k_hal_srng_update_shadow_config()
2483 hal->num_shadow_reg_configured++; in ath12k_hal_srng_update_shadow_config()
2485 target_reg = srng_config->reg_start[HAL_HP_OFFSET_IN_REG_START]; in ath12k_hal_srng_update_shadow_config()
2486 target_reg += srng_config->reg_size[HAL_HP_OFFSET_IN_REG_START] * in ath12k_hal_srng_update_shadow_config()
2490 if (srng_config->ring_dir == HAL_SRNG_DIR_DST) in ath12k_hal_srng_update_shadow_config()
2493 hal->shadow_reg_addr[shadow_cfg_idx] = target_reg; in ath12k_hal_srng_update_shadow_config()
2511 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_shadow_config()
2514 /* update all the non-CE srngs. */ in ath12k_hal_srng_shadow_config()
2516 struct hal_srng_config *srng_config = &hal->srng_config[ring_type]; in ath12k_hal_srng_shadow_config()
2523 if (srng_config->mac_type == ATH12K_HAL_SRNG_DMAC || in ath12k_hal_srng_shadow_config()
2524 srng_config->mac_type == ATH12K_HAL_SRNG_PMAC) in ath12k_hal_srng_shadow_config()
2527 for (ring_num = 0; ring_num < srng_config->max_rings; ring_num++) in ath12k_hal_srng_shadow_config()
2533 u32 **cfg, u32 *len) in ath12k_hal_srng_get_shadow_config() argument
2535 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_get_shadow_config()
2537 *len = hal->num_shadow_reg_configured; in ath12k_hal_srng_get_shadow_config()
2538 *cfg = hal->shadow_reg_addr; in ath12k_hal_srng_get_shadow_config()
2544 lockdep_assert_held(&srng->lock); in ath12k_hal_srng_shadow_update_hp_tp()
2549 if (srng->ring_dir == HAL_SRNG_DIR_SRC && in ath12k_hal_srng_shadow_update_hp_tp()
2550 *srng->u.src_ring.tp_addr != srng->u.src_ring.hp) in ath12k_hal_srng_shadow_update_hp_tp()
2556 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_register_srng_lock_keys()
2560 lockdep_register_key(&hal->srng_list[ring_id].lock_key); in ath12k_hal_register_srng_lock_keys()
2565 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_unregister_srng_lock_keys()
2569 lockdep_unregister_key(&hal->srng_list[ring_id].lock_key); in ath12k_hal_unregister_srng_lock_keys()
2574 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_init()
2579 ret = ab->hw_params->hal_ops->create_srng_config(ab); in ath12k_hal_srng_init()
2604 struct ath12k_hal *hal = &ab->hal; in ath12k_hal_srng_deinit()
2609 kfree(hal->srng_config); in ath12k_hal_srng_deinit()
2610 hal->srng_config = NULL; in ath12k_hal_srng_deinit()
2621 for (i = 0; i < ab->hw_params->ce_count; i++) { in ath12k_hal_dump_srng_stats()
2622 ce_pipe = &ab->ce.ce_pipe[i]; in ath12k_hal_dump_srng_stats()
2628 i, ce_pipe->pipe_num, in ath12k_hal_dump_srng_stats()
2629 jiffies_to_msecs(jiffies - ce_pipe->timestamp)); in ath12k_hal_dump_srng_stats()
2634 irq_grp = &ab->ext_irq_grp[i]; in ath12k_hal_dump_srng_stats()
2636 irq_grp->grp_id, in ath12k_hal_dump_srng_stats()
2637 jiffies_to_msecs(jiffies - irq_grp->timestamp)); in ath12k_hal_dump_srng_stats()
2641 srng = &ab->hal.srng_list[i]; in ath12k_hal_dump_srng_stats()
2643 if (!srng->initialized) in ath12k_hal_dump_srng_stats()
2646 if (srng->ring_dir == HAL_SRNG_DIR_SRC) in ath12k_hal_dump_srng_stats()
2649 srng->ring_id, srng->u.src_ring.hp, in ath12k_hal_dump_srng_stats()
2650 srng->u.src_ring.reap_hp, in ath12k_hal_dump_srng_stats()
2651 *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp, in ath12k_hal_dump_srng_stats()
2652 srng->u.src_ring.last_tp, in ath12k_hal_dump_srng_stats()
2653 jiffies_to_msecs(jiffies - srng->timestamp)); in ath12k_hal_dump_srng_stats()
2654 else if (srng->ring_dir == HAL_SRNG_DIR_DST) in ath12k_hal_dump_srng_stats()
2657 srng->ring_id, srng->u.dst_ring.tp, in ath12k_hal_dump_srng_stats()
2658 *srng->u.dst_ring.hp_addr, in ath12k_hal_dump_srng_stats()
2659 srng->u.dst_ring.cached_hp, in ath12k_hal_dump_srng_stats()
2660 srng->u.dst_ring.last_hp, in ath12k_hal_dump_srng_stats()
2661 jiffies_to_msecs(jiffies - srng->timestamp)); in ath12k_hal_dump_srng_stats()