Lines Matching defs:ab
22 static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab,
30 struct ath12k_base *ab = ar->ab;
35 spin_lock_bh(&ab->base_lock);
36 peer = ath12k_peer_find(ab, vdev_id, addr);
38 ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n",
40 spin_unlock_bh(&ab->base_lock);
45 spin_unlock_bh(&ab->base_lock);
52 spin_unlock_bh(&ab->base_lock);
57 struct ath12k_base *ab = ar->ab;
69 ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n",
78 ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n",
86 ath12k_warn(ab, "failed to setup rx defrag context\n");
95 spin_lock_bh(&ab->base_lock);
97 peer = ath12k_peer_find(ab, vdev_id, addr);
99 ath12k_warn(ab, "failed to find the peer to del rx tid\n");
100 spin_unlock_bh(&ab->base_lock);
107 spin_unlock_bh(&ab->base_lock);
112 void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring)
117 dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned,
137 static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab,
147 grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0];
150 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
151 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
158 grp_mask = &ab->hw_params->ring_mask->tx[0];
162 grp_mask = &ab->hw_params->ring_mask->rx_err[0];
165 grp_mask = &ab->hw_params->ring_mask->rx[0];
168 grp_mask = &ab->hw_params->ring_mask->reo_status[0];
171 grp_mask = &ab->hw_params->ring_mask->rx_mon_status[0];
174 grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0];
177 grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0];
180 grp_mask = &ab->hw_params->ring_mask->host2rxdma[0];
200 static void ath12k_dp_srng_msi_setup(struct ath12k_base *ab,
208 ret = ath12k_hif_get_user_msi_vector(ab, "DP",
214 msi_group_number = ath12k_dp_srng_calculate_msi_group(ab, type,
217 ath12k_dbg(ab, ATH12K_DBG_PCI,
226 ath12k_dbg(ab, ATH12K_DBG_PCI,
231 ath12k_hif_get_msi_address(ab, &addr_lo, &addr_hi);
240 int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring,
245 int entry_sz = ath12k_hal_srng_get_entrysize(ab, type);
246 int max_entries = ath12k_hal_srng_get_max_entries(ab, type);
256 ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size,
269 ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id);
297 if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) {
325 ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type);
329 ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms);
331 ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n",
342 u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab,
352 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags))
385 static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab,
395 bank_config = ath12k_dp_tx_get_vdev_bank_config(ab, arvif);
414 ath12k_err(ab, "unable to find TX bank!");
427 ath12k_hal_tx_configure_bank_register(ab, bank_config, bank_id);
429 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt tcl bank_id %d input 0x%x match 0x%x num_users %u",
443 static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab)
445 struct ath12k_dp *dp = &ab->dp;
451 static int ath12k_dp_init_bank_profiles(struct ath12k_base *ab)
453 struct ath12k_dp *dp = &ab->dp;
454 u32 num_tcl_banks = ab->hw_params->num_tcl_banks;
474 static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab)
476 struct ath12k_dp *dp = &ab->dp;
479 ath12k_dp_srng_cleanup(ab, &dp->reo_status_ring);
480 ath12k_dp_srng_cleanup(ab, &dp->reo_cmd_ring);
481 ath12k_dp_srng_cleanup(ab, &dp->reo_except_ring);
482 ath12k_dp_srng_cleanup(ab, &dp->rx_rel_ring);
483 ath12k_dp_srng_cleanup(ab, &dp->reo_reinject_ring);
484 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
485 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring);
486 ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring);
488 ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring);
491 static int ath12k_dp_srng_common_setup(struct ath12k_base *ab)
493 struct ath12k_dp *dp = &ab->dp;
499 ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring,
503 ath12k_warn(ab, "failed to set up wbm2sw_release ring :%d\n",
508 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
509 map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map;
512 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring,
516 ath12k_warn(ab, "failed to set up tcl_data ring (%d) :%d\n",
521 ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring,
525 ath12k_warn(ab, "failed to set up tcl_comp ring (%d) :%d\n",
531 ret = ath12k_dp_srng_setup(ab, &dp->reo_reinject_ring, HAL_REO_REINJECT,
534 ath12k_warn(ab, "failed to set up reo_reinject ring :%d\n",
539 ret = ath12k_dp_srng_setup(ab, &dp->rx_rel_ring, HAL_WBM2SW_RELEASE,
543 ath12k_warn(ab, "failed to set up rx_rel ring :%d\n", ret);
547 ret = ath12k_dp_srng_setup(ab, &dp->reo_except_ring, HAL_REO_EXCEPTION,
550 ath12k_warn(ab, "failed to set up reo_exception ring :%d\n",
555 ret = ath12k_dp_srng_setup(ab, &dp->reo_cmd_ring, HAL_REO_CMD,
558 ath12k_warn(ab, "failed to set up reo_cmd ring :%d\n", ret);
562 srng = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
563 ath12k_hal_reo_init_cmd_ring(ab, srng);
565 ret = ath12k_dp_srng_setup(ab, &dp->reo_status_ring, HAL_REO_STATUS,
568 ath12k_warn(ab, "failed to set up reo_status ring :%d\n", ret);
587 ath12k_hal_reo_hw_setup(ab, ring_hash_map);
592 ath12k_dp_srng_common_cleanup(ab);
597 static void ath12k_dp_scatter_idle_link_desc_cleanup(struct ath12k_base *ab)
599 struct ath12k_dp *dp = &ab->dp;
607 dma_free_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX,
613 static int ath12k_dp_scatter_idle_link_desc_setup(struct ath12k_base *ab,
619 struct ath12k_dp *dp = &ab->dp;
634 ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK);
641 slist[i].vaddr = dma_alloc_coherent(ab->dev,
680 ath12k_hal_setup_link_idle_list(ab, slist, num_scatter_buf,
686 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
692 ath12k_dp_link_desc_bank_free(struct ath12k_base *ab,
699 dma_free_coherent(ab->dev,
708 static int ath12k_dp_link_desc_bank_alloc(struct ath12k_base *ab,
713 struct ath12k_dp *dp = &ab->dp;
723 dma_alloc_coherent(ab->dev, desc_sz,
742 ath12k_dp_link_desc_bank_free(ab, dp->link_desc_banks);
747 void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab,
751 ath12k_dp_link_desc_bank_free(ab, desc_bank);
754 ath12k_dp_srng_cleanup(ab, ring);
755 ath12k_dp_scatter_idle_link_desc_cleanup(ab);
759 static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc)
761 struct ath12k_dp *dp = &ab->dp;
786 ret = ath12k_dp_srng_setup(ab, &dp->wbm_idle_ring,
789 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
795 int ath12k_dp_link_desc_setup(struct ath12k_base *ab,
807 enum hal_rx_buf_return_buf_manager rbm = ab->dp.idle_link_rbm;
830 ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks,
836 entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type);
842 ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz,
847 ath12k_warn(ab, "failed to setup scatting idle list descriptor :%d\n",
857 ath12k_hal_srng_access_begin(ab, srng);
866 (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) {
874 ath12k_hal_srng_access_end(ab, srng);
881 ath12k_dp_link_desc_bank_free(ab, link_desc_banks);
886 int ath12k_dp_service_srng(struct ath12k_base *ab,
898 if (ab->hw_params->ring_mask->tx[grp_id]) {
899 i = fls(ab->hw_params->ring_mask->tx[grp_id]) - 1;
900 ath12k_dp_tx_completion_handler(ab, i);
903 if (ab->hw_params->ring_mask->rx_err[grp_id]) {
904 work_done = ath12k_dp_rx_process_err(ab, napi, budget);
911 if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) {
912 work_done = ath12k_dp_rx_process_wbm_err(ab,
922 if (ab->hw_params->ring_mask->rx[grp_id]) {
923 i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1;
924 work_done = ath12k_dp_rx_process(ab, i, napi,
932 if (ab->hw_params->ring_mask->rx_mon_status[grp_id]) {
933 ring_mask = ab->hw_params->ring_mask->rx_mon_status[grp_id];
934 for (i = 0; i < ab->num_radios; i++) {
935 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
936 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
940 ath12k_dp_mon_process_ring(ab, id, napi, budget,
951 if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) {
953 ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id];
954 for (i = 0; i < ab->num_radios; i++) {
955 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
956 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
960 ath12k_dp_mon_process_ring(ab, id, napi, budget,
972 if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) {
974 ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id];
975 for (i = 0; i < ab->num_radios; i++) {
976 for (j = 0; j < ab->hw_params->num_rxdma_per_pdev; j++) {
977 int id = i * ab->hw_params->num_rxdma_per_pdev + j;
981 ath12k_dp_mon_process_ring(ab, id, napi, budget,
993 if (ab->hw_params->ring_mask->reo_status[grp_id])
994 ath12k_dp_rx_process_reo_status(ab);
996 if (ab->hw_params->ring_mask->host2rxdma[grp_id]) {
997 struct ath12k_dp *dp = &ab->dp;
1001 ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0);
1010 void ath12k_dp_pdev_free(struct ath12k_base *ab)
1014 for (i = 0; i < ab->num_radios; i++)
1015 ath12k_dp_rx_pdev_free(ab, i);
1028 bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab)
1030 if (test_bit(WMI_TLV_SERVICE_WMSK_COMPACTION_RX_TLVS, ab->wmi_ab.svc_map) &&
1031 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start &&
1032 ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end &&
1033 ab->hw_params->hal_ops->get_hal_rx_compact_ops) {
1039 void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab)
1041 if (ath12k_dp_wmask_compaction_rx_tlv_supported(ab)) {
1045 ab->hal_rx_ops = ab->hw_params->hal_ops->get_hal_rx_compact_ops();
1047 ab->hal.hal_desc_sz =
1048 ab->hal_rx_ops->rx_desc_get_desc_size();
1051 int ath12k_dp_pdev_alloc(struct ath12k_base *ab)
1057 ret = ath12k_dp_rx_htt_setup(ab);
1062 for (i = 0; i < ab->num_radios; i++) {
1063 ar = ab->pdevs[i].ar;
1064 ret = ath12k_dp_rx_pdev_alloc(ab, i);
1066 ath12k_warn(ab, "failed to allocate pdev rx for pdev_id :%d\n",
1072 ath12k_warn(ab, "failed to initialize mon pdev %d\n", i);
1079 ath12k_dp_pdev_free(ab);
1096 status = ath12k_htc_connect_service(&dp->ab->htc, &conn_req,
1127 struct ath12k_base *ab = ar->ab;
1140 arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp);
1144 ath12k_err(ar->ab, "Failed to initialize DP TX Banks");
1149 static void ath12k_dp_cc_cleanup(struct ath12k_base *ab)
1153 struct ath12k_dp *dp = &ab->dp;
1179 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr,
1209 dma_unmap_single(ab->dev,
1219 if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) {
1226 dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr,
1254 dma_free_coherent(ab->dev, ATH12K_PAGE_SIZE,
1263 static void ath12k_dp_reoq_lut_cleanup(struct ath12k_base *ab)
1265 struct ath12k_dp *dp = &ab->dp;
1267 if (!ab->hw_params->reoq_lut_support)
1271 ath12k_hif_write32(ab,
1273 HAL_REO1_QDESC_LUT_BASE0(ab), 0);
1274 dma_free_coherent(ab->dev, dp->reoq_lut.size,
1281 ath12k_hif_write32(ab,
1283 HAL_REO1_QDESC_LUT_BASE1(ab), 0);
1284 dma_free_coherent(ab->dev, dp->ml_reoq_lut.size,
1291 void ath12k_dp_free(struct ath12k_base *ab)
1293 struct ath12k_dp *dp = &ab->dp;
1296 if (!dp->ab)
1299 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,
1302 ath12k_dp_cc_cleanup(ab);
1303 ath12k_dp_reoq_lut_cleanup(ab);
1304 ath12k_dp_deinit_bank_profiles(ab);
1305 ath12k_dp_srng_common_cleanup(ab);
1307 ath12k_dp_rx_reo_cmd_list_cleanup(ab);
1309 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1314 ath12k_dp_rx_free(ab);
1316 dp->ab = NULL;
1319 void ath12k_dp_cc_config(struct ath12k_base *ab)
1321 u32 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1329 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base);
1341 ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG1(ab), val);
1344 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG0, cmem_base);
1354 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG1, val);
1357 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2);
1362 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CFG2, val);
1365 val = ath12k_hif_read32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG);
1367 ab->hw_params->hal_params->wbm2sw_cc_enable;
1369 ath12k_hif_write32(ab, wbm_base + HAL_WBM_SW_COOKIE_CONVERT_CFG, val);
1377 static inline void *ath12k_dp_cc_get_desc_addr_ptr(struct ath12k_base *ab,
1380 struct ath12k_dp *dp = &ab->dp;
1385 struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab,
1388 struct ath12k_dp *dp = &ab->dp;
1404 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1409 struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab,
1427 desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx);
1432 static int ath12k_dp_cc_desc_init(struct ath12k_base *ab)
1434 struct ath12k_dp *dp = &ab->dp;
1459 rx_descs[j].device_id = ab->device_id;
1463 rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1495 ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j);
1504 static int ath12k_dp_cmem_init(struct ath12k_base *ab,
1511 cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start;
1524 ath12k_err(ab, "invalid descriptor type %d in cmem init\n", type);
1530 ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i),
1536 void ath12k_dp_partner_cc_init(struct ath12k_base *ab)
1538 struct ath12k_hw_group *ag = ab->ag;
1542 if (ag->ab[i] == ab)
1545 ath12k_dp_cmem_init(ab, &ag->ab[i]->dp, ATH12K_DP_RX_DESC);
1549 static int ath12k_dp_cc_init(struct ath12k_base *ab)
1551 struct ath12k_dp *dp = &ab->dp;
1571 ath12k_warn(ab, "SPT page allocation failure");
1575 dp->rx_ppt_base = ab->device_id * ATH12K_NUM_RX_SPT_PAGES;
1578 dp->spt_info[i].vaddr = dma_alloc_coherent(ab->dev,
1589 ath12k_warn(ab, "SPT allocated memory is not 4K aligned");
1595 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_TX_DESC);
1597 ath12k_warn(ab, "HW CC Tx cmem init failed %d", ret);
1601 ret = ath12k_dp_cmem_init(ab, dp, ATH12K_DP_RX_DESC);
1603 ath12k_warn(ab, "HW CC Rx cmem init failed %d", ret);
1607 ret = ath12k_dp_cc_desc_init(ab);
1609 ath12k_warn(ab, "HW CC desc init failed %d", ret);
1615 ath12k_dp_cc_cleanup(ab);
1619 static int ath12k_dp_alloc_reoq_lut(struct ath12k_base *ab,
1623 lut->vaddr_unaligned = dma_alloc_coherent(ab->dev, lut->size,
1635 static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
1637 struct ath12k_dp *dp = &ab->dp;
1641 if (!ab->hw_params->reoq_lut_support)
1644 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->reoq_lut);
1646 ath12k_warn(ab, "failed to allocate memory for reoq table");
1650 ret = ath12k_dp_alloc_reoq_lut(ab, &dp->ml_reoq_lut);
1652 ath12k_warn(ab, "failed to allocate memory for ML reoq table");
1653 dma_free_coherent(ab->dev, dp->reoq_lut.size,
1666 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab),
1669 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE1(ab),
1672 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(ab));
1674 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR(ab),
1677 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(ab),
1684 ath12k_dp_get_idle_link_rbm(struct ath12k_base *ab)
1686 switch (ab->device_id) {
1694 ath12k_warn(ab, "invalid %d device id, so choose default rbm\n",
1695 ab->device_id);
1701 int ath12k_dp_alloc(struct ath12k_base *ab)
1703 struct ath12k_dp *dp = &ab->dp;
1710 dp->ab = ab;
1717 dp->idle_link_rbm = ath12k_dp_get_idle_link_rbm(ab);
1719 ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc);
1721 ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret);
1725 srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id];
1727 ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks,
1730 ath12k_warn(ab, "failed to setup link desc: %d\n", ret);
1734 ret = ath12k_dp_cc_init(ab);
1737 ath12k_warn(ab, "failed to setup cookie converter %d\n", ret);
1740 ret = ath12k_dp_init_bank_profiles(ab);
1742 ath12k_warn(ab, "failed to setup bank profiles %d\n", ret);
1746 ret = ath12k_dp_srng_common_setup(ab);
1752 ret = ath12k_dp_reoq_lut_setup(ab);
1754 ath12k_warn(ab, "failed to setup reoq table %d\n", ret);
1758 for (i = 0; i < ab->hw_params->max_tx_ring; i++) {
1774 ath12k_hal_tx_set_dscp_tid_map(ab, i);
1776 ret = ath12k_dp_rx_alloc(ab);
1785 ath12k_dp_rx_free(ab);
1788 ath12k_dp_reoq_lut_cleanup(ab);
1791 ath12k_dp_srng_common_cleanup(ab);
1794 ath12k_dp_deinit_bank_profiles(ab);
1797 ath12k_dp_cc_cleanup(ab);
1800 ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks,