Lines Matching full:u32
43 u32 cmd_id;
47 u32 header;
2233 u32 pdev_id;
2234 u32 start_freq;
2235 u32 end_freq;
2239 u32 numss_m1;
2240 u32 ru_bit_mask;
2241 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS];
2245 u32 default_conc_scan_config_bits;
2246 u32 default_fw_config_bits;
2248 u32 he_cap_info;
2249 u32 mpdu_density;
2250 u32 max_bssid_rx_filters;
2251 u32 num_hw_modes;
2252 u32 num_phy;
2256 u32 hw_mode_id;
2257 u32 phy_id_map;
2258 u32 hw_mode_config_type;
2270 u32 phy_id;
2271 u32 eeprom_reg_domain;
2272 u32 eeprom_reg_domain_ext;
2273 u32 regcap1;
2274 u32 regcap2;
2275 u32 wireless_modes;
2276 u32 low_2ghz_chan;
2277 u32 high_2ghz_chan;
2278 u32 low_5ghz_chan;
2279 u32 high_5ghz_chan;
2285 u32 tlv_header;
2286 u32 req_id;
2287 u32 ptr;
2288 u32 size;
2294 u32 len;
2295 u32 req_id;
2299 u32 tlv_header;
2303 u32 hw_mode_id;
2304 u32 num_band_to_mac;
2309 u32 tlv_header;
2310 u32 pdev_id;
2311 u32 start_freq;
2312 u32 end_freq;
2316 u32 tlv_header;
2317 u32 pdev_id;
2318 u32 hw_mode_index;
2319 u32 num_band_to_mac;
2323 u32 numss_m1; /** NSS - 1*/
2325 u32 ru_count;
2326 u32 ru_mask;
2328 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS];
2334 u32 abi_version_0;
2335 u32 abi_version_1;
2336 u32 abi_version_ns_0;
2337 u32 abi_version_ns_1;
2338 u32 abi_version_ns_2;
2339 u32 abi_version_ns_3;
2343 u32 tlv_header;
2345 u32 num_host_mem_chunks;
2355 u32 tlv_header;
2356 u32 num_vdevs;
2357 u32 num_peers;
2358 u32 num_offload_peers;
2359 u32 num_offload_reorder_buffs;
2360 u32 num_peer_keys;
2361 u32 num_tids;
2362 u32 ast_skid_limit;
2363 u32 tx_chain_mask;
2364 u32 rx_chain_mask;
2365 u32 rx_timeout_pri[4];
2366 u32 rx_decap_mode;
2367 u32 scan_max_pending_req;
2368 u32 bmiss_offload_max_vdev;
2369 u32 roam_offload_max_vdev;
2370 u32 roam_offload_max_ap_profiles;
2371 u32 num_mcast_groups;
2372 u32 num_mcast_table_elems;
2373 u32 mcast2ucast_mode;
2374 u32 tx_dbg_log_size;
2375 u32 num_wds_entries;
2376 u32 dma_burst_size;
2377 u32 mac_aggr_delim;
2378 u32 rx_skip_defrag_timeout_dup_detection_check;
2379 u32 vow_config;
2380 u32 gtk_offload_max_vdev;
2381 u32 num_msdu_desc;
2382 u32 max_frag_entries;
2383 u32 num_tdls_vdevs;
2384 u32 num_tdls_conn_table_entries;
2385 u32 beacon_tx_offload_max_vdev;
2386 u32 num_multicast_filter_entries;
2387 u32 num_wow_filters;
2388 u32 num_keep_alive_pattern;
2389 u32 keep_alive_pattern_size;
2390 u32 max_tdls_concurrent_sleep_sta;
2391 u32 max_tdls_concurrent_buffer_sta;
2392 u32 wmi_send_separate;
2393 u32 num_ocb_vdevs;
2394 u32 num_ocb_channels;
2395 u32 num_ocb_schedules;
2396 u32 flag1;
2397 u32 smart_ant_cap;
2398 u32 bk_minfree;
2399 u32 be_minfree;
2400 u32 vi_minfree;
2401 u32 vo_minfree;
2402 u32 alloc_frag_desc_for_data_pkt;
2403 u32 num_ns_ext_tuples_cfg;
2404 u32 bpf_instruction_size;
2405 u32 max_bssid_rx_filters;
2406 u32 use_pdev_id;
2407 u32 max_num_dbs_scan_duty_cycle;
2408 u32 max_num_group_keys;
2409 u32 peer_map_unmap_v2_support;
2410 u32 sched_params;
2411 u32 twt_ap_pdev_count;
2412 u32 twt_ap_sta_count;
2413 u32 max_nlo_ssids;
2414 u32 num_pkt_filters;
2415 u32 num_max_sta_vdevs;
2416 u32 max_bssid_indicator;
2417 u32 ul_resp_config;
2418 u32 msdu_flow_override_config0;
2419 u32 msdu_flow_override_config1;
2420 u32 flags2;
2421 u32 host_service_flags;
2422 u32 max_rnr_neighbours;
2423 u32 ema_max_vap_cnt;
2424 u32 ema_max_profile_period;
2428 u32 fw_build_vers;
2430 u32 phy_capability;
2431 u32 max_frag_entry;
2432 u32 num_rf_chains;
2433 u32 ht_cap_info;
2434 u32 vht_cap_info;
2435 u32 vht_supp_mcs;
2436 u32 hw_min_tx_power;
2437 u32 hw_max_tx_power;
2438 u32 sys_cap_info;
2439 u32 min_pkt_size_enable;
2440 u32 max_bcn_ie_size;
2441 u32 num_mem_reqs;
2442 u32 max_num_scan_channels;
2443 u32 hw_bd_id;
2444 u32 hw_bd_info[HW_BD_INFO_SIZE];
2445 u32 max_supported_macs;
2446 u32 wmi_fw_sub_feat_caps;
2447 u32 num_dbs_hw_modes;
2454 u32 txrx_chainmask;
2455 u32 default_dbs_hw_mode_index;
2456 u32 num_msdu_desc;
2459 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32))
2461 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */
2462 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32))
2467 u32 default_conc_scan_config_bits;
2468 u32 default_fw_config_bits;
2470 u32 he_cap_info;
2471 u32 mpdu_density;
2472 u32 max_bssid_rx_filters;
2473 u32 fw_build_vers_ext;
2474 u32 max_nlo_ssids;
2475 u32 max_bssid_indicator;
2476 u32 he_cap_info_ext;
2480 u32 num_hw_modes;
2481 u32 num_chainmask_tables;
2485 u32 tlv_header;
2486 u32 hw_mode_id;
2487 u32 phy_id_map;
2488 u32 hw_mode_config_type;
2500 u32 hw_mode_id;
2501 u32 pdev_id;
2502 u32 phy_id;
2503 u32 supported_flags;
2504 u32 supported_bands;
2505 u32 ampdu_density;
2506 u32 max_bw_supported_2g;
2507 u32 ht_cap_info_2g;
2508 u32 vht_cap_info_2g;
2509 u32 vht_supp_mcs_2g;
2510 u32 he_cap_info_2g;
2511 u32 he_supp_mcs_2g;
2512 u32 tx_chain_mask_2g;
2513 u32 rx_chain_mask_2g;
2514 u32 max_bw_supported_5g;
2515 u32 ht_cap_info_5g;
2516 u32 vht_cap_info_5g;
2517 u32 vht_supp_mcs_5g;
2518 u32 he_cap_info_5g;
2519 u32 he_supp_mcs_5g;
2520 u32 tx_chain_mask_5g;
2521 u32 rx_chain_mask_5g;
2522 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE];
2523 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE];
2526 u32 chainmask_table_id;
2527 u32 lmac_id;
2528 u32 he_cap_info_2g_ext;
2529 u32 he_cap_info_5g_ext;
2530 u32 he_cap_info_internal;
2531 u32 wireless_modes;
2532 u32 low_2ghz_chan_freq;
2533 u32 high_2ghz_chan_freq;
2534 u32 low_5ghz_chan_freq;
2535 u32 high_5ghz_chan_freq;
2536 u32 nss_ratio;
2540 u32 tlv_header;
2541 u32 phy_id;
2542 u32 eeprom_reg_domain;
2543 u32 eeprom_reg_domain_ext;
2544 u32 regcap1;
2545 u32 regcap2;
2546 u32 wireless_modes;
2547 u32 low_2ghz_chan;
2548 u32 high_2ghz_chan;
2549 u32 low_5ghz_chan;
2550 u32 high_5ghz_chan;
2554 u32 num_phy;
2562 u32 word0;
2563 u32 word1;
2569 u32 tlv_header;
2570 u32 pdev_id;
2571 u32 module_id;
2572 u32 min_elem;
2573 u32 min_buf_sz;
2574 u32 min_buf_align;
2580 u32 status;
2581 u32 num_dscp_table;
2582 u32 num_extra_mac_addr;
2583 u32 num_total_peers;
2584 u32 num_extra_peers;
2589 u32 max_ast_index;
2590 u32 pktlog_defs_checksum;
2594 u32 wmi_service_segment_offset;
2595 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32];
2601 u32 rx_decap_mode;
2607 u32 type;
2608 u32 subtype;
2613 u32 pdev_id;
2614 u32 mbssid_flags;
2615 u32 mbssid_tx_vdev_id;
2619 u32 tlv_header;
2620 u32 vdev_id;
2621 u32 vdev_type;
2622 u32 vdev_subtype;
2624 u32 num_cfg_txrx_streams;
2625 u32 pdev_id;
2626 u32 mbssid_flags;
2627 u32 mbssid_tx_vdev_id;
2631 u32 tlv_header;
2632 u32 band;
2633 u32 supported_tx_streams;
2634 u32 supported_rx_streams;
2638 u32 tlv_header;
2639 u32 vdev_id;
2643 u32 tlv_header;
2644 u32 vdev_id;
2645 u32 vdev_assoc_id;
2648 u32 nontx_profile_idx;
2649 u32 nontx_profile_cnt;
2653 u32 tlv_header;
2654 u32 vdev_id;
2658 u32 tlv_header;
2659 u32 vdev_id;
2668 u32 ssid_len;
2669 u32 ssid[8];
2675 u32 tlv_header;
2676 u32 vdev_id;
2677 u32 requestor_id;
2678 u32 beacon_interval;
2679 u32 dtim_period;
2680 u32 flags;
2682 u32 bcn_tx_rate;
2683 u32 bcn_txpower;
2684 u32 num_noa_descriptors;
2685 u32 disable_hw_ack;
2686 u32 preferred_tx_streams;
2687 u32 preferred_rx_streams;
2688 u32 he_ops;
2689 u32 cac_duration_ms;
2690 u32 regdomain;
2691 u32 min_data_rate;
2692 u32 mbssid_flags;
2693 u32 mbssid_tx_vdev_id;
2704 u32 type_count;
2705 u32 duration;
2706 u32 interval;
2707 u32 start_time;
2713 u32 mhz;
2714 u32 half_rate:1,
2724 u32 phy_mode;
2725 u32 cfreq1;
2726 u32 cfreq2;
2827 u32 freq;
2828 u32 band_center_freq1;
2829 u32 band_center_freq2;
2838 u32 min_power;
2839 u32 max_power;
2840 u32 max_reg_power;
2841 u32 max_antenna_gain;
2846 u32 vdev_id;
2848 u32 bcn_intval;
2849 u32 dtim_period;
2851 u32 ssid_len;
2852 u32 bcn_tx_rate;
2853 u32 bcn_tx_power;
2857 u32 he_ops;
2858 u32 cac_duration_ms;
2859 u32 regdomain;
2860 u32 pref_rx_streams;
2861 u32 pref_tx_streams;
2862 u32 num_noa_descriptors;
2863 u32 min_data_rate;
2864 u32 mbssid_flags;
2865 u32 mbssid_tx_vdev_id;
2870 u32 peer_type;
2871 u32 vdev_id;
2879 u32 peer_tid_bitmap;
2887 u32 ctl_2g;
2888 u32 ctl_5g;
2890 u32 pdev_id;
2896 u32 peer_tid_bitmap;
2985 u32 param_id;
2986 u32 param_value;
2996 u32 tlv_header;
2997 u32 vdev_id;
2999 u32 peer_type;
3003 u32 tlv_header;
3004 u32 vdev_id;
3009 u32 tlv_header;
3010 u32 vdev_id;
3012 u32 tid;
3013 u32 queue_ptr_lo;
3014 u32 queue_ptr_hi;
3015 u32 queue_no;
3016 u32 ba_window_size_valid;
3017 u32 ba_window_size;
3021 u32 tlv_header;
3022 u32 vdev_id;
3024 u32 tid_mask;
3028 u32 gpio_num;
3029 u32 input;
3030 u32 pull_type;
3031 u32 intr_mode;
3055 u32 tlv_header;
3056 u32 gpio_num;
3057 u32 input;
3058 u32 pull_type;
3059 u32 intr_mode;
3063 u32 gpio_num;
3064 u32 set;
3068 u32 tlv_header;
3069 u32 gpio_num;
3070 u32 set;
3074 u32 arg;
3075 u32 value;
3079 u32 tlv_header;
3080 u32 param_id;
3081 u32 param_value;
3085 u32 tlv_header;
3086 u32 pdev_id;
3087 u32 param_id;
3088 u32 param_value;
3092 u32 tlv_header;
3093 u32 vdev_id;
3094 u32 sta_ps_mode;
3098 u32 tlv_header;
3099 u32 pdev_id;
3100 u32 suspend_opt;
3104 u32 tlv_header;
3105 u32 pdev_id;
3109 u32 tlv_header;
3111 u32 req_type;
3112 u32 pdev_id;
3116 u32 tlv_header;
3117 u32 vdev_id;
3119 u32 param;
3120 u32 value;
3124 u32 tlv_header;
3125 u32 vdev_id;
3126 u32 param;
3127 u32 value;
3131 u32 tlv_header;
3132 u32 pdev_id;
3133 u32 reg_domain;
3134 u32 reg_domain_2g;
3135 u32 reg_domain_5g;
3136 u32 conformance_test_limit_2g;
3137 u32 conformance_test_limit_5g;
3138 u32 dfs_domain;
3142 u32 tlv_header;
3143 u32 vdev_id;
3145 u32 param_id;
3146 u32 param_value;
3150 u32 tlv_header;
3151 u32 vdev_id;
3153 u32 peer_tid_bitmap;
3157 u32 tlv_header;
3158 u32 pdev_id;
3162 u32 tlv_header;
3163 u32 vdev_id;
3164 u32 bcn_ctrl_op;
3178 u32 len;
3188 u32 tlv_header;
3191 u32 chan_cfreq;
3196 u32 tx_power;
3200 u32 tlv_header;
3201 u32 vdev_id;
3204 u32 psd_power;
3207 u32 eirp_power;
3210 u32 power_type_6ghz;
3272 u32 tlv_header;
3273 u32 scan_id;
3274 u32 scan_req_id;
3275 u32 vdev_id;
3276 u32 scan_priority;
3277 u32 notify_scan_events;
3278 u32 dwell_time_active;
3279 u32 dwell_time_passive;
3280 u32 min_rest_time;
3281 u32 max_rest_time;
3282 u32 repeat_probe_time;
3283 u32 probe_spacing_time;
3284 u32 idle_time;
3285 u32 max_scan_time;
3286 u32 probe_delay;
3287 u32 scan_ctrl_flags;
3288 u32 burst_duration;
3289 u32 num_chan;
3290 u32 num_bssid;
3291 u32 num_ssids;
3292 u32 ie_len;
3293 u32 n_probes;
3296 u32 ie_bitmap[WMI_IE_BITMAP_SIZE];
3297 u32 num_vendor_oui;
3298 u32 scan_ctrl_flags_ext;
3299 u32 dwell_time_active_2g;
3300 u32 dwell_time_active_6g;
3301 u32 dwell_time_passive_6g;
3302 u32 scan_start_offset;
3347 u32 freq_flags;
3348 u32 short_ssid;
3352 u32 freq_flags;
3357 u32 scan_id;
3358 u32 scan_req_id;
3359 u32 vdev_id;
3360 u32 pdev_id;
3362 u32 scan_ev_started:1,
3375 u32 scan_ctrl_flags_ext;
3376 u32 dwell_time_active;
3377 u32 dwell_time_active_2g;
3378 u32 dwell_time_passive;
3379 u32 dwell_time_active_6g;
3380 u32 dwell_time_passive_6g;
3381 u32 min_rest_time;
3382 u32 max_rest_time;
3383 u32 repeat_probe_time;
3384 u32 probe_spacing_time;
3385 u32 idle_time;
3386 u32 max_scan_time;
3387 u32 probe_delay;
3388 u32 scan_f_passive:1,
3414 u32 burst_duration;
3415 u32 num_chan;
3416 u32 num_bssid;
3417 u32 num_ssids;
3418 u32 n_probes;
3419 u32 *chan_list;
3420 u32 notify_scan_events;
3426 u32 num_hint_s_ssid;
3427 u32 num_hint_bssid;
3459 u32 requester;
3460 u32 scan_id;
3462 u32 vdev_id;
3463 u32 pdev_id;
3467 u32 tlv_header;
3468 u32 vdev_id;
3469 u32 data_len;
3471 u32 frag_ptr;
3472 u32 frag_ptr_lo;
3474 u32 frame_ctrl;
3475 u32 dtim_flag;
3476 u32 bcn_antenna;
3477 u32 frag_ptr_hi;
3504 u32 tlv_header;
3505 u32 mhz;
3506 u32 band_center_freq1;
3507 u32 band_center_freq2;
3508 u32 info;
3509 u32 reg_info_1;
3510 u32 reg_info_2;
3540 u32 tlv_header;
3541 u32 type;
3542 u32 delay_time_ms;
3546 u32 tlv_header;
3547 u32 vdev_id;
3548 u32 param_id;
3549 u32 param_value;
3570 u32 tlv_header;
3572 u32 vdev_id;
3574 u32 pdev_id;
3578 u32 tlv_header;
3579 u32 param;
3580 u32 pdev_id;
3584 u32 len;
3585 u32 msgref;
3586 u32 segmentinfo;
3587 u32 pdev_id;
3591 u32 tlv_header;
3604 u32 vdev_id;
3608 u32 type_count; /* 255: continuous schedule, 0: reserved */
3609 u32 duration; /* Absent period duration in micro seconds */
3610 u32 interval; /* Absent period interval in micro seconds */
3611 u32 start_time; /* 32 bit tsf time when in starts */
3628 u32 noa_attr;
3639 u32 tlv_header;
3640 u32 vdev_id;
3641 u32 tim_ie_offset;
3642 u32 buf_len;
3643 u32 csa_switch_count_offset;
3644 u32 ext_csa_switch_count_offset;
3645 u32 csa_event_bitmap;
3646 u32 mbssid_ie_offset;
3647 u32 esp_ie_offset;
3648 u32 csc_switch_count_offset;
3649 u32 csc_event_bitmap;
3650 u32 mu_edca_ie_offset;
3651 u32 feature_enable_bitmap;
3652 u32 ema_params;
3656 u32 tlv_header;
3657 u32 vdev_id;
3658 u32 ie_buf_len;
3663 u32 key_seq_counter_l;
3664 u32 key_seq_counter_h;
3668 u32 tlv_header;
3669 u32 vdev_id;
3671 u32 key_idx;
3672 u32 key_flags;
3673 u32 key_cipher;
3679 u32 key_len;
3680 u32 key_txmic_len;
3681 u32 key_rxmic_len;
3682 u32 is_group_key_id_valid;
3683 u32 group_key_id;
3691 u32 vdev_id;
3693 u32 key_idx;
3694 u32 key_flags;
3695 u32 key_cipher;
3696 u32 key_len;
3697 u32 key_txmic_len;
3698 u32 key_rxmic_len;
3711 u32 num_rates;
3717 u32 vdev_id;
3718 u32 peer_new_assoc;
3719 u32 peer_associd;
3720 u32 peer_flags;
3721 u32 peer_caps;
3722 u32 peer_listen_intval;
3723 u32 peer_ht_caps;
3724 u32 peer_max_mpdu;
3725 u32 peer_mpdu_density;
3726 u32 peer_rate_caps;
3727 u32 peer_nss;
3728 u32 peer_vht_caps;
3729 u32 peer_phymode;
3730 u32 peer_ht_info[2];
3733 u32 rx_max_rate;
3734 u32 rx_mcs_set;
3735 u32 tx_max_rate;
3736 u32 tx_mcs_set;
3739 u32 tx_max_mcs_nss;
3740 u32 peer_bw_rxnss_override;
3765 u32 peer_he_cap_macinfo[2];
3766 u32 peer_he_cap_macinfo_internal;
3767 u32 peer_he_caps_6ghz;
3768 u32 peer_he_ops;
3769 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE];
3770 u32 peer_he_mcs_count;
3771 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3772 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET];
3780 u32 tlv_header;
3782 u32 vdev_id;
3783 u32 peer_new_assoc;
3784 u32 peer_associd;
3785 u32 peer_flags;
3786 u32 peer_caps;
3787 u32 peer_listen_intval;
3788 u32 peer_ht_caps;
3789 u32 peer_max_mpdu;
3790 u32 peer_mpdu_density;
3791 u32 peer_rate_caps;
3792 u32 peer_nss;
3793 u32 peer_vht_caps;
3794 u32 peer_phymode;
3795 u32 peer_ht_info[2];
3796 u32 num_peer_legacy_rates;
3797 u32 num_peer_ht_rates;
3798 u32 peer_bw_rxnss_override;
3800 u32 peer_he_cap_info;
3801 u32 peer_he_ops;
3802 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
3803 u32 peer_he_mcs;
3804 u32 peer_he_cap_info_ext;
3805 u32 peer_he_cap_info_internal;
3806 u32 min_data_rate;
3807 u32 peer_he_caps_6ghz;
3811 u32 tlv_header;
3812 u32 requestor;
3813 u32 scan_id;
3814 u32 req_type;
3815 u32 vdev_id;
3816 u32 pdev_id;
3820 u32 pdev_id;
3826 u32 tlv_header;
3827 u32 num_scan_chans;
3828 u32 flags;
3829 u32 pdev_id;
3833 u32 tlv_header;
3834 u32 prob_req_oui;
3851 u32 tlv_header;
3852 u32 tx_params_dword0;
3853 u32 tx_params_dword1;
3857 u32 tlv_header;
3858 u32 vdev_id;
3859 u32 desc_id;
3860 u32 chanfreq;
3861 u32 paddr_lo;
3862 u32 paddr_hi;
3863 u32 frame_len;
3864 u32 buf_len;
3865 u32 tx_params_valid;
3873 u32 tlv_header;
3874 u32 vdev_id;
3875 u32 sta_ps_mode;
3879 u32 tlv_header;
3880 u32 vdev_id;
3881 u32 forced_mode;
3885 u32 tlv_header;
3886 u32 vdev_id;
3887 u32 param;
3888 u32 value;
3892 u32 tlv_header;
3893 u32 caps;
3894 u32 erp;
3903 u32 value;
3907 u32 tlv_header;
3908 u32 pdev_id;
3909 u32 enable;
3913 u32 vdev_id;
3914 u32 param;
3915 u32 value;
3919 u32 if_id;
3920 u32 param_id;
3921 u32 param_value;
3925 u32 stats_id;
3926 u32 vdev_id;
3927 u32 pdev_id;
3935 u32 tlv_header;
3936 u32 pdev_id;
3937 u32 new_alpha2;
3963 u32 tlv_header;
3964 u32 pdev_id;
3965 u32 init_cc_type;
3967 u32 country_code;
3968 u32 regdom_id;
3969 u32 alpha2;
3974 u32 vdev_id;
3975 u32 scan_period_msec;
3976 u32 start_interval_msec;
3980 u32 tlv_header;
3981 u32 vdev_id;
3982 u32 scan_period_msec;
3983 u32 start_interval_msec;
3987 u32 tlv_header;
3988 u32 vdev_id;
3992 u32 new_alpha2;
3997 u32 tmplwm;
3998 u32 tmphwm;
3999 u32 dcoffpercent;
4000 u32 priority;
4004 u32 pdev_id;
4005 u32 enable;
4006 u32 dc;
4007 u32 dc_per_event;
4012 u32 tlv_header;
4013 u32 pdev_id;
4014 u32 enable;
4015 u32 dc;
4016 u32 dc_per_event;
4017 u32 therm_throt_levels;
4021 u32 tlv_header;
4022 u32 temp_lwm;
4023 u32 temp_hwm;
4024 u32 dc_off_percent;
4025 u32 prio;
4029 u32 tlv_header;
4030 u32 vdev_id;
4032 u32 tid;
4033 u32 initiator;
4034 u32 reasoncode;
4038 u32 tlv_header;
4039 u32 vdev_id;
4041 u32 tid;
4042 u32 statuscode;
4046 u32 tlv_header;
4047 u32 vdev_id;
4049 u32 tid;
4050 u32 buffersize;
4054 u32 tlv_header;
4055 u32 vdev_id;
4060 u32 tlv_header;
4065 u32 tlv_header;
4066 u32 pdev_id;
4067 u32 enable;
4068 u32 filter_type;
4069 u32 num_mac;
4078 u32 tlv_header;
4079 u32 pdev_id;
4080 u32 evlist; /* WMI_PKTLOG_EVENT */
4081 u32 enable;
4085 u32 tlv_header;
4086 u32 pdev_id;
4101 u32 cmd_id;
4102 u32 pdev_id;
4103 u32 radar_param;
4107 u32 tlv_header;
4108 u32 vdev_id;
4109 u32 module_id;
4110 u32 num_args;
4111 u32 diag_token;
4119 u32 tim_ie_offset;
4120 u32 tmpl_len;
4121 u32 tmpl_len_aligned;
4122 u32 csa_switch_count_offset;
4123 u32 ext_csa_switch_count_offset;
4128 u32 num_rates;
4129 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1];
4133 u32 tlv_header;
4134 u32 rx_max_rate;
4135 u32 rx_mcs_set;
4136 u32 tx_max_rate;
4137 u32 tx_mcs_set;
4138 u32 tx_max_mcs_nss;
4142 u32 tlv_header;
4145 u32 rx_mcs_set;
4148 u32 tx_mcs_set;
4161 u32 vdev_id;
4162 u32 requestor_id;
4164 u32 status;
4165 u32 chain_mask;
4166 u32 smps_mode;
4168 u32 mac_id;
4169 u32 pdev_id;
4171 u32 cfgd_tx_streams;
4172 u32 cfgd_rx_streams;
4426 u32 dfs_region;
4427 u32 phybitmap;
4428 u32 min_bw_2ghz;
4429 u32 max_bw_2ghz;
4430 u32 min_bw_5ghz;
4431 u32 max_bw_5ghz;
4432 u32 num_2ghz_reg_rules;
4433 u32 num_5ghz_reg_rules;
4442 u32 domain_code_6ghz_super_id;
4443 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4444 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4445 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4446 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4447 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE];
4448 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE];
4455 u32 status_code;
4456 u32 phy_id;
4457 u32 alpha2;
4458 u32 num_phy;
4459 u32 country_id;
4460 u32 domain_code;
4461 u32 dfs_region;
4462 u32 phybitmap;
4463 u32 min_bw_2ghz;
4464 u32 max_bw_2ghz;
4465 u32 min_bw_5ghz;
4466 u32 max_bw_5ghz;
4467 u32 num_2ghz_reg_rules;
4468 u32 num_5ghz_reg_rules;
4472 u32 tlv_header;
4473 u32 freq_info;
4474 u32 bw_pwr_info;
4475 u32 flag_info;
4481 u32 status_code;
4482 u32 phy_id;
4483 u32 alpha2;
4484 u32 num_phy;
4485 u32 country_id;
4486 u32 domain_code;
4487 u32 dfs_region;
4488 u32 phybitmap;
4489 u32 min_bw_2ghz;
4490 u32 max_bw_2ghz;
4491 u32 min_bw_5ghz;
4492 u32 max_bw_5ghz;
4493 u32 num_2ghz_reg_rules;
4494 u32 num_5ghz_reg_rules;
4495 u32 client_type;
4496 u32 rnr_tpe_usable;
4497 u32 unspecified_ap_usable;
4498 u32 domain_code_6ghz_ap_lpi;
4499 u32 domain_code_6ghz_ap_sp;
4500 u32 domain_code_6ghz_ap_vlp;
4501 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4502 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4503 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4504 u32 domain_code_6ghz_super_id;
4505 u32 min_bw_6ghz_ap_sp;
4506 u32 max_bw_6ghz_ap_sp;
4507 u32 min_bw_6ghz_ap_lpi;
4508 u32 max_bw_6ghz_ap_lpi;
4509 u32 min_bw_6ghz_ap_vlp;
4510 u32 max_bw_6ghz_ap_vlp;
4511 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4512 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX];
4513 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4514 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX];
4515 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4516 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX];
4517 u32 num_6ghz_reg_rules_ap_sp;
4518 u32 num_6ghz_reg_rules_ap_lpi;
4519 u32 num_6ghz_reg_rules_ap_vlp;
4520 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX];
4521 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX];
4522 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX];
4526 u32 tlv_header;
4527 u32 freq_info;
4528 u32 bw_pwr_info;
4529 u32 flag_info;
4530 u32 psd_power_info;
4534 u32 vdev_id;
4538 u32 vdev_id;
4543 u32 vdev_id;
4544 u32 tx_status;
4548 u32 vdev_id;
4552 u32 freq; /* Units in MHz */
4553 u32 noise_floor; /* units are dBm */
4555 u32 rx_clear_count_low;
4556 u32 rx_clear_count_high;
4558 u32 cycle_count_low;
4559 u32 cycle_count_high;
4561 u32 tx_cycle_count_low;
4562 u32 tx_cycle_count_high;
4564 u32 rx_cycle_count_low;
4565 u32 rx_cycle_count_high;
4567 u32 rx_bss_cycle_count_low;
4568 u32 rx_bss_cycle_count_high;
4569 u32 pdev_id;
4575 u32 vdev_id;
4577 u32 key_idx;
4578 u32 key_flags;
4579 u32 status;
4583 u32 vdev_id;
4585 u32 key_idx;
4586 u32 key_flags;
4587 u32 status;
4591 u32 vdev_id;
4596 u32 vdev_id;
4601 u32 vdev_id;
4602 u32 fils_tt;
4603 u32 tbtt;
4607 u32 vdev_id;
4608 u32 tx_status;
4616 u32 tx_frame_count; /* Cycles spent transmitting frames */
4617 u32 rx_frame_count; /* Cycles spent receiving frames */
4618 u32 rx_clear_count; /* Total channel busy time, evidently */
4619 u32 cycle_count; /* Total on-channel time */
4620 u32 phy_err_count;
4621 u32 chan_tx_pwr;
4625 u32 ack_rx_bad;
4626 u32 rts_bad;
4627 u32 rts_good;
4628 u32 fcs_bad;
4629 u32 no_beacons;
4630 u32 mib_int_count;
4665 u32 hw_paused;
4674 u32 tx_ko;
4676 u32 tx_xretry;
4679 u32 data_rc;
4682 u32 self_triggers;
4685 u32 sw_retry_failure;
4688 u32 illgl_rate_phy_err;
4691 u32 pdev_cont_xretry;
4694 u32 pdev_tx_timeout;
4697 u32 pdev_resets;
4700 u32 stateless_tid_alloc_failure;
4703 u32 phy_underrun;
4706 u32 txop_ovf;
4709 u32 seq_posted;
4712 u32 seq_failed_queueing;
4715 u32 seq_completed;
4718 u32 seq_restarted;
4721 u32 mu_seq_posted;
4791 u32 vdev_id;
4792 u32 beacon_snr;
4793 u32 data_snr;
4794 u32 num_tx_frames[WLAN_MAX_AC];
4795 u32 num_rx_frames;
4796 u32 num_tx_frames_retries[WLAN_MAX_AC];
4797 u32 num_tx_frames_failures[WLAN_MAX_AC];
4798 u32 num_rts_fail;
4799 u32 num_rts_success;
4800 u32 num_rx_err;
4801 u32 num_rx_discard;
4802 u32 num_tx_not_acked;
4803 u32 tx_rate_history[MAX_TX_RATE_VALUES];
4804 u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
4808 u32 vdev_id;
4809 u32 tx_bcn_succ_cnt;
4810 u32 tx_bcn_outage_cnt;
4814 u32 stats_id;
4815 u32 num_pdev_stats;
4816 u32 num_vdev_stats;
4817 u32 num_peer_stats;
4818 u32 num_bcnflt_stats;
4819 u32 num_chan_stats;
4820 u32 num_mib_stats;
4821 u32 pdev_id;
4822 u32 num_bcn_stats;
4823 u32 num_peer_extd_stats;
4824 u32 num_peer_extd2_stats;
4828 u32 vdev_id;
4829 u32 rssi_avg_beacon[WMI_MAX_CHAINS];
4830 u32 rssi_avg_data[WMI_MAX_CHAINS];
4835 u32 num_per_chain_rssi_stats;
4839 u32 pdev_id;
4840 u32 ctl_failsafe_status;
4844 u32 pdev_id;
4845 u32 current_switch_count;
4846 u32 num_vdevs;
4850 u32 pdev_id;
4851 u32 detection_mode;
4852 u32 chan_freq;
4853 u32 chan_width;
4854 u32 detector_id;
4855 u32 segment_id;
4856 u32 timestamp;
4857 u32 is_chirp;
4865 u32 pdev_id;
4877 u32 chan_freq;
4878 u32 channel;
4879 u32 snr;
4881 u32 rate;
4883 u32 buf_len;
4885 u32 flags;
4887 u32 tsf_delta;
4894 u32 channel;
4895 u32 snr;
4896 u32 rate;
4897 u32 phy_mode;
4898 u32 buf_len;
4899 u32 status;
4900 u32 rssi_ctl[ATH_MAX_ANTENNA];
4901 u32 flags;
4903 u32 tsf_delta;
4904 u32 rx_tsf_l32;
4905 u32 rx_tsf_u32;
4906 u32 pdev_id;
4907 u32 chan_freq;
4913 u32 tlv_header;
4914 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA];
4918 u32 desc_id;
4919 u32 status;
4920 u32 pdev_id;
4921 u32 ppdu_id;
4922 u32 ack_rssi;
4926 u32 event_type; /* %WMI_SCAN_EVENT_ */
4927 u32 reason; /* %WMI_SCAN_REASON_ */
4928 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */
4929 u32 scan_req_id;
4930 u32 scan_id;
4931 u32 vdev_id;
4937 u32 tsf_timestamp;
4960 u32 vdev_id;
4961 u32 reason;
4962 u32 rssi;
4969 u32 err_code;
4970 u32 freq;
4971 u32 cmd_flags;
4972 u32 noise_floor;
4973 u32 rx_clear_count;
4974 u32 cycle_count;
4975 u32 chan_tx_pwr_range;
4976 u32 chan_tx_pwr_tp;
4977 u32 rx_frame_count;
4978 u32 my_bss_rx_cycle_count;
4979 u32 rx_11b_mode_data_duration;
4980 u32 tx_frame_cnt;
4981 u32 mac_clk_mhz;
4982 u32 vdev_id;
4986 u32 phy_capability;
4987 u32 max_frag_entry;
4988 u32 num_rf_chains;
4989 u32 ht_cap_info;
4990 u32 vht_cap_info;
4991 u32 vht_supp_mcs;
4992 u32 hw_min_tx_power;
4993 u32 hw_max_tx_power;
4994 u32 sys_cap_info;
4995 u32 min_pkt_size_enable;
4996 u32 max_bcn_ie_size;
4997 u32 max_num_scan_channels;
4998 u32 max_supported_macs;
4999 u32 wmi_fw_sub_feat_caps;
5000 u32 txrx_chainmask;
5001 u32 default_dbs_hw_mode_index;
5002 u32 num_msdu_desc;
5052 u32 wmm_ac;
5053 u32 user_priority;
5054 u32 service_interval;
5055 u32 suspend_interval;
5056 u32 delay_interval;
5060 u32 vdev_id;
5062 u32 num_ac;
5066 u32 wmm_ac;
5067 u32 user_priority;
5068 u32 service_interval;
5069 u32 suspend_interval;
5070 u32 delay_interval;
5234 u32 eeprom_rd;
5235 u32 eeprom_rd_ext;
5236 u32 regcap1;
5237 u32 regcap2;
5238 u32 wireless_modes;
5239 u32 low_2ghz_chan;
5240 u32 high_2ghz_chan;
5241 u32 low_5ghz_chan;
5242 u32 high_5ghz_chan;
5248 u32 len;
5249 u32 req_id;
5269 u32 tlv_header;
5270 u32 cwmin;
5271 u32 cwmax;
5272 u32 aifs;
5273 u32 txoplimit;
5274 u32 acm;
5275 u32 no_ack;
5288 u32 tlv_header;
5289 u32 vdev_id;
5291 u32 wmm_param_type;
5318 u32 sta_cong_timer_ms;
5319 u32 mbss_support;
5320 u32 default_slot_size;
5321 u32 congestion_thresh_setup;
5322 u32 congestion_thresh_teardown;
5323 u32 congestion_thresh_critical;
5324 u32 interference_thresh_teardown;
5325 u32 interference_thresh_setup;
5326 u32 min_no_sta_setup;
5327 u32 min_no_sta_teardown;
5328 u32 no_of_bcast_mcast_slots;
5329 u32 min_no_twt_slots;
5330 u32 max_no_sta_twt;
5331 u32 mode_check_interval;
5332 u32 add_sta_slot_interval;
5333 u32 remove_sta_slot_interval;
5337 u32 tlv_header;
5338 u32 pdev_id;
5339 u32 sta_cong_timer_ms;
5340 u32 mbss_support;
5341 u32 default_slot_size;
5342 u32 congestion_thresh_setup;
5343 u32 congestion_thresh_teardown;
5344 u32 congestion_thresh_critical;
5345 u32 interference_thresh_teardown;
5346 u32 interference_thresh_setup;
5347 u32 min_no_sta_setup;
5348 u32 min_no_sta_teardown;
5349 u32 no_of_bcast_mcast_slots;
5350 u32 min_no_twt_slots;
5351 u32 max_no_sta_twt;
5352 u32 mode_check_interval;
5353 u32 add_sta_slot_interval;
5354 u32 remove_sta_slot_interval;
5358 u32 tlv_header;
5359 u32 pdev_id;
5379 u32 tlv_header;
5380 u32 vdev_id;
5382 u32 dialog_id;
5383 u32 wake_intvl_us;
5384 u32 wake_intvl_mantis;
5385 u32 wake_dura_us;
5386 u32 sp_offset_us;
5387 u32 flags;
5391 u32 vdev_id;
5393 u32 dialog_id;
5394 u32 wake_intvl_us;
5395 u32 wake_intvl_mantis;
5396 u32 wake_dura_us;
5397 u32 sp_offset_us;
5419 u32 vdev_id;
5421 u32 dialog_id;
5422 u32 status;
5426 u32 vdev_id;
5428 u32 dialog_id;
5432 u32 tlv_header;
5433 u32 vdev_id;
5435 u32 dialog_id;
5439 u32 vdev_id;
5441 u32 dialog_id;
5445 u32 tlv_header;
5446 u32 vdev_id;
5448 u32 dialog_id;
5452 u32 vdev_id;
5454 u32 dialog_id;
5455 u32 sp_offset_us;
5456 u32 next_twt_size;
5460 u32 tlv_header;
5461 u32 vdev_id;
5463 u32 dialog_id;
5464 u32 sp_offset_us;
5465 u32 next_twt_size;
5469 u32 tlv_header;
5470 u32 pdev_id;
5471 u32 enable;
5474 u32 vdev_id;
5478 u32 tlv_header;
5479 u32 pdev_id;
5480 u32 bitmap[2];
5498 u32 tlv_header;
5499 u32 vdev_id;
5500 u32 flags;
5501 u32 evt_type;
5502 u32 current_bss_color;
5503 u32 detection_period_ms;
5504 u32 scan_period_ms;
5505 u32 free_slot_expiry_time_ms;
5509 u32 tlv_header;
5510 u32 vdev_id;
5511 u32 enable;
5515 u32 vdev_id;
5516 u32 evt_type;
5524 u32 tlv_header;
5525 u32 lro_enable;
5526 u32 res;
5527 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE];
5528 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE];
5529 u32 pdev_id;
5552 u32 vdev_id;
5553 u32 scan_count;
5554 u32 scan_period;
5555 u32 scan_priority;
5556 u32 scan_fft_size;
5557 u32 scan_gc_ena;
5558 u32 scan_restart_ena;
5559 u32 scan_noise_floor_ref;
5560 u32 scan_init_delay;
5561 u32 scan_nb_tone_thr;
5562 u32 scan_str_bin_thr;
5563 u32 scan_wb_rpt_mode;
5564 u32 scan_rssi_rpt_mode;
5565 u32 scan_rssi_thr;
5566 u32 scan_pwr_format;
5567 u32 scan_rpt_mode;
5568 u32 scan_bin_scale;
5569 u32 scan_dbm_adj;
5570 u32 scan_chn_mask;
5574 u32 tlv_header;
5584 u32 tlv_header;
5585 u32 vdev_id;
5586 u32 trigger_cmd;
5587 u32 enable_cmd;
5591 u32 tlv_header;
5592 u32 pdev_id;
5593 u32 module_id; /* see enum wmi_direct_buffer_module */
5594 u32 base_paddr_lo;
5595 u32 base_paddr_hi;
5596 u32 head_idx_paddr_lo;
5597 u32 head_idx_paddr_hi;
5598 u32 tail_idx_paddr_lo;
5599 u32 tail_idx_paddr_hi;
5600 u32 num_elems; /* Number of elems in the ring */
5601 u32 buf_size; /* size of allocated buffer in bytes */
5604 u32 num_resp_per_event;
5609 u32 event_timeout_ms;
5613 u32 pdev_id;
5614 u32 module_id;
5615 u32 num_buf_release_entry;
5616 u32 num_meta_data_entry;
5620 u32 tlv_header;
5621 u32 paddr_lo;
5626 u32 paddr_hi;
5635 u32 tlv_header;
5637 u32 reset_delay;
5638 u32 freq1;
5639 u32 freq2;
5640 u32 ch_width;
5649 u32 tlv_header;
5650 u32 vdev_id;
5651 u32 interval;
5652 u32 config; /* enum wmi_fils_discovery_cmd_type */
5656 u32 tlv_header;
5657 u32 vdev_id;
5658 u32 buf_len;
5662 u32 tlv_header;
5663 u32 vdev_id;
5664 u32 buf_len;
5668 u32 num_vdevs;
5669 u32 num_peers;
5670 u32 num_active_peers;
5671 u32 num_offload_peers;
5672 u32 num_offload_reorder_buffs;
5673 u32 num_peer_keys;
5674 u32 num_tids;
5675 u32 ast_skid_limit;
5676 u32 tx_chain_mask;
5677 u32 rx_chain_mask;
5678 u32 rx_timeout_pri[4];
5679 u32 rx_decap_mode;
5680 u32 scan_max_pending_req;
5681 u32 bmiss_offload_max_vdev;
5682 u32 roam_offload_max_vdev;
5683 u32 roam_offload_max_ap_profiles;
5684 u32 num_mcast_groups;
5685 u32 num_mcast_table_elems;
5686 u32 mcast2ucast_mode;
5687 u32 tx_dbg_log_size;
5688 u32 num_wds_entries;
5689 u32 dma_burst_size;
5690 u32 mac_aggr_delim;
5691 u32 rx_skip_defrag_timeout_dup_detection_check;
5692 u32 vow_config;
5693 u32 gtk_offload_max_vdev;
5694 u32 num_msdu_desc;
5695 u32 max_frag_entries;
5696 u32 max_peer_ext_stats;
5697 u32 smart_ant_cap;
5698 u32 bk_minfree;
5699 u32 be_minfree;
5700 u32 vi_minfree;
5701 u32 vo_minfree;
5702 u32 rx_batchmode;
5703 u32 tt_support;
5704 u32 flag1;
5705 u32 iphdr_pad_config;
5706 u32 qwrap_config:16,
5708 u32 num_tdls_vdevs;
5709 u32 num_tdls_conn_table_entries;
5710 u32 beacon_tx_offload_max_vdev;
5711 u32 num_multicast_filter_entries;
5712 u32 num_wow_filters;
5713 u32 num_keep_alive_pattern;
5714 u32 keep_alive_pattern_size;
5715 u32 max_tdls_concurrent_sleep_sta;
5716 u32 max_tdls_concurrent_buffer_sta;
5717 u32 wmi_send_separate;
5718 u32 num_ocb_vdevs;
5719 u32 num_ocb_channels;
5720 u32 num_ocb_schedules;
5721 u32 num_ns_ext_tuples_cfg;
5722 u32 bpf_instruction_size;
5723 u32 max_bssid_rx_filters;
5724 u32 use_pdev_id;
5725 u32 peer_map_unmap_v2_support;
5726 u32 sched_params;
5727 u32 twt_ap_pdev_count;
5728 u32 twt_ap_sta_count;
5730 u32 ema_max_vap_cnt;
5731 u32 ema_max_profile_period;
5744 u32 tlv_header;
5745 u32 dbg_log_param;
5746 u32 value;
5768 u32 peer_ps_state;
5769 u32 ps_supported_bitmap;
5770 u32 peer_ps_valid;
5771 u32 peer_ps_timestamp;
5778 u32 max_msg_len[MAX_RADIOS];
5784 u32 num_mem_chunks;
5785 u32 rx_decap_mode;
5801 u32 tlv_header;
5802 u32 vdev_id;
5803 u32 enable;
5804 u32 hw_filter_bitmap;
5952 u32 vdev_id;
5953 u32 flag;
5955 u32 data_len;
5984 u32 tlv_header;
5985 u32 vdev_id;
5986 u32 is_add;
5987 u32 event_bitmap;
5991 u32 tlv_header;
5992 u32 enable;
5993 u32 pause_iface_config;
5994 u32 flags;
5998 u32 tlv_header;
5999 u32 reserved;
6003 u32 vdev_id;
6004 u32 flag;
6005 u32 wake_reason;
6006 u32 data_len;
6010 u32 tlv_header;
6013 u32 pattern_offset;
6014 u32 pattern_len;
6015 u32 bitmask_len;
6016 u32 pattern_id;
6020 u32 tlv_header;
6021 u32 vdev_id;
6022 u32 pattern_id;
6023 u32 pattern_type;
6027 u32 tlv_header;
6028 u32 vdev_id;
6029 u32 pattern_id;
6030 u32 pattern_type;
6079 u32 valid;
6084 u32 valid;
6085 u32 enc_type;
6089 u32 valid;
6090 u32 auth_type;
6094 u32 valid;
6095 u32 bcast_nw_type;
6099 u32 valid;
6105 u32 tlv_header;
6117 u32 authentication;
6118 u32 encryption;
6119 u32 bcast_nw_type;
6130 u32 fast_scan_period;
6131 u32 slow_scan_period;
6136 u32 delay_start_time;
6137 u32 active_min_time;
6138 u32 active_max_time;
6139 u32 passive_min_time;
6140 u32 passive_max_time;
6143 u32 enable_pno_scan_randomization;
6149 u32 tlv_header;
6150 u32 flags;
6151 u32 vdev_id;
6152 u32 fast_scan_max_cycles;
6153 u32 active_dwell_time;
6154 u32 passive_dwell_time;
6155 u32 probe_bundle_size;
6158 u32 rest_time;
6161 u32 max_rest_time;
6164 u32 scan_backoff_multiplier;
6167 u32 fast_scan_period;
6170 u32 slow_scan_period;
6172 u32 no_of_ssids;
6174 u32 num_of_channels;
6177 u32 delay_start_time;
6186 u32 ie_bitmap[8];
6189 u32 num_vendor_oui;
6192 u32 num_cnlo_band_pref;
6196 * u32 channel_list[num_of_channels];
6208 u32 tlv_header;
6209 u32 flags;
6223 u32 tlv_header;
6224 u32 flags;
6232 u32 tlv_header;
6233 u32 flags;
6234 u32 vdev_id;
6235 u32 num_ns_ext_tuples;
6258 u32 word0;
6259 u32 word1;
6265 u32 vdev_id;
6266 u32 flags;
6267 u32 refresh_cnt;
6280 u32 tlv_header;
6281 u32 vdev_id;
6282 u32 flags;
6293 u32 tlv_header;
6294 u32 pdev_id;
6295 u32 sar_len;
6296 u32 rsvd_len;
6300 u32 tlv_header;
6301 u32 pdev_id;
6302 u32 rsvd_len;
6306 u32 tlv_header;
6307 u32 vdev_id;
6308 u32 enabled;
6311 u32 method;
6314 u32 interval;
6322 u32 tlv_header;
6323 u32 src_ip4_addr;
6324 u32 dest_ip4_addr;
6329 u32 vdev_id;
6330 u32 enabled;
6331 u32 method;
6332 u32 interval;
6333 u32 src_ip4_addr;
6334 u32 dest_ip4_addr;
6352 u32 cmd_id);
6353 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len);
6354 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id,
6356 int ath11k_wmi_p2p_go_bcn_ie(struct ath11k *ar, u32 vdev_id,
6358 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id,
6360 struct sk_buff *bcn, u32 ema_param);
6362 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid,
6363 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx,
6364 u32 nontx_profile_cnt);
6369 u32 vdev_id, u32 param_id, u32 param_val);
6370 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id,
6371 u32 param_value, u8 pdev_id);
6387 u32 ba_window_size);
6390 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id,
6391 u32 param_id, u32 param_value);
6393 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id,
6394 u32 param, u32 param_value);
6395 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms);
6404 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id,
6406 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt,
6407 u32 pdev_id);
6408 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id);
6427 u32 pdev_id);
6428 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac);
6429 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6430 u32 tid, u32 buf_size);
6431 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6432 u32 tid, u32 status);
6433 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac,
6434 u32 tid, u32 initiator, u32 reason);
6436 u32 vdev_id, u32 bcn_ctrl_op);
6445 int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id);
6450 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter);
6461 struct ath11k_fw_stats *fw_stats, u32 stats_id,
6465 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id,
6467 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id);
6476 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id,
6478 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap);
6479 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap);
6481 u32 *bitmap);
6483 u32 *bitmap);
6485 u32 *bitmap);
6487 u32 *bitmap);
6488 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id,
6489 u8 bss_color, u32 period,
6491 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id,
6496 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id,
6497 u32 trigger, u32 enable);
6500 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id,
6502 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval,
6504 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id,
6512 int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap,
6514 int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id,
6516 int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id);
6517 int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id,
6520 int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id,
6522 u32 enable);
6523 int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id,
6524 u32 filter_bitmap, bool enable);
6537 u32 vdev_id,