Lines Matching +full:reo2host +full:- +full:destination +full:- +full:ring3
1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
15 "mhi-er0",
16 "mhi-er1",
29 "host2wbm-desc-feed",
30 "host2reo-re-injection",
31 "host2reo-command",
32 "host2rxdma-monitor-ring3",
33 "host2rxdma-monitor-ring2",
34 "host2rxdma-monitor-ring1",
35 "reo2ost-exception",
36 "wbm2host-rx-release",
37 "reo2host-status",
38 "reo2host-destination-ring4",
39 "reo2host-destination-ring3",
40 "reo2host-destination-ring2",
41 "reo2host-destination-ring1",
42 "rxdma2host-monitor-destination-mac3",
43 "rxdma2host-monitor-destination-mac2",
44 "rxdma2host-monitor-destination-mac1",
45 "ppdu-end-interrupts-mac3",
46 "ppdu-end-interrupts-mac2",
47 "ppdu-end-interrupts-mac1",
48 "rxdma2host-monitor-status-ring-mac3",
49 "rxdma2host-monitor-status-ring-mac2",
50 "rxdma2host-monitor-status-ring-mac1",
51 "host2rxdma-host-buf-ring-mac3",
52 "host2rxdma-host-buf-ring-mac2",
53 "host2rxdma-host-buf-ring-mac1",
54 "rxdma2host-destination-ring-mac3",
55 "rxdma2host-destination-ring-mac2",
56 "rxdma2host-destination-ring-mac1",
57 "host2tcl-input-ring4",
58 "host2tcl-input-ring3",
59 "host2tcl-input-ring2",
60 "host2tcl-input-ring1",
61 "wbm2host-tx-completions-ring3",
62 "wbm2host-tx-completions-ring2",
63 "wbm2host-tx-completions-ring1",
64 "tcl2host-status-ring",
152 if (msi_config->hw_rev == ab->hw_rev) in ath11k_pcic_init_msi_config()
158 ab->hw_rev); in ath11k_pcic_init_msi_config()
159 return -EINVAL; in ath11k_pcic_init_msi_config()
162 ab->pci.msi.config = msi_config; in ath11k_pcic_init_msi_config()
170 iowrite32(value, ab->mem + offset); in __ath11k_pcic_write32()
172 ab->pci.ops->window_write32(ab, offset, value); in __ath11k_pcic_write32()
180 /* for offset beyond BAR + 4K - 32, may in ath11k_pcic_write32()
183 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && in ath11k_pcic_write32()
185 if (wakeup_required && ab->pci.ops->wakeup) in ath11k_pcic_write32()
186 ret = ab->pci.ops->wakeup(ab); in ath11k_pcic_write32()
190 if (wakeup_required && !ret && ab->pci.ops->release) in ath11k_pcic_write32()
191 ab->pci.ops->release(ab); in ath11k_pcic_write32()
200 val = ioread32(ab->mem + offset); in __ath11k_pcic_read32()
202 val = ab->pci.ops->window_read32(ab, offset); in __ath11k_pcic_read32()
213 /* for offset beyond BAR + 4K - 32, may in ath11k_pcic_read32()
216 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && in ath11k_pcic_read32()
218 if (wakeup_required && ab->pci.ops->wakeup) in ath11k_pcic_read32()
219 ret = ab->pci.ops->wakeup(ab); in ath11k_pcic_read32()
223 if (wakeup_required && !ret && ab->pci.ops->release) in ath11k_pcic_read32()
224 ab->pci.ops->release(ab); in ath11k_pcic_read32()
237 /* for offset beyond BAR + 4K - 32, may in ath11k_pcic_read()
240 wakeup_required = test_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags) && in ath11k_pcic_read()
242 if (wakeup_required && ab->pci.ops->wakeup) { in ath11k_pcic_read()
243 ret = ab->pci.ops->wakeup(ab); in ath11k_pcic_read()
261 if (wakeup_required && ab->pci.ops->release) in ath11k_pcic_read()
262 ab->pci.ops->release(ab); in ath11k_pcic_read()
271 *msi_addr_lo = ab->pci.msi.addr_lo; in ath11k_pcic_get_msi_address()
272 *msi_addr_hi = ab->pci.msi.addr_hi; in ath11k_pcic_get_msi_address()
280 const struct ath11k_msi_config *msi_config = ab->pci.msi.config; in ath11k_pcic_get_user_msi_assignment()
283 for (idx = 0; idx < msi_config->total_users; idx++) { in ath11k_pcic_get_user_msi_assignment()
284 if (strcmp(user_name, msi_config->users[idx].name) == 0) { in ath11k_pcic_get_user_msi_assignment()
285 *num_vectors = msi_config->users[idx].num_vectors; in ath11k_pcic_get_user_msi_assignment()
286 *base_vector = msi_config->users[idx].base_vector; in ath11k_pcic_get_user_msi_assignment()
287 *user_base_data = *base_vector + ab->pci.msi.ep_base_data; in ath11k_pcic_get_user_msi_assignment()
300 return -EINVAL; in ath11k_pcic_get_user_msi_assignment()
308 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_get_ce_msi_idx()
326 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_free_ext_irq()
328 for (j = 0; j < irq_grp->num_irq; j++) in ath11k_pcic_free_ext_irq()
329 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); in ath11k_pcic_free_ext_irq()
331 netif_napi_del(&irq_grp->napi); in ath11k_pcic_free_ext_irq()
332 free_netdev(irq_grp->napi_ndev); in ath11k_pcic_free_ext_irq()
340 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_free_irq()
344 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); in ath11k_pcic_free_irq()
358 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ce_irq_enable()
362 enable_irq(ab->irq_num[irq_idx]); in ath11k_pcic_ce_irq_enable()
372 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ce_irq_disable()
376 disable_irq_nosync(ab->irq_num[irq_idx]); in ath11k_pcic_ce_irq_disable()
383 clear_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath11k_pcic_ce_irqs_disable()
385 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_ce_irqs_disable()
397 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_sync_ce_irqs()
402 synchronize_irq(ab->irq_num[irq_idx]); in ath11k_pcic_sync_ce_irqs()
409 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; in ath11k_pcic_ce_tasklet()
411 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); in ath11k_pcic_ce_tasklet()
413 enable_irq(ce_pipe->ab->irq_num[irq_idx]); in ath11k_pcic_ce_tasklet()
419 struct ath11k_base *ab = ce_pipe->ab; in ath11k_pcic_ce_interrupt_handler()
420 int irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_pipe->pipe_num; in ath11k_pcic_ce_interrupt_handler()
422 if (!test_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags)) in ath11k_pcic_ce_interrupt_handler()
426 ce_pipe->timestamp = jiffies; in ath11k_pcic_ce_interrupt_handler()
428 disable_irq_nosync(ab->irq_num[irq_idx]); in ath11k_pcic_ce_interrupt_handler()
430 tasklet_schedule(&ce_pipe->intr_tq); in ath11k_pcic_ce_interrupt_handler()
437 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_grp_disable()
443 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ext_grp_disable()
446 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_grp_disable()
447 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_grp_disable()
454 clear_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in __ath11k_pcic_ext_irq_disable()
457 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in __ath11k_pcic_ext_irq_disable()
461 if (irq_grp->napi_enabled) { in __ath11k_pcic_ext_irq_disable()
462 napi_synchronize(&irq_grp->napi); in __ath11k_pcic_ext_irq_disable()
463 napi_disable(&irq_grp->napi); in __ath11k_pcic_ext_irq_disable()
464 irq_grp->napi_enabled = false; in __ath11k_pcic_ext_irq_disable()
471 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_grp_enable()
477 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ext_grp_enable()
480 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_grp_enable()
481 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_grp_enable()
489 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_ext_irq_enable()
491 if (!irq_grp->napi_enabled) { in ath11k_pcic_ext_irq_enable()
492 napi_enable(&irq_grp->napi); in ath11k_pcic_ext_irq_enable()
493 irq_grp->napi_enabled = true; in ath11k_pcic_ext_irq_enable()
498 set_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags); in ath11k_pcic_ext_irq_enable()
507 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_sync_ext_irqs()
509 for (j = 0; j < irq_grp->num_irq; j++) { in ath11k_pcic_sync_ext_irqs()
510 irq_idx = irq_grp->irqs[j]; in ath11k_pcic_sync_ext_irqs()
511 synchronize_irq(ab->irq_num[irq_idx]); in ath11k_pcic_sync_ext_irqs()
528 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_grp_napi_poll()
535 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_grp_napi_poll()
536 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_grp_napi_poll()
548 struct ath11k_base *ab = irq_grp->ab; in ath11k_pcic_ext_interrupt_handler()
551 if (!test_bit(ATH11K_FLAG_EXT_IRQ_ENABLED, &ab->dev_flags)) in ath11k_pcic_ext_interrupt_handler()
554 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq %d\n", irq); in ath11k_pcic_ext_interrupt_handler()
557 irq_grp->timestamp = jiffies; in ath11k_pcic_ext_interrupt_handler()
559 for (i = 0; i < irq_grp->num_irq; i++) in ath11k_pcic_ext_interrupt_handler()
560 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); in ath11k_pcic_ext_interrupt_handler()
562 napi_schedule(&irq_grp->napi); in ath11k_pcic_ext_interrupt_handler()
570 return ab->pci.ops->get_msi_irq(ab, vector); in ath11k_pcic_get_msi_irq()
587 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_ext_irq_config()
591 irq_grp = &ab->ext_irq_grp[i]; in ath11k_pcic_ext_irq_config()
594 irq_grp->ab = ab; in ath11k_pcic_ext_irq_config()
595 irq_grp->grp_id = i; in ath11k_pcic_ext_irq_config()
596 irq_grp->napi_ndev = alloc_netdev_dummy(0); in ath11k_pcic_ext_irq_config()
597 if (!irq_grp->napi_ndev) { in ath11k_pcic_ext_irq_config()
598 ret = -ENOMEM; in ath11k_pcic_ext_irq_config()
602 netif_napi_add(irq_grp->napi_ndev, &irq_grp->napi, in ath11k_pcic_ext_irq_config()
605 if (ab->hw_params.ring_mask->tx[i] || in ath11k_pcic_ext_irq_config()
606 ab->hw_params.ring_mask->rx[i] || in ath11k_pcic_ext_irq_config()
607 ab->hw_params.ring_mask->rx_err[i] || in ath11k_pcic_ext_irq_config()
608 ab->hw_params.ring_mask->rx_wbm_rel[i] || in ath11k_pcic_ext_irq_config()
609 ab->hw_params.ring_mask->reo_status[i] || in ath11k_pcic_ext_irq_config()
610 ab->hw_params.ring_mask->rxdma2host[i] || in ath11k_pcic_ext_irq_config()
611 ab->hw_params.ring_mask->host2rxdma[i] || in ath11k_pcic_ext_irq_config()
612 ab->hw_params.ring_mask->rx_mon_status[i]) { in ath11k_pcic_ext_irq_config()
616 irq_grp->num_irq = num_irq; in ath11k_pcic_ext_irq_config()
617 irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i; in ath11k_pcic_ext_irq_config()
619 for (j = 0; j < irq_grp->num_irq; j++) { in ath11k_pcic_ext_irq_config()
620 int irq_idx = irq_grp->irqs[j]; in ath11k_pcic_ext_irq_config()
629 ab->irq_num[irq_idx] = irq; in ath11k_pcic_ext_irq_config()
641 irq_grp = &ab->ext_irq_grp[n]; in ath11k_pcic_ext_irq_config()
642 free_netdev(irq_grp->napi_ndev); in ath11k_pcic_ext_irq_config()
652 /* i ->napi_ndev was properly allocated. Free it also */ in ath11k_pcic_ext_irq_config()
656 irq_grp = &ab->ext_irq_grp[n]; in ath11k_pcic_ext_irq_config()
657 free_netdev(irq_grp->napi_ndev); in ath11k_pcic_ext_irq_config()
678 if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) in ath11k_pcic_config_irq()
682 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_config_irq()
691 ce_pipe = &ab->ce.ce_pipe[i]; in ath11k_pcic_config_irq()
695 tasklet_setup(&ce_pipe->intr_tq, ath11k_pcic_ce_tasklet); in ath11k_pcic_config_irq()
705 ab->irq_num[irq_idx] = irq; in ath11k_pcic_config_irq()
723 set_bit(ATH11K_FLAG_CE_IRQ_ENABLED, &ab->dev_flags); in ath11k_pcic_ce_irqs_enable()
725 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_ce_irqs_enable()
737 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pcic_kill_tasklets()
738 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; in ath11k_pcic_kill_tasklets()
743 tasklet_kill(&ce_pipe->intr_tq); in ath11k_pcic_kill_tasklets()
764 set_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); in ath11k_pcic_start()
780 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { in ath11k_pcic_map_service_to_pipe()
781 entry = &ab->hw_params.svc_to_ce_map[i]; in ath11k_pcic_map_service_to_pipe()
783 if (__le32_to_cpu(entry->service_id) != service_id) in ath11k_pcic_map_service_to_pipe()
786 switch (__le32_to_cpu(entry->pipedir)) { in ath11k_pcic_map_service_to_pipe()
791 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
796 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
802 *dl_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
803 *ul_pipe = __le32_to_cpu(entry->pipenum); in ath11k_pcic_map_service_to_pipe()
811 return -ENOENT; in ath11k_pcic_map_service_to_pipe()
824 if (!pci_ops->get_msi_irq || !pci_ops->window_write32 || in ath11k_pcic_register_pci_ops()
825 !pci_ops->window_read32) in ath11k_pcic_register_pci_ops()
826 return -EINVAL; in ath11k_pcic_register_pci_ops()
828 ab->pci.ops = pci_ops; in ath11k_pcic_register_pci_ops()
837 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pci_enable_ce_irqs_except_wake_irq()
852 for (i = 0; i < ab->hw_params.ce_count; i++) { in ath11k_pci_disable_ce_irqs_except_wake_irq()
853 ce_pipe = &ab->ce.ce_pipe[i]; in ath11k_pci_disable_ce_irqs_except_wake_irq()
860 disable_irq_nosync(ab->irq_num[irq_idx]); in ath11k_pci_disable_ce_irqs_except_wake_irq()
861 synchronize_irq(ab->irq_num[irq_idx]); in ath11k_pci_disable_ce_irqs_except_wake_irq()
862 tasklet_kill(&ce_pipe->intr_tq); in ath11k_pci_disable_ce_irqs_except_wake_irq()