Lines Matching defs:ab
145 ath11k_ahb_get_msi_irq_wcn6750(struct ath11k_base *ab, unsigned int vector)
147 return ab->pci.msi.irqs[vector];
151 ath11k_ahb_get_window_start_wcn6750(struct ath11k_base *ab, u32 offset)
159 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
167 ath11k_ahb_window_write32_wcn6750(struct ath11k_base *ab, u32 offset, u32 value)
172 window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);
174 iowrite32(value, ab->mem + window_start +
178 static u32 ath11k_ahb_window_read32_wcn6750(struct ath11k_base *ab, u32 offset)
184 window_start = ath11k_ahb_get_window_start_wcn6750(ab, offset);
186 val = ioread32(ab->mem + window_start +
199 static inline u32 ath11k_ahb_read32(struct ath11k_base *ab, u32 offset)
201 return ioread32(ab->mem + offset);
204 static inline void ath11k_ahb_write32(struct ath11k_base *ab, u32 offset, u32 value)
206 iowrite32(value, ab->mem + offset);
209 static void ath11k_ahb_kill_tasklets(struct ath11k_base *ab)
213 for (i = 0; i < ab->hw_params.ce_count; i++) {
214 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
216 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
228 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
231 static void __ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
236 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
253 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
256 static void ath11k_ahb_setbit32(struct ath11k_base *ab, u8 bit, u32 offset)
260 val = ath11k_ahb_read32(ab, offset);
261 ath11k_ahb_write32(ab, offset, val | BIT(bit));
264 static void ath11k_ahb_clearbit32(struct ath11k_base *ab, u8 bit, u32 offset)
268 val = ath11k_ahb_read32(ab, offset);
269 ath11k_ahb_write32(ab, offset, val & ~BIT(bit));
272 static void ath11k_ahb_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
275 const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr;
278 ie1_reg_addr = ce_ie_addr->ie1_reg_addr + ATH11K_CE_OFFSET(ab);
279 ie2_reg_addr = ce_ie_addr->ie2_reg_addr + ATH11K_CE_OFFSET(ab);
280 ie3_reg_addr = ce_ie_addr->ie3_reg_addr + ATH11K_CE_OFFSET(ab);
282 ce_attr = &ab->hw_params.host_ce_config[ce_id];
284 ath11k_ahb_setbit32(ab, ce_id, ie1_reg_addr);
287 ath11k_ahb_setbit32(ab, ce_id, ie2_reg_addr);
288 ath11k_ahb_setbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
293 static void ath11k_ahb_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
296 const struct ce_ie_addr *ce_ie_addr = ab->hw_params.ce_ie_addr;
299 ie1_reg_addr = ce_ie_addr->ie1_reg_addr + ATH11K_CE_OFFSET(ab);
300 ie2_reg_addr = ce_ie_addr->ie2_reg_addr + ATH11K_CE_OFFSET(ab);
301 ie3_reg_addr = ce_ie_addr->ie3_reg_addr + ATH11K_CE_OFFSET(ab);
303 ce_attr = &ab->hw_params.host_ce_config[ce_id];
305 ath11k_ahb_clearbit32(ab, ce_id, ie1_reg_addr);
308 ath11k_ahb_clearbit32(ab, ce_id, ie2_reg_addr);
309 ath11k_ahb_clearbit32(ab, ce_id + CE_HOST_IE_3_SHIFT,
314 static void ath11k_ahb_sync_ce_irqs(struct ath11k_base *ab)
319 for (i = 0; i < ab->hw_params.ce_count; i++) {
320 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
324 synchronize_irq(ab->irq_num[irq_idx]);
328 static void ath11k_ahb_sync_ext_irqs(struct ath11k_base *ab)
334 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
338 synchronize_irq(ab->irq_num[irq_idx]);
343 static void ath11k_ahb_ce_irqs_enable(struct ath11k_base *ab)
347 for (i = 0; i < ab->hw_params.ce_count; i++) {
348 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
350 ath11k_ahb_ce_irq_enable(ab, i);
354 static void ath11k_ahb_ce_irqs_disable(struct ath11k_base *ab)
358 for (i = 0; i < ab->hw_params.ce_count; i++) {
359 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
361 ath11k_ahb_ce_irq_disable(ab, i);
365 static int ath11k_ahb_start(struct ath11k_base *ab)
367 ath11k_ahb_ce_irqs_enable(ab);
368 ath11k_ce_rx_post_buf(ab);
373 static void ath11k_ahb_ext_irq_enable(struct ath11k_base *ab)
378 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
388 static void ath11k_ahb_ext_irq_disable(struct ath11k_base *ab)
390 __ath11k_ahb_ext_irq_disable(ab);
391 ath11k_ahb_sync_ext_irqs(ab);
394 static void ath11k_ahb_stop(struct ath11k_base *ab)
396 if (!test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
397 ath11k_ahb_ce_irqs_disable(ab);
398 ath11k_ahb_sync_ce_irqs(ab);
399 ath11k_ahb_kill_tasklets(ab);
400 timer_delete_sync(&ab->rx_replenish_retry);
401 ath11k_ce_cleanup_pipes(ab);
404 static int ath11k_ahb_power_up(struct ath11k_base *ab)
406 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
411 ath11k_err(ab, "failed to boot the remote processor Q6\n");
416 static void ath11k_ahb_power_down(struct ath11k_base *ab, bool is_suspend)
418 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
423 static void ath11k_ahb_init_qmi_ce_config(struct ath11k_base *ab)
425 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
427 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
428 cfg->tgt_ce = ab->hw_params.target_ce_config;
429 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
430 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
431 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
434 static void ath11k_ahb_free_ext_irq(struct ath11k_base *ab)
439 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
442 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
449 static void ath11k_ahb_free_irq(struct ath11k_base *ab)
454 if (ab->hw_params.hybrid_bus_type)
455 return ath11k_pcic_free_irq(ab);
457 for (i = 0; i < ab->hw_params.ce_count; i++) {
458 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
461 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
464 ath11k_ahb_free_ext_irq(ab);
471 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
473 ath11k_ahb_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
483 ath11k_ahb_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
495 struct ath11k_base *ab = irq_grp->ab;
498 work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
524 static int ath11k_ahb_config_ext_irq(struct ath11k_base *ab)
526 struct ath11k_hw_params *hw = &ab->hw_params;
532 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
535 irq_grp->ab = ab;
546 if (ab->hw_params.ring_mask->tx[i] & BIT(j)) {
551 if (ab->hw_params.ring_mask->rx[i] & BIT(j)) {
556 if (ab->hw_params.ring_mask->rx_err[i] & BIT(j))
559 if (ab->hw_params.ring_mask->rx_wbm_rel[i] & BIT(j))
562 if (ab->hw_params.ring_mask->reo_status[i] & BIT(j))
565 if (j < ab->hw_params.max_radios) {
566 if (ab->hw_params.ring_mask->rxdma2host[i] & BIT(j)) {
572 if (ab->hw_params.ring_mask->host2rxdma[i] & BIT(j)) {
578 if (ab->hw_params.ring_mask->rx_mon_status[i] & BIT(j)) {
593 irq = platform_get_irq_byname(ab->pdev,
595 ab->irq_num[irq_idx] = irq;
601 ath11k_err(ab, "failed request_irq for %d\n",
610 static int ath11k_ahb_config_irq(struct ath11k_base *ab)
615 if (ab->hw_params.hybrid_bus_type)
616 return ath11k_pcic_config_irq(ab);
619 for (i = 0; i < ab->hw_params.ce_count; i++) {
620 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
622 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
628 irq = platform_get_irq_byname(ab->pdev, irq_name[irq_idx]);
635 ab->irq_num[irq_idx] = irq;
639 ret = ath11k_ahb_config_ext_irq(ab);
644 static int ath11k_ahb_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
651 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
652 entry = &ab->hw_params.svc_to_ce_map[i];
687 static int ath11k_ahb_hif_suspend(struct ath11k_base *ab)
689 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
694 if (!device_may_wakeup(ab->dev))
697 wake_irq = ab->irq_num[ATH11K_PCI_IRQ_CE0_OFFSET + ATH11K_PCI_CE_WAKE_IRQ];
701 ath11k_err(ab, "failed to enable wakeup irq :%d\n", ret);
713 ath11k_err(ab, "failed to send smp2p power save enter cmd :%d\n", ret);
717 ath11k_dbg(ab, ATH11K_DBG_AHB, "device suspended\n");
722 static int ath11k_ahb_hif_resume(struct ath11k_base *ab)
724 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
729 if (!device_may_wakeup(ab->dev))
732 wake_irq = ab->irq_num[ATH11K_PCI_IRQ_CE0_OFFSET + ATH11K_PCI_CE_WAKE_IRQ];
736 ath11k_err(ab, "failed to disable wakeup irq: %d\n", ret);
740 reinit_completion(&ab->wow.wakeup_completed);
750 ath11k_err(ab, "failed to send smp2p power save enter cmd :%d\n", ret);
754 ret = wait_for_completion_timeout(&ab->wow.wakeup_completed, 3 * HZ);
756 ath11k_warn(ab, "timed out while waiting for wow wakeup completion\n");
760 ath11k_dbg(ab, ATH11K_DBG_AHB, "device resumed\n");
797 static int ath11k_core_get_rproc(struct ath11k_base *ab)
799 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
800 struct device *dev = ab->dev;
805 ath11k_err(ab, "failed to get q6_rproc handle\n");
811 ath11k_dbg(ab, ATH11K_DBG_AHB, "failed to get rproc, deferring\n");
819 static int ath11k_ahb_setup_msi_resources(struct ath11k_base *ab)
821 struct platform_device *pdev = ab->pdev;
829 ret = ath11k_pcic_init_msi_config(ab);
831 ath11k_err(ab, "failed to init msi config: %d\n", ret);
837 ath11k_err(ab, "failed to fetch msi_addr\n");
842 msi_addr_iova = dma_map_resource(ab->dev, msi_addr_pa, PAGE_SIZE,
844 if (dma_mapping_error(ab->dev, msi_addr_iova))
847 ab->pci.msi.addr_lo = lower_32_bits(msi_addr_iova);
848 ab->pci.msi.addr_hi = upper_32_bits(msi_addr_iova);
850 ret = of_property_read_u32_index(ab->dev->of_node, "interrupts", 1, &int_prop);
854 ab->pci.msi.ep_base_data = int_prop + 32;
856 for (i = 0; i < ab->pci.msi.config->total_vectors; i++) {
861 ab->pci.msi.irqs[i] = ret;
864 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
869 static int ath11k_ahb_setup_smp2p_handle(struct ath11k_base *ab)
871 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
873 if (!ab->hw_params.smp2p_wow_exit)
876 ab_ahb->smp2p_info.smem_state = qcom_smem_state_get(ab->dev, "wlan-smp2p-out",
879 ath11k_err(ab, "failed to fetch smem state: %ld\n",
887 static void ath11k_ahb_release_smp2p_handle(struct ath11k_base *ab)
889 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
891 if (!ab->hw_params.smp2p_wow_exit)
897 static int ath11k_ahb_setup_resources(struct ath11k_base *ab)
899 struct platform_device *pdev = ab->pdev;
903 if (ab->hw_params.hybrid_bus_type)
904 return ath11k_ahb_setup_msi_resources(ab);
912 ab->mem = mem;
913 ab->mem_len = resource_size(mem_res);
918 static int ath11k_ahb_setup_msa_resources(struct ath11k_base *ab)
920 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
921 struct device *dev = ab->dev;
957 static int ath11k_ahb_ce_remap(struct ath11k_base *ab)
959 const struct ce_remap *ce_remap = ab->hw_params.ce_remap;
960 struct platform_device *pdev = ab->pdev;
964 ab->mem_ce = ab->mem;
972 ab->mem_ce = ioremap(ce_remap->base, ce_remap->size);
973 if (!ab->mem_ce) {
981 static void ath11k_ahb_ce_unmap(struct ath11k_base *ab)
983 if (ab->hw_params.ce_remap)
984 iounmap(ab->mem_ce);
987 static int ath11k_ahb_fw_resources_init(struct ath11k_base *ab)
989 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
990 struct device *host_dev = ab->dev;
1000 if (!ab->hw_params.fixed_fw_mem)
1009 ret = ath11k_ahb_setup_msa_resources(ab);
1011 ath11k_err(ab, "failed to setup msa resources\n");
1028 ath11k_err(ab, "dma configure fail: %d\n", ret);
1036 ath11k_err(ab, "failed to allocate iommu domain\n");
1043 ath11k_err(ab, "could not attach device: %d\n", ret);
1051 ath11k_err(ab, "failed to map firmware region: %d\n", ret);
1059 ath11k_err(ab, "failed to map firmware CE region: %d\n", ret);
1085 static int ath11k_ahb_fw_resource_deinit(struct ath11k_base *ab)
1087 struct ath11k_ahb *ab_ahb = ath11k_ahb_priv(ab);
1094 if (!ab->hw_params.fixed_fw_mem)
1104 ath11k_err(ab, "failed to unmap firmware: %zu\n",
1109 ath11k_err(ab, "failed to unmap firmware CE memory: %zu\n",
1122 struct ath11k_base *ab;
1152 ab = ath11k_core_alloc(&pdev->dev, sizeof(struct ath11k_ahb),
1154 if (!ab) {
1159 ab->hif.ops = hif_ops;
1160 ab->pdev = pdev;
1161 ab->hw_rev = hw_rev;
1162 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL;
1163 platform_set_drvdata(pdev, ab);
1165 ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
1167 ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
1171 ret = ath11k_core_pre_init(ab);
1175 ret = ath11k_ahb_setup_resources(ab);
1179 ret = ath11k_ahb_ce_remap(ab);
1183 ret = ath11k_ahb_fw_resources_init(ab);
1187 ret = ath11k_ahb_setup_smp2p_handle(ab);
1191 ret = ath11k_hal_srng_init(ab);
1195 ret = ath11k_ce_alloc_pipes(ab);
1197 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1201 ath11k_ahb_init_qmi_ce_config(ab);
1203 ret = ath11k_core_get_rproc(ab);
1205 ath11k_err(ab, "failed to get rproc: %d\n", ret);
1209 ret = ath11k_core_init(ab);
1211 ath11k_err(ab, "failed to init core: %d\n", ret);
1215 ret = ath11k_ahb_config_irq(ab);
1217 ath11k_err(ab, "failed to configure irq: %d\n", ret);
1221 ath11k_qmi_fwreset_from_cold_boot(ab);
1226 ath11k_ce_free_pipes(ab);
1229 ath11k_hal_srng_deinit(ab);
1232 ath11k_ahb_release_smp2p_handle(ab);
1235 ath11k_ahb_fw_resource_deinit(ab);
1238 ath11k_ahb_ce_unmap(ab);
1241 ath11k_core_free(ab);
1247 static void ath11k_ahb_remove_prepare(struct ath11k_base *ab)
1251 if (test_bit(ATH11K_FLAG_RECOVERY, &ab->dev_flags)) {
1252 left = wait_for_completion_timeout(&ab->driver_recovery,
1255 ath11k_warn(ab, "failed to receive recovery response completion\n");
1258 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
1259 cancel_work_sync(&ab->restart_work);
1260 cancel_work_sync(&ab->qmi.event_work);
1263 static void ath11k_ahb_free_resources(struct ath11k_base *ab)
1265 struct platform_device *pdev = ab->pdev;
1267 ath11k_ahb_free_irq(ab);
1268 ath11k_hal_srng_deinit(ab);
1269 ath11k_ahb_release_smp2p_handle(ab);
1270 ath11k_ahb_fw_resource_deinit(ab);
1271 ath11k_ce_free_pipes(ab);
1272 ath11k_ahb_ce_unmap(ab);
1274 ath11k_core_free(ab);
1280 struct ath11k_base *ab = platform_get_drvdata(pdev);
1282 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1283 ath11k_ahb_power_down(ab, false);
1284 ath11k_debugfs_soc_destroy(ab);
1285 ath11k_qmi_deinit_service(ab);
1289 ath11k_ahb_remove_prepare(ab);
1290 ath11k_core_deinit(ab);
1293 ath11k_fw_destroy(ab);
1294 ath11k_ahb_free_resources(ab);
1299 struct ath11k_base *ab = platform_get_drvdata(pdev);
1305 ath11k_ahb_remove_prepare(ab);
1307 if (!(test_bit(ATH11K_FLAG_REGISTERED, &ab->dev_flags)))
1310 ath11k_core_deinit(ab);
1313 ath11k_fw_destroy(ab);
1314 ath11k_ahb_free_resources(ab);