Lines Matching defs:ctrl_addr

435 	u32 ctrl_addr = ce_state->ctrl_addr;
472 		ath10k_ce_src_ring_write_index_set(ar, ctrl_addr, write_index);
492 	u32 ctrl_addr = ce_state->ctrl_addr;
551 			ath10k_ce_src_ring_write_index_set(ar, ctrl_addr,
577 	u32 ctrl_addr = pipe->ctrl_addr;
590 			 ath10k_ce_src_ring_write_index_get(ar, ctrl_addr)))
662 	u32 ctrl_addr = pipe->ctrl_addr;
675 	ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
694 	u32 ctrl_addr = pipe->ctrl_addr;
708 	ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
720 	u32 ctrl_addr = pipe->ctrl_addr;
721 	u32 cur_write_idx = ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
730 	ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
1007 	u32 ctrl_addr = ce_state->ctrl_addr;
1023 		read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
1032 		read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
1060 	u32 ctrl_addr = ce_state->ctrl_addr;
1076 		read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
1085 		read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
1234 	u32 ctrl_addr = ce_state->ctrl_addr;
1246 	ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
1291 	u32 ctrl_addr = ce_state->ctrl_addr;
1297 		ath10k_ce_copy_complete_inter_enable(ar, ctrl_addr);
1299 		ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
1301 	ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
1308 	u32 ctrl_addr;
1314 	ctrl_addr = ath10k_ce_base_address(ar, ce_id);
1316 	ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
1317 	ath10k_ce_error_intr_disable(ar, ctrl_addr);
1318 	ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
1363 	u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
1374 	src_ring->sw_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
1379 		ath10k_ce_src_ring_write_index_get(ar, ctrl_addr);
1384 	ath10k_ce_src_ring_size_set(ar, ctrl_addr, nentries);
1385 	ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, attr->src_sz_max);
1386 	ath10k_ce_src_ring_byte_swap_set(ar, ctrl_addr, 0);
1387 	ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
1388 	ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
1404 	u32 nentries, ctrl_addr = ath10k_ce_base_address(ar, ce_id);
1415 	dest_ring->sw_index = ath10k_ce_dest_ring_read_index_get(ar, ctrl_addr);
1418 		ath10k_ce_dest_ring_write_index_get(ar, ctrl_addr);
1423 	ath10k_ce_dest_ring_size_set(ar, ctrl_addr, nentries);
1424 	ath10k_ce_dest_ring_byte_swap_set(ar, ctrl_addr, 0);
1425 	ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
1426 	ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
1692 	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);
1695 	ath10k_ce_src_ring_size_set(ar, ctrl_addr, 0);
1696 	ath10k_ce_src_ring_dmax_set(ar, ctrl_addr, 0);
1697 	ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, 0);
1702 	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);
1705 	ath10k_ce_dest_ring_size_set(ar, ctrl_addr, 0);
1706 	ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, 0);
1891 	ce_state->ctrl_addr = ath10k_ce_base_address(ar, ce_id);