Lines Matching +full:bd +full:- +full:address
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 0x000 - 0x050 TX#0 0x050 - 0x140 RX#0
15 0x140 - 0x190 TX#1 0x190 - 0x280 RX#1
16 0x280 - 0x2D0 TX#2 0x2D0 - 0x3C0 RX#2
17 0x3C0 - 0x410 TX#3 0x410 - 0x500 RX#3
20 000 5FF 1536 Bytes Dual-Port RAM User Data / BDs
21 600 6FF 256 Bytes Dual-Port RAM User Data / BDs
22 700 7FF 256 Bytes Dual-Port RAM User Data / BDs
23 C00 CBF 192 Bytes Dual-Port RAM Parameter RAM Page 1
24 D00 DBF 192 Bytes Dual-Port RAM Parameter RAM Page 2
25 E00 EBF 192 Bytes Dual-Port RAM Parameter RAM Page 3
26 F00 FBF 192 Bytes Dual-Port RAM Parameter RAM Page 4
32 Cable - not used 1
79 SCC_RBASE = 0 // 16-bit RxBD base address
80 SCC_TBASE = 2 // 16-bit TxBD base address
81 SCC_RFCR = 4 // 8-bit Rx function code
82 SCC_TFCR = 5 // 8-bit Tx function code
83 SCC_MRBLR = 6 // 16-bit maximum Rx buffer length
84 SCC_C_MASK = 0x34 // 32-bit CRC constant
85 SCC_C_PRES = 0x38 // 32-bit CRC preset
86 SCC_MFLR = 0x46 // 16-bit max Rx frame length (without flags)
89 PICR = REGBASE + 0x026 // 16-bit periodic irq control
90 PITR = REGBASE + 0x02A // 16-bit periodic irq timing
91 OR1 = REGBASE + 0x064 // 32-bit RAM bank #1 options
92 CICR = REGBASE + 0x540 // 32(24)-bit CP interrupt config
93 CIMR = REGBASE + 0x548 // 32-bit CP interrupt mask
94 CISR = REGBASE + 0x54C // 32-bit CP interrupts in-service
95 PADIR = REGBASE + 0x550 // 16-bit PortA data direction bitmap
96 PAPAR = REGBASE + 0x552 // 16-bit PortA pin assignment bitmap
97 PAODR = REGBASE + 0x554 // 16-bit PortA open drain bitmap
98 PADAT = REGBASE + 0x556 // 16-bit PortA data register
100 PCDIR = REGBASE + 0x560 // 16-bit PortC data direction bitmap
101 PCPAR = REGBASE + 0x562 // 16-bit PortC pin assignment bitmap
102 PCSO = REGBASE + 0x564 // 16-bit PortC special options
103 PCDAT = REGBASE + 0x566 // 16-bit PortC data register
104 PCINT = REGBASE + 0x568 // 16-bit PortC interrupt control
105 CR = REGBASE + 0x5C0 // 16-bit Command register
111 SICR = REGBASE + 0x6EC // 32-bit SI clock route
147 movel %d7, -(%sp) // src and dest must be < 256 MB
151 beq 99f // only 0 - 3 bytes
199 orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size
224 // SCC1=SCCa SCC2=SCCb SCC3=SCCc SCC4=SCCd prio=4 HP=-1 IRQ=64-79
226 movel #0x543, PLX_DMA_0_MODE // 32-bit, Ready, Burst, IRQ
237 movel #1, PLX_MAILBOX_5 // non-zero value = init complete
253 // nothing to do - wait for next event
291 movel ch_status_addr(%d0), %a0 // A0 = port status address
317 movel first_buffer(%d0), %d1 // D1 = starting buffer address
318 movel tx_first_bd(%d0), %a1 // A1 = starting TX BD address
319 movel #TX_BUFFERS - 2, %d2 // D2 = TX_BUFFERS - 1 counter
320 movel #0x18000000, %d3 // D3 = initial TX BD flags: Int + Last
323 bsetl #26, %d3 // TX BD flag: Transmit CRC
326 movel %d1, (%a1)+ // buffer address
330 bsetl #29, %d3 // TX BD flag: Wrap (last BD)
332 movel %d1, (%a1)+ // buffer address
334 // Setup RX descriptors // A1 = starting RX BD address
335 movel #RX_BUFFERS - 2, %d2 // D2 = RX_BUFFERS - 1 counter
338 movel %d1, (%a1)+ // buffer address
343 movel %d1, (%a1)+ // buffer address
346 movel scc_base_addr(%d0), %a1 // A1 = SCC_BASE address
347 movel scc_reg_addr(%d0), %a2 // A2 = SCC_REGS address
362 clrw SCC_PSMR(%a2) // CRC16-CCITT
372 movew #0x0800, SCC_PSMR(%a2) // CRC32-CCITT
382 clrw SCC_PSMR(%a2) // CRC16-CCITT preset 0
392 movew #0x0800, SCC_PSMR(%a2) // CRC32-CCITT preset 0
433 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address
452 movel %d1, %d2 // D1 = D2 = tx_out BD# = desc#
455 addl #STATUS_TX_DESCS, %d2 // D2 = TX desc address
460 movel 4(%d2), %a0 // PCI address
461 lsll #3, %d1 // BD is 8-bytes long
462 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr
464 movel 4(%d1), %a1 // A1 = dest address
466 movew %d2, 2(%d1) // length into BD
487 rx: movel rx_in(%d0), %d1 // D1 = rx_in BD#
488 lsll #3, %d1 // BD is 8-bytes long
489 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address
490 movew (%d1), %d2 // D2 = RX BD flags
492 bne rx_ret // BD still empty
513 addl rx_descs_addr, %d2 // D2 = RX desc address
518 movel 4(%d1), %a0 // A0 = source address
537 bsetl #31, (%d1) // free BD
567 movel %d1, %d2 // D1 = D2 = tx_in BD# = desc#
568 lsll #3, %d1 // BD is 8-bytes long
569 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address
570 movew (%d1), %d3 // D3 = TX BD flags
572 bne tx_end_ret // BD still being transmitted
588 addl #STATUS_TX_DESCS, %d2 // D2 = TX desc address
606 movel %d0, -(%sp)
607 movew %sr, -(%sp)
617 movel %d0, -(%sp)
618 movew %sr, -(%sp)
641 movel %d0, -(%sp)
685 movel %d0, -(%sp)
686 movel %d1, -(%sp)
687 movel %d2, -(%sp)
688 movel %a0, -(%sp)
689 movel %a1, -(%sp)
692 movel #CSRA, %a0 // A0 = CSR address
781 movel %d1, (128 * 1024 - 4)
787 addl #128 * 1024 - 4, %a0
796 movel %d1, (128 * 1024 - 4)
806 movel %a0, -(%a0)
894 firmware_end: // must be dword-aligned