Lines Matching full:d1
301 movel SICR, %d1 // D1 = clock settings in SICR
302 andl clocking_mask(%d0), %d1
305 orl clocking_txfromrx(%d0), %d1
309 orl clocking_ext(%d0), %d1
311 movel %d1, SICR // update clock settings in SICR
317 movel first_buffer(%d0), %d1 // D1 = starting buffer address
326 movel %d1, (%a1)+ // buffer address
327 addl #BUFFER_LENGTH, %d1
332 movel %d1, (%a1)+ // buffer address
338 movel %d1, (%a1)+ // buffer address
339 addl #BUFFER_LENGTH, %d1
343 movel %d1, (%a1)+ // buffer address
352 movel tx_first_bd(%d0), %d1
353 movew %d1, SCC_TBASE(%a1) // D1 = offset of first TxBD
354 addl #TX_BUFFERS * 8, %d1
355 movew %d1, SCC_RBASE(%a1) // D1 = offset of first RxBD
417 movel %d0, %d1
418 lsll #4, %d1 // D1 bits 7 and 6 = port
419 orl #1, %d1
420 movew %d1, CR // Init SCC RX and TX params
440 movel ch_status_addr(%d0), %d1
441 clrl STATUS_OPEN(%d1) // confirm the port is closed
451 movel tx_out(%d0), %d1
452 movel %d1, %d2 // D1 = D2 = tx_out BD# = desc#
461 lsll #3, %d1 // BD is 8-bytes long
462 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr
464 movel 4(%d1), %a1 // A1 = dest address
466 movew %d2, 2(%d1) // length into BD
468 bsetl #31, (%d1) // CP go ahead
471 movel tx_out(%d0), %d1
472 addl #1, %d1
473 cmpl #TX_BUFFERS, %d1
475 clrl %d1
476 tx_1: movel %d1, tx_out(%d0)
487 rx: movel rx_in(%d0), %d1 // D1 = rx_in BD#
488 lsll #3, %d1 // BD is 8-bytes long
489 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address
490 movew (%d1), %d2 // D2 = RX BD flags
505 movew 2(%d1), %d3
518 movel 4(%d1), %a0 // A0 = source address
536 andw #0xF000, (%d1) // clear CM and error bits
537 bsetl #31, (%d1) // free BD
539 movel rx_in(%d0), %d1
540 addl #1, %d1
541 cmpl #RX_BUFFERS, %d1
543 clrl %d1
544 rx_2: movel %d1, rx_in(%d0)
566 movel tx_in(%d0), %d1
567 movel %d1, %d2 // D1 = D2 = tx_in BD# = desc#
568 lsll #3, %d1 // BD is 8-bytes long
569 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address
570 movew (%d1), %d3 // D3 = TX BD flags
577 movel tx_in(%d0), %d1
578 addl #1, %d1
579 cmpl #TX_BUFFERS, %d1
581 clrl %d1
583 movel %d1, tx_in(%d0)
686 movel %d1, -(%sp)
695 movew (%a0), %d1 // D1 = CSR input bits
696 andl #0xE7, %d1 // PM and cable sense bits (no DCE bit)
697 cmpw #STATUS_CABLE_V35 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
699 movew #0x0E08, %d1
703 cmpw #STATUS_CABLE_X21 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
705 movew #0x0408, %d1
709 cmpw #STATUS_CABLE_V24 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
711 movew #0x0208, %d1
715 cmpw #STATUS_CABLE_EIA530 * (1 + 1 << STATUS_CABLE_PM_SHIFT), %d1
717 movew #0x0D08, %d1
721 movew #0x0008, %d1 // D1 = disable everything
725 check_csr_valid: // D1 = mode and IRQ bits
728 orw %d2, %d1 // D1 = all requested output bits
732 cmpw old_csr_output(%d0), %d1
734 movew %d1, old_csr_output(%d0)
735 movew %d1, (%a0) // Write CSR output bits
738 movew (PCDAT), %d1
739 andw dcd_mask(%d0), %d1
741 movew (%a0), %d1 // D1 = CSR input bits
742 andw #~STATUS_CABLE_DCD, %d1 // DCD off
746 movew (%a0), %d1 // D1 = CSR input bits
747 orw #STATUS_CABLE_DCD, %d1 // DCD on
749 andw %d2, %d1 // input mask
751 cmpl STATUS_CABLE(%a1), %d1 // check for change
753 movel %d1, STATUS_CABLE(%a1) // update status
765 movel (%sp)+, %d1
780 movel #0x12345678, %d1 // D1 = test value
781 movel %d1, (128 * 1024 - 4)
788 cmpl (%a0), %d1
795 eorl #0xFFFFFFFF, %d1
796 movel %d1, (128 * 1024 - 4)
797 cmpl (%a0), %d1
804 movel %d0, %d1 // D1 = DBf counter
807 dbfw %d1, ram_test_fill
808 subl #0x10000, %d1
809 cmpl #0xFFFFFFFF, %d1